JPS628017B2 - - Google Patents
Info
- Publication number
- JPS628017B2 JPS628017B2 JP55120965A JP12096580A JPS628017B2 JP S628017 B2 JPS628017 B2 JP S628017B2 JP 55120965 A JP55120965 A JP 55120965A JP 12096580 A JP12096580 A JP 12096580A JP S628017 B2 JPS628017 B2 JP S628017B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- groove
- processing
- amount
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55120965A JPS5745254A (en) | 1980-09-01 | 1980-09-01 | Automatic detector for amount of silicon wafer worked |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55120965A JPS5745254A (en) | 1980-09-01 | 1980-09-01 | Automatic detector for amount of silicon wafer worked |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5745254A JPS5745254A (en) | 1982-03-15 |
JPS628017B2 true JPS628017B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1987-02-20 |
Family
ID=14799383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55120965A Granted JPS5745254A (en) | 1980-09-01 | 1980-09-01 | Automatic detector for amount of silicon wafer worked |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5745254A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3273475D1 (en) * | 1982-10-14 | 1986-10-30 | Ibm Deutschland | Method to measure the thickness of eroded layers at subtractive work treatment processes |
US4468857A (en) * | 1983-06-27 | 1984-09-04 | Teletype Corporation | Method of manufacturing an integrated circuit device |
US4472875A (en) * | 1983-06-27 | 1984-09-25 | Teletype Corporation | Method for manufacturing an integrated circuit device |
US4485553A (en) * | 1983-06-27 | 1984-12-04 | Teletype Corporation | Method for manufacturing an integrated circuit device |
JPS60149133U (ja) * | 1984-03-13 | 1985-10-03 | 日本真空技術株式会社 | エツチングモニタ− |
JPS6178137A (ja) * | 1984-09-26 | 1986-04-21 | Oki Electric Ind Co Ltd | 半導体装置 |
JPH0682636B2 (ja) * | 1985-04-19 | 1994-10-19 | 株式会社日立製作所 | ドライエッチング方法 |
JP2873314B2 (ja) * | 1989-03-30 | 1999-03-24 | 住友シチックス株式会社 | 半導体基板の研磨方法及びその装置 |
JP3287798B2 (ja) | 1997-12-17 | 2002-06-04 | レンゴー株式会社 | 球状セルロース微粒子の製造方法 |
JP6977509B2 (ja) * | 2017-11-29 | 2021-12-08 | 株式会社デンソー | 半導体基板の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3754730A (en) * | 1972-05-01 | 1973-08-28 | Refrigerating Specialties Co | Pressure refrigerant regulator |
JPS52125451U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1976-03-19 | 1977-09-24 |
-
1980
- 1980-09-01 JP JP55120965A patent/JPS5745254A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5745254A (en) | 1982-03-15 |