JPS6279658A - Manufacture of resistance element in semiconductor device - Google Patents
Manufacture of resistance element in semiconductor deviceInfo
- Publication number
- JPS6279658A JPS6279658A JP22063285A JP22063285A JPS6279658A JP S6279658 A JPS6279658 A JP S6279658A JP 22063285 A JP22063285 A JP 22063285A JP 22063285 A JP22063285 A JP 22063285A JP S6279658 A JPS6279658 A JP S6279658A
- Authority
- JP
- Japan
- Prior art keywords
- ion implantation
- resistance value
- region
- active layer
- converging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造において、半導体基板表面
部に抵抗素子を形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming a resistance element on a surface portion of a semiconductor substrate in manufacturing a semiconductor device.
第2図A −0はこのような抵抗素子の従来の製造方法
の主要段階における状態を示す平面図で、まず、半導体
基板(1)の表面部の一部にイオン注入。FIG. 2A-0 is a plan view showing the main stages of a conventional manufacturing method for such a resistance element. First, ions are implanted into a part of the surface of a semiconductor substrate (1).
及びアニーリングを施して活性層(2)を形成し、その
両端部にオーミック接触するオーミック電極(3)を形
成する(第1図A)。次に、その抵抗値を測定し、上記
活性層12)の一部をエツチングして所望の抵抗値にす
べきエツチング領域の位置、大きさを計算決定し、上記
活性層(2)及びオーミック電極(3)の上を含めて半
導体基板(1)の全上面にレジスト膜C4)を形成した
後、上記エツチング領域に対応する開口(5)を形成す
る(第2図B)。その後に上記開口(fi)を有するレ
ジスト膜(4)をマスクとして半導(4)を除去する(
第2図O)。このように、活性層(2)の中央部の幅を
狭くして抵抗値を大きくすることによって全体の抵抗値
を制御して所望の抵抗素子が得られる。and annealing to form an active layer (2), and ohmic electrodes (3) in ohmic contact are formed at both ends of the active layer (2) (FIG. 1A). Next, measure the resistance value, calculate and determine the position and size of the etched region where a part of the active layer 12) should be etched to obtain the desired resistance value, and After forming a resist film (C4) on the entire upper surface of the semiconductor substrate (1) including the top of (3), an opening (5) corresponding to the etching region is formed (FIG. 2B). After that, the semiconductor (4) is removed using the resist film (4) having the opening (fi) as a mask (
Figure 2 O). In this way, by narrowing the width of the central portion of the active layer (2) and increasing the resistance value, the overall resistance value can be controlled and a desired resistance element can be obtained.
従来の方法ではレジスト膜(4)の開口(5)のパター
ンの位置は±1μm以下の精度で合わせることが困難で
あり、正確に抵抗値を制御することが困難であった。ま
た、異なるエツチングノぜターン(6)の形状の抵抗に
対してはレジスト膜(4)の開口(5)の位置。In the conventional method, it is difficult to match the position of the pattern of the opening (5) in the resist film (4) with an accuracy of ±1 μm or less, and it is difficult to accurately control the resistance value. Also, the position of the opening (5) in the resist film (4) for resistors with different etching nozzle (6) shapes.
大きさをそれぞれ変える必要があり、第2図B。It is necessary to change the size of each, as shown in Figure 2B.
0に示す工程を異なるパターン形状の抵抗に対して繰り
返し行わなければならず工程が長くなるなどの問題点が
あった。There was a problem that the process shown in No. 0 had to be repeated for resistors with different pattern shapes, resulting in a long process.
この発明は上記のような間領点を解消するためになされ
たもので、正確で簡単に抵抗値を制御出来る半導体装置
における抵抗素子の*漬方法を得ることを目的とする。This invention has been made to eliminate the above-mentioned problems, and an object thereof is to provide a method for dipping a resistor element in a semiconductor device, which can accurately and easily control the resistance value.
この発明に係る抵抗素子の製造方法では、活性層中に集
束イオンビームによりイオン注入を行い、絶縁層を形成
するようにしたものである。In the method for manufacturing a resistance element according to the present invention, ions are implanted into the active layer using a focused ion beam to form an insulating layer.
この発明における半導体装置における抵抗素子の製造方
法では集束イオンビームで注入された領域が絶縁層化さ
れ、これによって抵抗値を制御することが出来る。In the method for manufacturing a resistive element in a semiconductor device according to the present invention, a region implanted with a focused ion beam is made into an insulating layer, thereby making it possible to control the resistance value.
第1図A、Bはこの発明の一実施例の主要段階における
状態を示す平面図で、まず、GaA3基板(1)の上に
81のイオン注入、アニールを行ない活性層(21fi
?形成し、活性層(2)に接触する様にAumGe1蒸
着し、リフトオフ法によってパターニングを行い、その
後熱処理を行なってオーミック電極(3)全形成する(
第1図A)。この抵抗値を測定し、所望の抵抗値との差
から絶縁層化すべき領域(7)全決定する。そして、た
とえば200keVに加速したBeの集束イオンビーム
をイオン注入領域(7)へ照射する。この時イオン注入
された部分が絶縁領域(7)になる。(fJI、1図B
)
上記実施例ではGaAa基板を用いたがその他、Slま
たは他の鷹−マ族、n−w族半導体であっても良い。更
に、集束イオンビームとして200meV −のBe
t−用いたが、その他の絶縁Nを形成出来るものなら何
であっても良い。FIGS. 1A and 1B are plan views showing the main stages of an embodiment of the present invention. First, ions 81 are implanted and annealed onto a GaA3 substrate (1), and an active layer (21fi) is implanted and annealed.
? AumGe1 is deposited in contact with the active layer (2), patterned by a lift-off method, and then heat treated to completely form the ohmic electrode (3).
Figure 1A). This resistance value is measured, and the entire region (7) to be formed into an insulating layer is determined based on the difference from the desired resistance value. Then, the ion implantation region (7) is irradiated with a Be focused ion beam accelerated to, for example, 200 keV. The ion-implanted portion at this time becomes an insulating region (7). (fJI, Figure 1B
) Although a GaAa substrate was used in the above embodiment, it may also be made of Sl or other Taka-Ma group or N-W group semiconductors. Furthermore, Be of 200 meV − is used as a focused ion beam.
Although t- is used, any other material that can form the insulating layer N may be used.
以上のようにこの発明によれば電気的に偏向可能な集束
イオンビームを用いるので、正確にイオン注入領域を形
成することが出来、精度の高い抵抗値をイ(トろことが
出来る。また集束イオンビームでは任意のパターンの描
画が出来るため、異なったパターンの活性層を有する抵
抗に対しても簡単に対応出来る。またレジスト?用いな
いので工程が短縮される効果がある。As described above, since an electrically deflectable focused ion beam is used, the ion implantation region can be formed accurately and the resistance value can be determined with high precision. Since an arbitrary pattern can be drawn using an ion beam, it can easily be applied to resistors having active layers with different patterns.Furthermore, since no resist is used, the process can be shortened.
@1図はこの発明の一実施例を説明する平面図、第2図
は従来の工程を説明する平面図である。
図において、(1)は半導体基板、(2)は活性層、(
3)けオーミック電極、(7)は絶縁領域である。
なお、図中、同一符号は同一、又は相当部分を示す。Figure 1 is a plan view illustrating an embodiment of the present invention, and Figure 2 is a plan view illustrating a conventional process. In the figure, (1) is a semiconductor substrate, (2) is an active layer, (
3) ohmic electrode, (7) is an insulating region. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
層を形成し、この活性層の両端部においてそれぞれオー
ミック接触するオーミック電極を形成する工程、及び上
記活性層の一部に所要のイオンを集束イオンビームによ
つて注入し当該イオン注入部を絶縁領域とし所望の抵抗
値の抵抗素子を得る工程を備えたことを特徴とする半導
体装置における抵抗素子の製造方法。(1) A process of forming an active layer that constitutes a resistance element on the surface of a semiconductor substrate, forming ohmic electrodes that make ohmic contact at both ends of the active layer, and injecting necessary ions into a part of the active layer. 1. A method for manufacturing a resistive element in a semiconductor device, comprising the step of implanting a resistive element using a focused ion beam and using the ion implanted portion as an insulating region to obtain a resistive element having a desired resistance value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60220632A JPH0824160B2 (en) | 1985-10-03 | 1985-10-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60220632A JPH0824160B2 (en) | 1985-10-03 | 1985-10-03 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6279658A true JPS6279658A (en) | 1987-04-13 |
JPH0824160B2 JPH0824160B2 (en) | 1996-03-06 |
Family
ID=16754011
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60220632A Expired - Lifetime JPH0824160B2 (en) | 1985-10-03 | 1985-10-03 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0824160B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02119244A (en) * | 1988-10-28 | 1990-05-07 | Nec Corp | Manufacture of semiconductor integrated circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4837232A (en) * | 1971-09-15 | 1973-06-01 | ||
JPS4921754A (en) * | 1972-04-20 | 1974-02-26 | ||
JPS4921597A (en) * | 1971-06-15 | 1974-02-26 | ||
JPS5160484A (en) * | 1974-11-22 | 1976-05-26 | Mitsubishi Electric Corp | Handotaisochino seizohoho |
-
1985
- 1985-10-03 JP JP60220632A patent/JPH0824160B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4921597A (en) * | 1971-06-15 | 1974-02-26 | ||
JPS4837232A (en) * | 1971-09-15 | 1973-06-01 | ||
JPS4921754A (en) * | 1972-04-20 | 1974-02-26 | ||
JPS5160484A (en) * | 1974-11-22 | 1976-05-26 | Mitsubishi Electric Corp | Handotaisochino seizohoho |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02119244A (en) * | 1988-10-28 | 1990-05-07 | Nec Corp | Manufacture of semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0824160B2 (en) | 1996-03-06 |
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