JPS61228662A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61228662A JPS61228662A JP6932185A JP6932185A JPS61228662A JP S61228662 A JPS61228662 A JP S61228662A JP 6932185 A JP6932185 A JP 6932185A JP 6932185 A JP6932185 A JP 6932185A JP S61228662 A JPS61228662 A JP S61228662A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask material
- forming
- region
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- -1 boron ions Chemical class 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- PPTSBERGOGHCHC-UHFFFAOYSA-N boron lithium Chemical compound [Li].[B] PPTSBERGOGHCHC-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置の製造方法に関し、特に抵抗素子
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a resistive element.
（従来の技術）
従来、半導体装置に使用される抵抗素子の一つに半導体
基板に不純物をイオン注入して形成する方法がある。こ
の方法では不純物の濃度を適度に設定することにエリ任
意の比抵抗の抵抗素子を形成することが出来る。(Prior Art) Conventionally, one method of forming a resistance element used in a semiconductor device is to implant impurity ions into a semiconductor substrate. In this method, a resistance element having an arbitrary specific resistance can be formed by setting the impurity concentration appropriately.
８ｇ５図は従来の抵抗素子の一例の平面図、第６図（ａ
）〜（Ｃ）は第５図に示す抵抗素子の製造方法を説明す
るための工程順に示し比断面図である。Figure 8g5 is a plan view of an example of a conventional resistance element, and Figure 6 (a
) to (C) are ratio cross-sectional views shown in the order of steps for explaining the method of manufacturing the resistance element shown in FIG. 5.
まず、第６図（ａ）に示すエリにｎ型シリコン基板２０
１にシリコン酸化膜２０２を形成する０次に、フォトレ
ジスト等の第１のマスク材２０３に１って、抵抗形成領
域の形状１位置を設足し、イオン注入法に工９、シリコ
ン基板２０１に第１の抵抗素子領域２０７’ｉ形成する
。First, an n-type silicon substrate 20 is placed on the area shown in FIG. 6(a).
Forming a silicon oxide film 202 in Step 1 Next, a resistor forming region is formed at a position 1 in a first mask material 203 such as a photoresist, and then an ion implantation method is applied to the silicon substrate 201. A first resistance element region 207'i is formed.
次に、１ｔ６図（ｂ）に示すエリに、！１のマスク材２
０３を除去し、続いて、８［２のマスク材２０５を形成
することに工９、第２の抵抗形成領域の形状配置を設定
し、イオン注入法に１９基板２０１にＩＥ２の抵抗素子
領域２０９を形成する。Next, to Eri shown in 1t6 figure (b),! 1 mask material 2
03 is removed, and then a mask material 205 of 8[2 is formed, step 9 is set, the shape and arrangement of the second resistor forming region is set, and a resistive element region 209 of IE2 is formed on the substrate 201 by ion implantation. form.
次に、纂６図（Ｃ）に示すように、ｆｊｇ２のマスク材
２０５１に除去する。Next, as shown in Figure 6 (C), a mask material 2051 of fjg2 is removed.
次に、ｉ４５図に示すように、各抵抗素子領域の両端の
シリコン酸化膜を選択的に除去して、コンタクト穴２１
０ｔ−形成する０次に、電極配線２１１を形成すること
にエリ抵抗素子が形成される。Next, as shown in Figure i45, the silicon oxide film at both ends of each resistive element region is selectively removed, and
Next, after forming the electrode wiring 211, an edge resistance element is formed.
（発明が解決しょうとする問題点）
上述の工うな形成方法では、ＩＥ６図（ｂ）に示すよう
に、第２のマスク材２０５を形成する際に、第１の抵抗
素子領域２０７０段差が形成されていないので第１の抵
抗素子領域２０７に対して直接的に位置合せを行なうこ
とが不可能である０位置ずれに工っでは抵抗領域２０７
と２０９間の接近による耐圧劣化や著しい場合は短絡を
起こすという欠点がある。(Problems to be Solved by the Invention) In the above-mentioned method for forming a hole, a step is formed in the first resistive element region 2070 when forming the second mask material 205, as shown in FIG. Therefore, it is impossible to directly align the resistor region 207 with respect to the first resistor element region 207.
There is a drawback that the close proximity between 209 and 209 causes deterioration of withstand voltage and, in severe cases, short circuit.
従って、第１の抵抗領域２０７と纂２の抵抗領域２０９
の間隔Ｗは第１のマスク材２０３の位置ずれに対する余
裕と、第２のマスク材２０５の位置ずれに対する余裕を
加味して設定しなければならず、抵抗素子形成領域の高
密度化の障害となっているという問題があった。Therefore, the first resistance region 207 and the second resistance region 209
The interval W must be set by taking into account allowances for misalignment of the first mask material 203 and misalignment of the second mask material 205, which may be an obstacle to increasing the density of the resistive element forming area. There was a problem that
本発明の目的は、上記従来の欠点を解決し、比抵抗の異
なる抵抗素子を高密度に安定的に半導体基板に形成する
方法を含む半導体装置の製造方法を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a method for manufacturing a semiconductor device including a method for stably forming resistive elements having different specific resistances in a high density on a semiconductor substrate.
（問題点ｔ−解決するための手段）
本発明の半導体装置の製造方法は、表面を絶縁膜で覆わ
れた第１導電形の半導体基板上に第１の膜を被着し抵抗
素子形成領域に開口部を形成する工程と、所定の位置の
前記開孔部ｔ−榎う工うに構２の膜を形成する工程と、
前記第１の膜と第２の膜をマスクとして、イオン注入法
に工り、前記半導体基板に反対導電形の第１の不純物層
領域を形成する工程と、前記第２の膜を除去して続いて
少なくとも前記１！１の不純物層領域を覆う工うに、＠
３の膜を形成する工程と、Ｗ！ｉ１の膜と纂３の膜をマ
スクとしてイオン注入法に１９、前記半導体基板に反対
導電形の８１の不純物層とは比抵抗の異なる鷹２の不純
物層を形成する工程とを含んで構成される。(Problem t - Means for Solving) A method for manufacturing a semiconductor device of the present invention includes depositing a first film on a semiconductor substrate of a first conductivity type whose surface is covered with an insulating film, and forming a resistive element forming area. a step of forming an opening at a predetermined position, and a step of forming a membrane of the opening section 2 at a predetermined position;
forming a first impurity layer region of opposite conductivity type in the semiconductor substrate by using the first film and the second film as masks, and removing the second film; Then, to cover at least the 1!1 impurity layer region, @
Step 3 of forming the film and W! 19, using the film i1 and the film 3 as masks, using an ion implantation method, and forming an impurity layer 2 on the semiconductor substrate having a resistivity different from that of the impurity layer 81, which is of an opposite conductivity type. Ru.
ここで、第１の膜として多結晶シリコンまたはアルミニ
ウムが選ばれ、第２及び第３の膜としてフォトレジスト
が選ばれる。また、ＩＥｌの膜が多結晶シリコンである
とき、第２及び第３の膜としてアルミニウムを用いるこ
とができる。Here, polycrystalline silicon or aluminum is selected as the first film, and photoresist is selected as the second and third films. Furthermore, when the IEl film is polycrystalline silicon, aluminum can be used as the second and third films.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
ＩＥ ｉ 図（ａ）、 （ｂ）乃至ｗＥ４図（ａ）、
（ｂ）Ｗ本発明の一実施例全説明するための工程順に示
した平面図及び断面図である。IE i Figures (a), (b) to wE4 (a),
(b) W is a plan view and a cross-sectional view showing the steps in order to fully explain an embodiment of the present invention.
まず、第１図（１１，（ｂ）に示す工うに、ｎ型半尋体
基板１０１上にシリコン酸化膜１０２ｔ−２００ＯＡの
厚さに形成する１次に、全面に第１のマスク材としてア
ルミニウム１ｌａ１０３ｔ−５００ＯＡの厚さに被着さ
せる。続いて、フォトエツチング法によって抵抗素子形
成領域上のアルミニウム膜１０３を選択的に除去するこ
とによって開孔部１０４．１０５を形成する。First, in the process shown in FIG. 1 (11, (b)), a silicon oxide film is formed on the n-type half-layer substrate 101 to a thickness of 102t-200OA, and then aluminum is coated on the entire surface as a first mask material. The aluminum film 103 is deposited to a thickness of 1 la 10 3 t-500 OA.Then, the aluminum film 103 on the resistor element formation region is selectively removed by photoetching to form openings 104 and 105.
次に、第２図（ａ）、 （ｂ）に示す工うに、開孔部１
０５を覆うように、第２のマスク材としてフオトレジス
）１０６ｔ−形成し、続いてイオン注入法にＪ：リホウ
素１ｋ１．０Ｘ１０ ｃｍ 打込むことにＬＤ％鷹
１の抵抗素子領域１０７を形成する。Next, as shown in FIGS. 2(a) and 2(b), the opening 1 is
A photoresist (photoresist) 106t is formed as a second mask material so as to cover the resistor element region 106t as a second mask material, and then a resistive element region 107 with an LD% of 1 is formed by implanting 1k1.0×10 cm of lithium boron using an ion implantation method.
次に、第３図（ａ）、 （ｂ）に示す工うに、フォトレ
ジスト１０６を除去し、続いて開孔部１０４を覆う工う
に、第３のマスク材としてフォトレジスト１０８を形成
する。続いてイオン注入に工り、第１のイオン注入とは
異なるドーズ量のホウ素ｔ”ＬＯＸｌｏ”ｃｍ−”＠度
打込むことにエフ、第２の抵抗素子領域１０９ｔ−形成
する。Next, as shown in FIGS. 3A and 3B, the photoresist 106 is removed, and then a photoresist 108 is formed as a third mask material to cover the opening 104. Subsequently, ion implantation is performed, and a second resistance element region 109t- is formed by implanting boron at a dose t"LOXlo"cm-" which is different from the first ion implantation.
第４図（ａ）、 （ｂ）に示す工うに、フォトレジスト
１０８を除去し、続いてアルミニウム膜１０２ｔ−除去
する０次に、イ、オン注入された不純物層の活性化の為
に９００℃でアニールを行ない、抵抗素子領域の両端の
シリコン酸化膜１０２ｔ−選択的に除去して電極取出し
、開孔部１１０會形成し、次にアルミニウム電極１１１
ｔ−形成することに工って、抵抗素子が形成される。In the process shown in FIGS. 4(a) and 4(b), the photoresist 108 is removed, and then the aluminum film 102t is removed. The silicon oxide film 102t at both ends of the resistive element region is selectively removed to take out the electrode, an opening 110 is formed, and then an aluminum electrode 111 is formed.
A resistive element is formed by forming the resistive element.
上記実施例において［、Ｉ！１のマスク材にアルミニウ
ム、第２．＠３のマスク材に７オトレジストｔ−用いた
が、他のマスク材として多結晶シリコン膜なども適用で
きる。In the above embodiment, [,I! The first mask material is aluminum, the second mask material is aluminum. Although 7-otoresist t- was used as the mask material in @3, other mask materials such as polycrystalline silicon films can also be used.
上記実施例において、抵抗素子領域１０７と１０９の距
離Ｗは第１図（ｂ）に示す工うに、アルミニウム膜１０
３のパターンで決定されており、従来の製造方法の欠点
である位置ずれによる距離Ｗの短縮に伴う、抵抗領域間
の耐圧劣化や短絡が解決されている。In the above embodiment, the distance W between the resistive element regions 107 and 109 is as shown in FIG.
3, which solves the drawbacks of conventional manufacturing methods, such as deterioration in breakdown voltage and short circuits between resistance regions due to shortening of distance W due to positional deviation.
（発明の効果］
以上説明し友工うに、本発明は、第１のマスク材のバタ
ーニングに工って、すべての抵抗領域の形状及び形成位
置を決定している為に、比抵抗の異なる抵抗の間隔を正
確に制御することが可能であり、かつ、十分に短縮して
も安定し比特性の抵抗素子を得ることができる。(Effects of the Invention) As explained above, the present invention utilizes the patterning of the first mask material to determine the shapes and formation positions of all the resistance regions. It is possible to accurately control the distance between the resistors, and even if the resistor spacing is sufficiently shortened, a resistive element with stable specific characteristics can be obtained.
従って、抵抗素子の高密度つ′ｔす、半導体装置の集積
度の同上に効果がある。Therefore, it is effective to increase the density of resistive elements and the degree of integration of semiconductor devices.
第１図（ａ）、 （ｂ）乃至薦４図（ａ）、 （ｂ）ｆ
１本発ｑｏ−実施例を説明するための工程順に示し比平
面図及び断面図、纂５図は従来の抵抗素子の一例の平面
図、渠６図（ａ）〜（Ｃ）は第５図に示す抵抗素子の製
造方法を説明するための工程順に示し友断面図である。
１０１・・・・・・半導体基板、１０２・・・・・・シ
リコン酸化膜、１０３・・・・・・アルミニウム膜、１
０４，１０５・・・・・・開孔部、１０６・・・・・・
フォトレジスト、１０７・・・・・・第１の抵抗素子領
域、１０８・・・・・・フォトレジスト、１０９・・・
・・・第２の抵抗素子領域、１１０・・・・・・開孔ｉ
、１１１・・・・・・アルミニウム電極、２０１・・・
・・・シリコン基板、２０２・・・・・・シリコン酸化
膜、２０３・・・・・・第１のマスク材（アルミニウム
］、２０５・・・・・・第２のマスク材、２０７・・・
・・・第１の抵抗素子領域、２０９・・・・・・第２の
抵抗素子領域、２１０・・・・・・コンタクト穴、２１
１−・−アルミニウム電極。
御４図Figure 1 (a), (b) to Recommended Figure 4 (a), (b)f
Figure 5 is a plan view of an example of a conventional resistance element, Figure 6 (a) to (C) are Figure 5. FIGS. 3A and 3B are cross-sectional views shown in order of steps for explaining the method for manufacturing the resistance element shown in FIGS. 101...Semiconductor substrate, 102...Silicon oxide film, 103...Aluminum film, 1
04,105...Opening part, 106...
Photoresist, 107...First resistance element region, 108...Photoresist, 109...
...Second resistance element region, 110...Opening i
, 111...aluminum electrode, 201...
... Silicon substrate, 202 ... Silicon oxide film, 203 ... First mask material (aluminum), 205 ... Second mask material, 207 ...
...First resistance element region, 209...Second resistance element region, 210...Contact hole, 21
1-.-Aluminum electrode. Figure 4
Claims (4)
上に第１の膜を被着し抵抗素子形成領域に開口部を形成
する工程と、所定の位置の前記開孔部を覆うように第２
の膜を形成する工程と、前記第１の膜と第２の膜をマス
クとして、イオン注入法により、前記半導体基板に反対
導電形の第１の不純物層領域を形成する工程と、前記第
２の膜を除去して続いて、少なくとも前記第１の不純物
層領域を覆うように、第３の膜を形成する工程と、第１
の膜と第３の膜をマスクとして、イオン注入法により、
前記半導体基板に反対導電形の第１の不純物層とは比抵
抗の異なる第２の不純物層を形成する工程を含むことを
特徴とする半導体装置の製造方法。(1) A step of depositing a first film on a semiconductor substrate of a first conductivity type whose surface is covered with an insulating film and forming an opening in a resistor element formation region, and forming the opening at a predetermined position. second to cover
forming a first impurity layer region of opposite conductivity type in the semiconductor substrate by ion implantation using the first film and the second film as masks; forming a third film so as to cover at least the first impurity layer region;
By using the ion implantation method using the film and the third film as masks,
A method of manufacturing a semiconductor device, comprising the step of forming a second impurity layer having a resistivity different from that of the first impurity layer of an opposite conductivity type on the semiconductor substrate.
び第３の膜がフォトレジスト膜である特許請求の範囲第
（１）項記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim (1), wherein the first film is a polycrystalline silicon film, and the second film and third film are photoresist films.
３の膜がフォトレジスト膜である特許請求の範囲第（１
）項記載の半導体装置の製造方法。(3) Claim No. 1, wherein the first film is aluminum, and the second film and the third film are photoresist films.
) The method for manufacturing a semiconductor device according to item 2.
び第３の膜がアルミニウムである特許請求の範囲第（１
）項記載の半導体装置の製造方法。(4) Claim No. 1 in which the first film is a polycrystalline silicon film, and the second film and the third film are aluminum.
) The method for manufacturing a semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6932185A JPS61228662A (en) | 1985-04-02 | 1985-04-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6932185A JPS61228662A (en) | 1985-04-02 | 1985-04-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61228662A true JPS61228662A (en) | 1986-10-11 |
Family
ID=13399169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6932185A Pending JPS61228662A (en) | 1985-04-02 | 1985-04-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61228662A (en) |
-
1985
- 1985-04-02 JP JP6932185A patent/JPS61228662A/en active Pending
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