JPS6278663A - Control system for processor bus - Google Patents

Abstract

PURPOSE:To economically and efficiently share a processor bus by allowing other devices to use the processor bus concerned when one processor does not use said processor bus. CONSTITUTION:Instruction codes a1 comprising an instruction executed by the processor 1 is converted into a bus use period code (c) and further into a bus use period signal (d), both of which control the conduction of gates 9 and 10 and how the processor bus 4 is used by other devices as a bus nonuse period signal (e). As a result, the processor 1 is connected to the bus 4 only during the execution period of the instruction, that is, the execution period using the bus 4, and is disconnected from the bus 4 during the execution period in nonuse of the bus 4. On the other hand, the execution period when the processor 1 does not use the bus 4 is transmitted to other processors, which can be allowed to use the bus 4 during said period. Accordingly the bus 4 can be economically and efficiently shared with the processor 4 and other processors.

Description

[Detailed Description of the Invention] [Summary] In an information processing system in which a processor and other devices share a processor bus, when the processor executes a program, the unused cycles of the processor bus of the processor are determined from read instruction codes. This information is transmitted to other devices to permit the other devices to use the bus.

[Industrial application field]

The present invention provides an information processing system in which a processor bus control system that enables a processor and other devices to share a processor bus economically and efficiently enables a processor to communicate with a memory and an input/output control device via a processor bus. In an information processing system that transfers information between
For example, the processor bus may also be shared by other processors.

In such an information processing system, there is a strong demand for a means that allows a processor and other devices to share a processor bus as economically and efficiently as possible.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional processor bus control method.

In FIG. 3, a processor 1, a memory 2 for storing various data, and an input/output control device 3 for controlling data transfer to various input/output devices (not shown) are connected by a processor bus 4.

Processor 1 communicates with memory 2 via processor bus 4.
Alternatively, data is exchanged with the input/output control device 3.

Furthermore, the processor bus 4 includes a memory 2 and an input/output fftl.
A direct memory access device W5 is connected to the f control device 3 in order to enable data transfer without going through the processor 1.

The direct memory access device 5 stops the processor lJ1 when transferring data between the memory 2 and the input/output control device 3! The processor 1 disconnects the memory 2 from the bus 4 based on instructions given from the processor 1.
After data transfer between the processor 1 and the input/output control device 3 is executed, the processor 1 is stopped and released.

[Problem that the invention seeks to solve]

As is clear from the above description, in some conventional processor bus control systems, in order to share the processor bus 4 between the processor 1 and other devices, it is necessary to provide complex logic such as the direct memory access device W5. Therefore, there was a risk that the economic efficiency of the information processing system would be impaired. Also, while other devices are using the processor bus 4,
Processor I must be stopped, which may reduce processing efficiency.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, a program to be executed by a processor 1 is stored, and identification means 100 identifies a storage address of an instruction code a1 of an instruction constituting the program, and reading is performed from the storage address identified by the identification means 100. A converting means 200 is provided for converting the instruction code a1 that has been executed into a bus non-use period signal e indicating whether or not the processor bus 4 is used within the instruction execution period.

[Effect]

That is, according to the present invention, it is possible to allow other devices to use the processor bus during the execution cycle of instructions in which the processor does not use the processor bus, and it is possible to share the processor bus economically and efficiently. becomes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a processor bus control method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the memo IJ 6 is used as the identification means +00.
is provided, and a memo IJ 7 is provided as the conversion means 200.
A shift register 8 and an inverter 11 are provided.

The memory 6 stores programs executed by the processor l. A recognition code is stored at the address where the instruction code a1 of each instruction that makes up the program is stored, and no recognition code is stored at the address where data such as a2 other than instruction need a1 is stored. .

On the other hand, in the memory 7, a bus usage cycle code C indicating whether or not the processor bus 4 is used in the execution cycle of the instruction read from the memory 6 is stored with the instruction code a1 as the storage address. For example, if the execution cycle of an instruction having instruction code a1 is three cycles, and the processor bus 4 is not used in the first cycle and the second cycle, but the processor bus 4 is used in the third cycle, the bus usage cycle code C is (0,0,1)
is set to

When the processor l executes an instruction, the storage address of the instruction code a1 is first transmitted to the memory 6 from the address terminal, and the instruction code a1 and the recognition code are read from the memory 6.

The instruction code a1 is transmitted to the data terminal of the processor 1, and is also transmitted to the memory 7 as a storage address, and the recognition code is transmitted to the shift register 8.

The memory 7 extracts the bus usage cycle code C stored at the storage address corresponding to the transmitted instruction code a1, and transmits it to the shift register 8.

The shift register B stores the bus use cycle code C transmitted from the memory 7 in parallel when the recognition code is transmitted from the memory 6.

The shift register 8 increments the stored bus usage cycle code C by one digit in synchronization with the clock signal ck that controls the execution cycle of the processor 1, and outputs it to the gate 9 and the serial bus usage cycle signal d. 10 and inverter 11.

Gates 9 and 10 are configured such that the bus use period signal d is logic “1”.
”, that is, when the processor 1 uses the processor bus 4 in the same execution cycle as 1υ1 and becomes conductive, and the bus use rWI signal d is logic “0”, that is, the processor 1 does not use the processor bus 4. It enters a shutdown state in synchronization with the execution cycle.

On the other hand, the inverter 11 creates a bus non-use period signal e by inverting the logic value of the bus use period signal d, and transmits it to another device (not shown) that shares the processor bus 4.

In other devices, the transmitted bus non-use period signal e is a logic "
It is determined that the processor bus 4 is usable when the bus non-use cycle signal e indicates logic "0", and it is determined that the processor bus 4 is unusable when the bus non-use periodic signal e indicates logic "0".

Next, processor 1 sends data etc. a to address end T-.
When the storage address of 2 is transmitted to the memory 6, only data a2 is read from the memory 6.

The data etc. a2 is transmitted to the data terminal of the processor 1 and is also transmitted to the memory 7 as a storage address, and from the memory 7, the stored content stored at the storage address corresponding to the data etc. a2 is extracted and shifted. However, since the recognition code is not transmitted from the memory 6 to the shift register 8, the storage contents transmitted from the memory 7 are not stored.

As is clear from the following explanation, according to this embodiment, the instruction code a1 of the instruction executed by the processor 1 is converted into the bus usage cycle code C1 and further into the bus usage cycle signal d, and the conduction state of the gates 9 and 10 is It also controls the use of the processor bus 4 by other devices as a bus non-use periodic signal e.

As a result, the processor 1 is connected to the processor bus 4 only during the execution cycle in which the processor bus 4 is used, and is disconnected from the processor bus 4 during the execution cycle in which the processor bus 4 is not used. On the other hand, other devices include
An execution cycle in which the processor 1 does not use the processor bus 4 is transmitted, and the processor bus 4 is allowed to be used during that period, so that the processor 1 and other devices can share the processor bus 4 economically and efficiently. becomes possible.

Note that FIG. 2 is merely an m-embodiment of the present invention, and for example, the recognition code is not limited to what is stored corresponding to the instruction code a1, and data other than the instruction need al, etc. Although many other modifications may be considered, such as storing in correspondence with a2, the effect of the present invention remains the same in either case.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, it is possible to allow other devices to use the processor bus during instruction execution cycles in which the processor does not use the processor bus, and the processor bus can be shared economically and efficiently. It becomes possible to do so.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a processor bus control method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional processor bus control method. In the figure, 1 is a processor, 2, 6 and 7 are memories, 3 is an input/output control device, 4 is a processor bus, 5 is a direct memory access device, 8 is a shift register, and 9 is a
and 10 is a gate, 11 is impark, al is an instruction code, a2 is data, etc., b is a recognition code, C is a bus usage cycle code, ck is a clock signal, d is a bus usage cycle signal,
e is a bus failure. 1. Ck is huge. 2 days.

Claims (1)

[Claims] A processor (1) and other devices are connected to a processor bus (4).
), an identification means (100) for storing a program executed by the processor (1) and for identifying a storage address of an instruction code (al) of an instruction constituting the program; The means (100) converts the instruction code (al) read from the identified storage address into a bus non-use cycle signal (e) indicating whether or not the processor bus (4) is used during the execution cycle of the instruction. a conversion means (200), and allows the other device to use the processor bus (4) during an execution cycle in which the processor (1) does not use the processor bus (4). Bus control method.