JPS6276927A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the initial synchronizing lock time when an in-loop frequency division ratio is large by preventing an input clock from being outputted by an AND circuit to the AND circuit of a frequency divider side outputting a frequency-division output discriminated to have a lead phase. CONSTITUTION:When a phase comparator 3 is operated to lead the phase of a comparison frequency FV1, the phase comparator 3 applies phase comparison in the phase of e1-f1 in comparison frequencies FR1, FV1. A control signal phiR descends at the trailing of a phase e1 and rises at the leading of a phase f1 in this case. That is, the phase of comparison frequency FR1 is led more than that of the comparison frequency FV1 by the period of the low level (L) of the control signal phiR. Thus, the phase of the comparison frequency FR1 is retarded equivalently by using the AND circuit 7 and the control signal phiR so as to prevent the input of the input clock to a frequency divider 1 while the control signal phiR is at L thereby placing the phase at the position of the phase e2. Thus, the phase is compared at a phase e2-f2 and the state is brought into a state close to the synchronizing state. Then the input clock and the output clock are synchronized at a phase e4-f4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase synchronization circuit that performs stable synchronization at the start of a phase comparison operation.

BACKGROUND OF THE INVENTION In recent years, phase synchronized circuits that generate a clock M/N times as high as the input bit rate are often used in digital communications to expand the time axis of compressed digital data.

An example of the above-mentioned conventional phase locked circuit will be described below with reference to the drawings. FIG. 2 is a block diagram of a conventional phase locked circuit. 1 is a frequency divider that divides the input clock by N, and FR2 is a comparison frequency that is the output of frequency divider 1. On the other hand, 6 is a voltage controlled oscillator that outputs an output clock, 2 is a frequency divider that divides the output clock by M, and FV2
is the comparison frequency that is the output of frequency divider 2. 3 is comparison frequency F
R2' is a phase comparator that compares the phase at the rising edge of FV2, and φ8 is a control signal that is output when the phase of comparison frequency FR2 is ahead of the phase of comparison frequency FV2 in the phase comparator, and φ is This is a control signal that is output when the phase of the comparison frequency FR□ lags behind the phase of the comparison frequency Fv□ in the phase comparator 3. 4 is a charge pump, 5 is a low-pass filter (hereinafter referred to as P,
) from the charge pump 4, P,
Control signal φ3. to F5. A charge variation based on φ9 is given. (2) This is the control voltage output from the beams, P and F5 to the voltage controlled oscillator 6, and is the control voltage V.

controls the voltage controlled oscillator 6 to synchronize the output clock with the input clock.

The operation of the phase synchronized circuit configured as described above will be explained below. Figures 3 and 4 are out of sync,
Alternatively, this is a time chart of a synchronization pull-in operation for resynchronizing from a state where the input is once cut off, and two types of results shown in both figures can occur depending on the initial state of the phase comparator 3. In addition, each figure is a comparison frequency FR□.

Fv□ control signal φ8. φ and the control voltage vc.

First, FIG. 3 shows a case where the phase comparator 3 operates to delay the phase of the comparison frequency FV2.

In other words, in phase comparator 3, comparison frequency FR2=FV2
Each clock waveform a1-b1. a - b ・・・・・・
The phases are compared at the rising edge of each clock. In the phase relationship between a and -b, the comparison frequency FR□ is delayed in phase from the comparison frequency Fv2, so the control signal φ9 is output from the phase comparator 3 and the control voltage ■. voltage is lowered, and the frequency of the output clock of the voltage controlled oscillation 3 is lowered. And since the comparison frequency FR2 lags behind the phase of the comparison frequency Fv□ even when a 2 '= b 2,
The control signal φヮ is output from the phase comparator 3 and the control voltage ■.

or further lowered and the frequency of the output clock is lowered, a
, 3-b3, the phases match, and operations are thereafter performed in a synchronous state.

Next, FIG. 4 shows a case where the phase comparator 3 operates to advance the phase of the comparison frequency FV2.

That is, in the phase comparator 3, the comparison frequency FR.

This shows a case where the phases are compared at the rising edge of each clock, such as C1-dI% C2-d2 ``'' of FV2. In this case, the comparison frequency FR□ is the comparison frequency Fv
The phase is leading from □, so the control signal φ3 is output from the phase comparator 3, and the control voltage V. works in the direction of increasing the voltage. However, since the limit voltage VC is at the upper limit, it does not change, and the frequency of the output clock also does not change. And cn
-dn phase relationship, the comparison frequency FV2 leads the comparison frequency FR2 in phase, and the control signal φ9 is transmitted to the phase comparator 3.
The control voltage V is output from the control voltage V. is lowered. Then, a synchronous pull-in operation similar to that shown in Fig. 3 is performed, and Cn and 2
-dn + 2 brings it into synchronization state.

The problem that the invention aims to solve However, in the above configuration, FIG.

As shown in FIG. 4, even if the initial phases of comparison frequencies FR□ and Fv□ are the same as al-bl and CI-ao, the phase comparison of C1-dl is performed as the operation of the phase comparator 3. This shows that there are cases where Therefore, since the operations shown in FIGS. 3 and 4 and those in between occur randomly, there is a problem that the synchronization pull-in time is long on average, and synchronization cannot be performed promptly. especially,
If the frequency division ratio M of the frequency divider 2 that divides the frequency by M is increased and the internal frequency division ratio is increased, the loop gain of the phase locked circuit decreases, so the synchronization pull-in time increases and synchronization takes time. There is a problem with this.

In view of the above-mentioned problems, the present invention provides a phase-locked circuit that can significantly shorten the initial synchronization pull-in time when the in-loop frequency division ratio is large.

Means for Solving the Problems In order to solve the above problems, the phase locked circuit of the present invention has the following features:
a first AND circuit whose one input is an input clock;
a first frequency divider that divides the output signal of the first AND circuit; a second AND circuit that receives the output clock of the voltage controlled oscillator as one input; and an output signal of the second AND circuit. The phases of the divided outputs of the second frequency divider and the first and second frequency dividers are compared, and the divided output of the first frequency divider is compared with that of the second frequency divider. a phase comparator that outputs a first control signal that is output when it is ahead of the phase of the frequency-divided output and a second control signal that is output when it is behind the phase of the frequency-divided output; the first of the phase comparators to the other input.
, and a second control signal of the phase comparator is input to the other input of the second AND circuit.

Effect of the present invention With the above-described configuration, the phase comparator outputs an output for a period corresponding to the phase difference of the divided output. ”llll (
In the * issue, the input clock acts on the AND circuit on the divider side that outputs the divided output whose phase is determined to be ahead, so that it is not output from the AND circuit, and is forced to divide. It works to delay the phase of the frequency output by the amount that it is leading.
By establishing a phase relationship close to a synchronous state in the next phase comparison operation, synchronization can be stably achieved in a short time no matter what the phase relationship is.

Embodiment Hereinafter, a phase locked circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase locked loop circuit which is an embodiment of the present invention. Common numbers and symbols used in FIGS. 1 and 2 indicate the same thing. In Figure 1,
7 is an AND circuit which takes the input clock as one input, 1 is a frequency divider that divides the signal output from the AND circuit 7 by N, and FRI is a comparison frequency output from the frequency divider 1. On the other hand, 6 is a voltage oscillator which outputs an output clock 7. 8 is AND with output Kurofuku as one input
2 is a circuit that converts the signal output from the AND circuit 8 into M
A frequency divider performs frequency division, and FVI is a comparison frequency output from the frequency divider 2. 3 is a phase comparator that compares the phases of comparison frequencies FRI and FVl, ψ8 is a control signal that is output in the phase comparator 3 when the comparison frequency FR1 is ahead of the comparison frequency FVl, and φ is the phase This is a control signal outputted when the comparison frequency FR□ is delayed in phase from the comparison frequency Fv+ in the comparator 3. 4 is a charge pump, 5 is P, F, and vc is a control voltage that controls the oscillation frequency of the voltage controlled oscillator 6.

When the charge pump 4 receives the control signal φ3,
The charge pump 4 operates to increase the voltage VC of the voltage control oscillator 6 by sending charges to the control signal φ9, and increases the oscillation frequency of the voltage controlled oscillator 6. Absorbs charge from F5 and increases control voltage V
. The voltage controlled oscillator 6 operates to lower the oscillation frequency of the voltage controlled oscillator 6.

However, the control voltage V. The relationship between the operation of the voltage controlled oscillator 6 and the oscillation frequency of the voltage controlled oscillator 6 may differ depending on the polarity of the voltage controlled oscillator 6.

The operation of the phase synchronized circuit configured as described above will be explained using FIG. 5. FIG. 5 shows a time chart of the synchronization pull-in operation for resynchronizing from synchronization loss or input disconnection at comparison frequency FR1°F, 1, control signal φ3. φ9 and control voltage vc are shown.

FIG. 5 shows a case where the phase comparator 3 operates to advance the phase of the comparison frequency FVl.
This is to perform phase comparison. At this time, the control signal φ3 falls at the rising edge of e1, and the control signal φ□ rises at the rising edge of 1. In other words, the comparison frequency FR0 is set to the comparison frequency FVl.
In contrast, control signal φ3 is at low level (hereinafter abbreviated as "L")
This means that the phase is advanced by the period of . Therefore, the control signal φ. By inhibiting input of the input clock to the frequency divider l during the period when is "L" using the AND circuit 7 and the control signal φ3, the phase of the comparison frequency FR□ is equivalently delayed to the position e2. As a result, the phase comparison is performed at e2-r2, and a state close to a synchronous state is achieved. and,
e4-r.

The input clock and output clock are synchronized.

In addition, when the phase comparator 3 works to delay the phase of the comparison frequency FVl, the operation is the same as that of the comparison frequency FR□"V2' control signal φ3.φ9 and control voltage v0 in the time chart shown in FIG. .

In this way, by forcibly delaying the phase of the comparison frequency that is leading by the amount that it is leading, it is possible to approach a state close to a synchronous state by two clocks of the comparison frequency at the worst.

Effects of the Invention As described above, the present invention forcibly delays the phase of a comparison frequency whose phase is leading based on a control signal output from a phase comparator. This is done by providing an AND circuit that takes the logical product of the control signal and the clock for the clock that is the input of the frequency divider that outputs the comparison frequency. This controls the number of input clocks.

As a result, even if synchronization is lost or the loop gain is small due to a large internal frequency division ratio, the phase of the comparison frequency that is leading in phase is forcibly delayed, and the oscillation frequency of the voltage controlled oscillator is controlled. With these two operations, synchronization can be established in an extremely short time.
This can be realized with a very simple circuit configuration by adding only two D circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a phase-locked circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional phase-locked circuit, and FIG. 3 is a block diagram of a conventional phase-locked circuit.
FIG. 4 is a time chart showing the operation of a conventional phase-locked circuit, and FIG. 5 is a time chart showing the operation of the phase-locked circuit of the present invention. 1.2... Frequency divider, 3... Phase comparator, 6... Voltage controlled oscillator, 7.8...
AND circuit, FR□, FR□, FVIFV2...
・Comparison frequency, φ3. φ, ... control signal 5 V
o... Control voltage. Name of agent Patent attorney Toshio Nakao 1 person 441; Kuchipeyani Ku Inusa〉 Kuchihegu Ku K Figure 3 H-11111 ÷ 1gJ Period 8 ζ t,: 甚 ≦

Claims (1)

[Claims] a first AND circuit whose one input is an input clock;
a first frequency divider that divides the output signal of the first AND circuit; a second AND circuit that receives the output clock of the voltage controlled oscillator as one input; and an output signal of the second AND circuit. The phase of the divided output of the second frequency divider and the first and second frequency dividers is compared, and the phase of the divided output of the first frequency divider is compared with the phase of the divided output of the first frequency divider. A first control signal that is output when the phase of the divided output of the first frequency divider is ahead of the divided output of the second frequency divider. a phase comparator that outputs a second control signal that is output when the phase is behind the phase; and inputting the first control signal of the phase comparator to the other input of the first AND circuit;
A phase synchronized circuit characterized in that a second control signal of the phase comparator is input to the other input of the second AND circuit.