JPS6276386A - Afc detection circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a frequency fluctuation in a phase locked point by sample-holding and outputting a voltage generated at an output capacitor in a circuit that switches the polarity of a detected current after the completion of a horizontal synchronizing pulse. CONSTITUTION:As for a phase difference between a horizontal synchronizing pulse and the dividing signal of a voltage controlled oscillator, the polarity of a detected current is switched by the circuit of transistors TRs 6-10 within a horizontal synchronizing period according to the position of the period. By changing the voltages of capacitors C1 and C2 connected to the output terminal of the circuit with the circuit of a buffer 500, a negative feedback is applied on the voltage controlled oscillator. The voltages generated at the capacitors C1 and C2 are sample-held by the circuit of qa capacitor C3 and a buffer 700 and outputted after the period of the horizontal synchronizing pulse.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a home video tape recorder (hereinafter referred to as VT).
Regarding the AFC detection circuit in the color synchronization circuit (referred to as R).

[Technical background of the invention]

In a VTR, for example, the recording of 8 fraVTH "sometimes a standard 3.
58 1MHz signal and 47.7×fH (horizontal frequency) signal 1,,,□eh□□4.27 MH! .

98. □ Combined with l signal to obtain difference frequency 47'fm
(743 kHz)', and the superimposed signal of the YFM signal, AFM signal, and pilot signal is recorded on tape using a video recorder.

In addition, during playback, the reproduced low frequency conversion color signal □ is controlled by AFC (automatic frequency control) as shown in Figure 6.
□3.58M by APC (Automatic Phase Control) loop
There is a color signal reproduction method that converts the signal into Hz and superimposes it on a reproduced Y signal to obtain a reproduced video signal.

In the AFC Rogue 100 indicated by the dotted line in FIG. The phase comparator 1 also receives the output of a counter 7.

This counter 3 is the output '37 of the voltage controlled oscillator 2.
It counts down to 8 and outputs a 9 signal.The phase comparator 1 compares the phase with the 9 signal and outputs the deviation to the voltage controlled oscillator 2.

Voltage controlled oscillator 2 has horizontal synchronization No. 46 a and 378 fIN
The signal is outputted to the south counter 3 so that there is no difference in center frequency between the two, thereby forming a negative feedback loop. As a result, a signal having a frequency exactly 378 times the horizontal synchronization frequency is obtained.

The output of this voltage controlled oscillator 2 is the Neulot signal generating circuit 2oo, -! -It is also sent to the frequency divider circuit 4.

It is also used to generate pilot signals for ATF.

Furthermore, the 74.3 kHz signal output from the frequency divider 4 and the 3.58 MHz signal from the variable voltage oscillator 6 are added to the frequency converter 5 to convert the frequency to 4.2 MHz, and the frequency converter 10.

This frequency converter 10 outputs 4.2 of the output of the frequency converter 5.
7 M) fz and reproduction low frequency conversion color signal b (743kHz
), frequency conversion is performed, and the output is sent to the comb filter 9, which outputs a 3.58 MHz signal.

This output signal is sent to the phase comparator 7, which compares the phase with the reference signal of 3.58 Ml (z) from the reference signal generator 8, and outputs the comparison result to the variable voltage oscillator 6. There is.

In FIG. 6, a circuit as shown in FIG. 7 is used as the phase comparator 1 constituting the AFC loop fzoo. In this figure 7, figure 8 (,)
A horizontal synchronizing signal a as shown in 1 constitutes a differential amplifier.
In addition to the pace of the pair of transistors TrI+Tr, both emitters thereof are grounded via a constant current source 300, and during the horizontal synchronization/mother pulse period of this horizontal synchronization signal a, the transistors Tr1+Trl are turned on, and the collector of the transistor Tr1 is supplies the power supply vco, and the transistor Try
The output from the collector of is applied to the emitters of a pair of transistors T r 3 + T r 4 forming a differential amplifier f=<.

The pace of the transistor Tr3+Tr is the eighth, that is,
The output of the hemp counter in FIG. 6 has been added. Therefore, transistor Tr3. At T'4, phase comparison is performed during the horizontal synchronization pulse period of the horizontal synchronization signal a.

The collectors of the transistors T r3 r T r4 are connected to the collectors of the transistors T r5 r T r4 and the pace of the transistors Tr7+Tr@, respectively. The collectors and paces of the transistors Tr and +Tr4 are directly connected, and the emitters of each transistor are connected to the power supply Vcc through resistors R1 and R2, respectively.

Transistor Tr7. The emitters of the transistors are connected to the power supply Vcc via resistors R3 and R4, respectively. Transistor T'r7. The collectors of Trs are transistors Tr, respectively. Connected to the collector of +Tr@.

Transistor Tr. +Tr, the emitter is resistor R5,
Grounded through R6f and transistor Tr□. The pace and collector of the transistor Tr are directly connected to the pace of the transistor Tr.

The collector of the transistor TrB is grounded via a capacitor C, and is also grounded via a resistor R7 and a capacitor C2.
is connected to the input end of the

A horizontal synchronizing signal a is applied to the pace of transistors T r, + T r2, and during that pulse period, the transistor T
r is turned on, a constant current I0 flows through the transistor Trl, and the transistor Tr4 causes the transistor Try or Tr4 to turn on depending on the phase difference with the -LvCO signal 3a during the horizontal synchronization pulse period of the horizontal synchronization signal a. is turned on, turning on or off transistors Trg and Tr@.

When the transistor Tr is on, the transistor Tr1
turns on, and at this time the transistor Tr@ rTr7
．． Trl. , Tr@ is turned off. transistor Tr,
When turned on, the capacitor C is charged.

Furthermore, when the transistor Tr is turned off, the transistor '
pry, Trl. , Tr@ is on, capacitor C
The charge of 1 is discharged through the transistor Tr@t-.

In this way, the charging and discharging time of the capacitor C1 is changed by the phase difference between the horizontal synchronizing signal and aysvCO, and the current I is changed as shown in FIG. 8(c), thereby controlling the voltage. The control voltage to the oscillator 2 (voltage at point A shown in FIG. 8(d)) is changed.

During other periods, the transistors T r@ and T r are cut off. If the phase is locked, the charging and discharging charges of the capacitor C1 should be approximately equal, and if the charging and discharging currents are selected equally, the charging period and the discharging period will be equal. .

Also, if the phase is shifted, the resistor R7, capacitor C, ? Ignoring this, at the lock point, if the charging current and discharging current are set equal, 1. HVCOs
When the rising point of the signal a is at the center of the horizontal synchronization signal's base line, and the charging and discharging charges of the capacitor C are equal, the voltage across the capacitor C1 is horizontally synchronized. It maintains a constant value during periods other than pulses.

Next, when the phase of the VCO, va signal with respect to the horizontal synchronizing signal a deviates from the lock point, the horizontal For the synchronization signal, as shown in Figure 3(b),
When the VCOs m shifts, the charging and discharging charges of the capacitor C1 become unbalanced, the current at point A changes, and the voltage at point A changes as shown in FIG. 3(d).

In the examples shown in FIGS. 3(A) to 3(d), the voltage becomes high. As a result, the charge increased during the period other than the horizontal synchronization passes through the resistor R7 and flows to the capacitor C2, so the voltage at point A becomes a waveform as shown in Figure 6(d), and gradually the voltage at point A becomes The voltage is increased and a phase correction is made.

[Problems with background technology]

In the above case, the voltage at point A during the horizontal synchronization period is
), the frequency of the voltage controlled oscillator is high during that period, and the frequency of the voltage controlled oscillator is lower than the target frequency during the other periods.
The phase will be locked so that the 79 sums match.

In addition, if a phase compensation and gain adjustment circuit such as resistor R7 and capacitor C2 is installed, charge will be charged to capacitor C2 during the horizontal synchronization period, and charge will be transferred from capacitor C2 to capacitor C1 outside of horizontal synchronization. , the phase lock point shifts slightly from the center, as shown in Figure 3 (
When the voltage at point A as shown in d) changes, the frequency gradually changes.

As mentioned above, the color conversion frequency and the ATF/#irot signal deviate from the target frequency, and since frequency changes occur during the IH period, there are changes in hue, fluctuations in the ATF detection signal, and other negative effects. affect

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and it is an object of the present invention to provide an AFC detection circuit in which no frequency change occurs at the phase lock point.

[Summary of the invention]

The AFC detection circuit of this invention has horizontal synchronization and
1□ and the frequency-divided signal of the voltage-controlled oscillator, and the first circuit switches the polarity of the detection current within the horizontal synchronization period depending on the position of the frequency-divided signal within the horizontal synchronization period. A second circuit changes the voltage of the capacitor connected to the output terminal of the oscillator to apply negative feedback to the voltage controlled oscillator, and a third circuit samples and holds the voltage generated at this capacitor after the horizontal synchronization pulse ends. It is designed to be output.

[Embodiments of the invention]

Embodiments of the AFC detection circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of one embodiment. In FIG. 1, parts that are the same as those in FIG. 7 are given the same reference numerals, and a description of the structure thereof will be omitted, and only the parts that are different from FIG. 7 will be described.

The collector of the transistor Tr1, that is, the point A is connected to the buffer 500. It is connected to the input end of the buffer 700 via switch S1. Further, the transistor Tr1.
The horizontal synchronizing signal a applied to the base of the Tr is also input to the sample pulse generating circuit 600.

Sunsol/4'rus 600 * I/C y F) spin f 81 output from this sample pulse creation circuit 600
f off.

It's supposed to turn off.

The input end of the buffer 700 is grounded via a capacitor C3, and the output end of the buffer 700 is connected to the VCO2 shown in FIG. 6 via a resistor R8.

A connection point between this resistor R8 and the VCO is grounded via a resistor R7 and a capacitor C2.

Next, the operation of the AFC detection circuit of the present invention will be explained using time charts of FIGS. 2 and 3. Figure 2 (c
), the voltage at point A shown in FIG.
On the other hand, the horizontal synchronizing signal a shown in FIG. 2(,) is input to the sample pulse creation circuit 600, and a sample pulse 6θOa is created as shown in FIG. 2(,).

This sample pulse 600a is generated after the horizontal synchronization signal a and is generated at regular intervals.

This sample pulse 600a turns on the switch S1 and charges the capacitor C3f buffer to the output voltage of 500.

Capacitor C3 is a high input impedance 50
0, the same voltage is held at the output terminal of the buffer 700 while the switch S1 is off, forming a so-called sample-and-hold circuit, as shown in FIG. 2(f). , the voltage at point B becomes the sample and hold voltage. That is, the present invention has a sample and hold circuit added to the conventional AFC detection circuit.

As a result, the detection current during the horizontal synchronization period is controlled by the capacitor C1.
It is possible to obtain a detection output corresponding to the phase difference with ripples generated by integrating at .

Also, for the horizontal synchronizing signal a in Figure 3G),
As shown in b), when the phase of VCOs a shifts, the current flow changes as shown in Fig. 3(c), and the voltage at point A in the conventional AFC detection circuit shown in Fig. 7 is as shown in Fig. 3. (d)
However, in this invention, it becomes as shown in FIG. 3 (,).

That is, as shown in FIG. 3(f), the voltage at point B changes, and correspondingly, as shown in the third oral history, the voltage at point 0 (detected voltage) changes.

FIG. 4 is a circuit diagram of a main part of a second embodiment of the present invention. In FIG. 4, .guffa7σ0 in FIG. 1 is omitted, and a capacitor C3 is connected in parallel to the circuit of resistor R7 and capacitor C2. The other configurations are the same as in FIG. 1.

With this configuration, the output of the buffer 500 is generated after the horizontal synchronizing signal a, and the output of the buffer 500 is generated after the horizontal synchronizing signal a.
Turn on the switch S1 in the gurus 600a, and turn on the buffer 50.
The voltage held at 0 is output only during that period, and a detected voltage as shown in the third paragraph is obtained at the 0 point.

FIG. 5 is a circuit diagram of a main part of yet another embodiment of the AFC circuit of the present invention. In this FIG. 5, the sample pulse generation circuit 600 is omitted, and the switch Slf is directly turned on and off by the horizontal synchronizing signal a, and the output from the sofa 500 onward is turned off only during the period of the horizontal synchronizing signal a, and the switch S1 is turned off for the horizontal synchronizing signal a. The voltage held by the buffer 5θ0 is output during periods other than the synchronization period. This results in
The sample signal can be replaced by the horizontal synchronizing signal a, which simplifies the circuit.

In the embodiment shown in FIG. 5, the sample and hold voltages shown in FIG. 3(f) and K and the zero point voltage shown in FIG. 3(g) are obtained in almost the same way as in the case of FIG. 4.

[Effects of the Invention] As explained above, according to the AFC detection circuit of the present invention, it is possible to eliminate the control voltage change of the voltage controlled oscillator at the phase lock point, and to create an AFC loop with less frequency change of the voltage controlled oscillator. can be configured. As a result, a color synchronization circuit with little hue change can be realized, and a stable ATF/4
'You can create a pilot signal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the AFC detection circuit of the present invention, FIGS. 2 and 3 are time charts for explaining the operation of the AFC detection circuit, respectively, and FIGS. 4 and 5 are respectively A circuit diagram of a main part of another embodiment of the AFC detection circuit of the present invention, FIG. 6 is a block diagram of a conventional color synchronization circuit, and FIG. 7 is a circuit diagram of a conventional AFC in the color synchronization circuit of FIG. 6.
Detection Circuit FIG. 8 is a time chart for explaining the operation of the AFC detection circuit shown in FIG. Tr1 to Trl. ...Transistor, RI~R8...
- Resistance, C1 to C3... Capacitor, Sl... Switch, 300... Constant power supply, 500,700... Buffer, 600... Sample pulse generation circuit. Applicant's agent Patent attorney Suzue Takehiko No. 1 Figure 7M5ec s2 Figure 7

Claims (3)

[Claims] (1) A first circuit that changes the phase difference between the horizontal synchronization pulse and the frequency-divided signal of the voltage-controlled oscillator and switches the polarity of the detection current within the horizontal synchronization period depending on the position of the frequency-divided signal within the horizontal synchronization period;
A second circuit is connected to the output terminal of the first circuit and configures a negative feedback loop as a control voltage of the voltage controlled oscillator by changing the voltage of the capacitor, and a second circuit is connected to the output terminal of the first circuit to configure a negative feedback loop as a control voltage of the voltage controlled oscillator by changing the voltage of the capacitor. and a third circuit that samples and holds the sample and outputs the sample. (2) The AFC detection circuit according to claim 1, wherein the voltage generated from the third circuit is sampled for a certain period of time after the horizontal synchronization pulse ends and is output. (3) The AFC detection circuit according to claim 1, wherein the voltage generated from the third circuit is taken out through a buffer and the output thereof is output through a switch that is turned off during a horizontal synchronization signal period.