JPS6117589Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a time axis correction device using a CCD.

A video signal reproduced from a VTR or the like usually contains a jitter drift component. As a device to correct this drift, CCD (Charge Coupled
A time axis correction device using a device is being considered. This device controls the delay time by changing the CCD transfer clock frequency. A time axis correction device using such a method has a property that the transfer efficiency decreases as the transfer clock frequency increases. That is, the higher the transfer clock frequency, the lower the level of the delayed output signal of the CCD. Furthermore, the above-mentioned device is
It has a characteristic that the level of the CCD output signal fluctuates due to changes in the transfer clock signal frequency associated with delay time control. Therefore, this device can correct jitter drift that accompanies time axis fluctuations. However, it is not possible to correct level fluctuations due to amplitude modulation caused by changes in transfer clock frequency. This means that
This means that the amplitude of the CCD output signal, that is, the video output signal, fluctuates in synchronization with the jitter drift period. As a result, a fritzing noise appears on the CRT screen.

This invention was developed in view of the above-mentioned circumstances, and it is an object of the present invention to provide a time axis correction device in which the amplitude of a corrected signal is not changed by a correction operation for a jitter drift component or the like.

In order to achieve the above object, the time axis correction device according to the invention includes a delay circuit that delays an input signal for a predetermined period of time according to a clock signal frequency; a phase comparison circuit that compares the component with a predetermined comparison signal and provides a second signal having a level corresponding to the phase difference between these two signals; and the clock having a frequency corresponding to the signal level of the second signal. an oscillation circuit that generates a signal; amplitude-modulating the first signal with the second signal to cancel an amplitude change in the first signal that occurs with the time delay operation in the delay circuit; and a cancellation circuit that provides a corresponding amplitude corrected output signal. When a device having such a configuration is used, for example, to correct jitter in a VTR reproduced video signal, the corrected video output signal does not include amplitude fluctuations due to jitter correction. This effect is obtained by an organic combination of the cancellation circuit and other components.

Figure 1 shows the time axis correction device according to this invention.
This figure shows a configuration used to correct jitter and flicker of a VTR playback video signal. Time delay control for jitter correction is performed by the CCD 10. A reproduced video signal E1 provided from a VTR or the like is input to the CCD 10. CCD
10 is supplied with a transfer clock signal E2 from a voltage controlled oscillator VCO12. Video signal E1
is delayed by a predetermined time depending on the frequency of clock signal E2. The signal E1 delayed by the CCD 10 is sent to the sync separator 14 as the first signal E3.
is input. Separator 14 separates horizontal synchronization signal E4 from first signal E3. Synchronization signal E4
is input to the phase comparator 16.

A comparison signal E5 is further input to the comparator 16. This signal E5 is provided by a sawtooth generator 18. The generator 18 is triggered by a reference signal E6 for time base correction, and the generator 18 is
occurs. That is, the comparison signal E5 has a predetermined period synchronized with the reference signal E6.

FIGS. 2a and 2b show the relationship between the comparison signal E5 and the synchronization signal E4. Signals E5 and E4
At a point p where the levels of E and E match, the comparator 16 outputs the second signal E7. The second signal E7 has a signal level held at a level corresponding to the level matching point p. This holding operation of the second signal E7 is performed every cycle of the reference signal E6.
Further, the signal level of the second signal E7 corresponds to the phase difference between the signal E4 and the signal E5. Second signal E
7 is input to the VCO 12. VCO12
changes the frequency of the transfer clock signal E2 in accordance with the signal level of the second signal E7.

The components 10 to 16 form a negative feedback loop. By providing a sufficient loop gain for this negative feedback, the first signal E3 always maintains a constant phase relationship with respect to the reference signal E6. However, if the loop gain is too high, a lockout phenomenon will occur in the negative feedback loop when a transient such as dropout occurs. Therefore, it is necessary to select an appropriate amount of negative feedback. The above negative feedback operation removes the jitter drift component from the first signal E3. However, the first signal E
3, the frequency of the clock signal E2 or the second
Amplitude fluctuations corresponding to the signal level of signal E7 are included. FIG. 3 is a graph illustrating the relationship between the frequency of the clock signal E2 and the signal level of the first signal E3. This graph shows that the higher the transfer clock frequency, that is, the shorter the delay time in the CCD 10, the lower the level or amplitude of the first signal E3. Incidentally, the transfer clock frequency corresponds to the signal level of the second signal E7. Therefore, the second signal E7 can be used to cancel out the level drop (fluctuation) of the first signal E3. This cancellation is performed in the cancellation circuit 22.

The first signal E3 and the second signal E7 are input to the cancellation circuit 22. Here, the amplitude fluctuation component of the first signal E3, that is, the flicker component, is the second signal E7.
is canceled by

FIG. 4 shows a specific circuit example of this cancellation circuit 22. FIG. 5 also shows signals E3 and E
7 and the signal waveform of the video output signal E8 output from the cancellation circuit 22 are illustrated.

In FIG. 4, a first signal E3 with amplitude fluctuations as shown in FIG. 5a is applied to the base of an NPN transistor ₂₀₁ via a resistor R20. The emitter of transistor ₂₀₁ is NPN
With the emitter of transistor ₂₀₁ , NPN
Connected to the collector of transistor ₂₀₃ . A variable resistor R22 is connected to the base of the transistor ₂₀₃ .
A second signal E7 as shown in FIG. 5b is supplied via the second signal E7. The emitter of transistor ₂₀₃ is connected to NPN transistor 2 through resistor R24.
Connected to ₀₄ emitter. transistor 20
The emitter of ₄ is connected to the collector of NPN transistor ₂₀₅ . The emitter of transistor ₂₀₅ is connected to negative power supply -Vs via resistor R26. The base of transistor ₂₀₅ is connected to resistor R2
8 and is also connected to -Vs via a temperature compensation diode D20 and a resistor R30.

The base of transistor ₂₀₄ is grounded via resistor R32 and connected to -Vs via resistor R34. The collector of transistor ₂₀₄ is connected to the emitters of NPN transistors ₂₀₆ and ₂₀₇ . Transistor 20 ₂ , 2
The bases of 0 ₆ and 20 ₇ are grounded. The collectors of transistors 20 ₁ and 20 ₇ are connected to resistor R3.
6 to the positive power supply +Vc. The collector of transistor ₂₀₂ , together with the collector of transistor ₂₀₆ , is connected to +Vc via resistor R38. A corrected video signal E8 is output from the collectors of transistors ₂₀₂ and ₂₀₆ .

The level fluctuation of the first signal E3 input to the base circuit of the transistor ₂₀₁ is caused by the transfer clock signal E.
This is caused by the frequency change of 2. Therefore, the envelope of the first signal E3 has the same period as the second signal E7. Here, the first signal E3 input to the base of the transistor ₂₀₁
Let us consider the positive envelope. The collector current of the transistor ₂₀₂ is the first signal E
The larger the positive envelope level of 3, the more it tends to decrease. At this time, the positive half cycle of the second signal E7 is input to the base of the transistor ₂₀₃ . Therefore, the collector current of transistor ₂₀₃ , that is, transistors ₂₀₁ and 20
The sum of the collector currents of the _second signal E7 tends to increase as the positive level of the second signal E7 increases. Therefore, the decrease in the collector current of the transistor ₂₀₂ is canceled out by the increase in the collector current of the transistor ₂₀₃ . Regarding the negative envelope of the first signal E3, the above explanation can be considered in reverse. From the above, by appropriately adjusting the variable resistor R22, it is possible to obtain a video output signal E8 containing almost no level fluctuations, that is, flicker, as shown in FIG. 5c.

That is, the input signal E1, which has undergone jitter correction by the CCD 10, is further subjected to flicker correction by the cancellation circuit 22, resulting in an output signal E8 containing neither jitter nor flicker. Therefore, when a time axis correction circuit as shown in FIG. 1 is used, it is possible to eliminate the flicker phenomenon peculiar to CCD delay circuits, so that a good reproduced image can be obtained.

Note that the embodiments illustrated in the drawings and disclosed in this specification do not limit the invention in any way. Various modifications can be made within the spirit of this invention and the scope of the utility model registration claims. For example, the cancellation circuit 22 can also be configured using an AGC or ALC circuit using variable impedance elements such as FETs and CdS.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a time axis correction device according to an embodiment of the invention, FIG. 2 is a diagram illustrating the waveforms of signals E4 and E5 in FIG. 1, and FIG. A graph illustrating the relationship between the signal E2 frequency and the signal E3 level (amplitude), FIG. 4 is a circuit diagram showing a specific example of the cancellation circuit in FIG. 1, and FIG. 5 shows the relationship between the signals E3, E7 and signal E3 in FIG. It is a figure which illustrates the signal waveform of E8. 10...CCD (delay circuit), 12...VCO (oscillation circuit), 14...synchronous separator, 16...phase comparator (phase comparison circuit), 18...sawtooth wave generator, 22...cancellation circuit (amplitude modulation circuit), 20 ₁
~20 ₇ ...NPN transistor, E1...Playback video signal (input signal), E2...Transfer clock signal, E3...First signal, E4...Horizontal synchronization signal (specific signal component), E5...Comparison signal , E6... Reference signal, E7... Second signal, E8... Video output signal (output signal).

Claims (1)

[Scope of utility model registration request] A delay circuit that delays an input signal for a predetermined time according to the clock signal frequency; Compares a specific signal component in a first signal output from this delay circuit with a predetermined comparison signal, and determines the phase difference between these two signals. a phase comparison circuit that provides a second signal having a level corresponding to the signal level of the second signal; an oscillation circuit that generates the clock signal having a frequency that corresponds to the signal level of the second signal; a cancellation circuit that amplitude modulates the second signal and the first signal to cancel amplitude changes in the first signal caused by the input signal and provides an amplitude-corrected output signal corresponding to the input signal. Axis correction device.