JP3133455B2 - Time axis correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction circuit (hereinafter referred to as a TBC) for correcting a time axis fluctuation generated when reproducing a video disk player, a video tape recorder or the like.
Circuit).

[0002]

2. Description of the Related Art A conventional feed-forward TBC circuit is shown in FIGS.

FIG. 3 shows an example using a CCD as a delay line, and FIG. 4 shows an example using a CMOS inverter delay line as a delay line.

In FIG. 3, a video signal (or luminance signal) input to an input terminal a is input to a CCD delay line 10 and also to a sync separation circuit 1, and a horizontal sync signal is extracted from the signal. It is. Then, the extracted horizontal synchronizing signal is input to a sample / hold circuit 6 and a PLL circuit including a comparator 2, an LPF 3, a VCO 4, and a frequency divider 5. Here, since the time constant of the LPF 3 is set to be very large, in this PLL circuit, the time axis fluctuation (for example,
The control is performed so as not to follow jitter (jitter generated due to the vibration of the magnetic tape caused by the contact of the head with the magnetic tape).

[0005] The signal output from the frequency divider 5 is also input to a saw-tooth wave generating circuit 7 as a reference signal, and a saw-tooth wave is created based on this signal.

On the other hand, the sample and hold circuit 6 receives the sawtooth wave generated by the sawtooth wave generation circuit 7 and the horizontal synchronizing signal separated by the sync separation circuit 1,
Sampling of the sawtooth wave is performed by a sampling pulse created using the horizontal synchronization signal as a reference signal. Here, since the position of the sampling pulse is different depending on the time axis variation in the high frequency range, the held value is different, and the time axis variation in the high frequency range included in the video signal is extracted. Then, the extracted time axis fluctuation in the high frequency range is input to the variable gain circuit 8, and the variable gain circuit 8 is optimally adjusted according to the characteristics of the VCO to control the VCO 9 and delay the CCD delay line 10. Control the time. As a result, on the output side of the CCD delay line 10, a video signal or a luminance signal from which the time axis fluctuation in a high frequency region has been removed appears. Next, the video signal or the luminance signal that has passed through the CCD delay line is replaced by the reference signal (pseudo horizontal synchronization signal) generated by the frequency divider 5 by the synchronization replacement circuit 11, and then output to the output terminal b. .

[0007] In this manner, a video signal or a luminance signal from which the time-axis fluctuation in the high-frequency range has been removed is output.

Next, the conventional example shown in FIG. 4 will be described.

FIG. 4 shows an example in which a CMOS inverter 9 is used as a variable delay line. The delay time of the CMOS inverter changes according to the VDD voltage, and the number of stages for connecting the CMOS inverter is determined according to a required variable range. .

The basic control of the conventional example of FIG. 4 is the same as that of FIG.

In this conventional example, a CMO is used as a variable delay line.
Since the S inverter is used, this CMOS inverter does not have the information in the amplitude direction, so that a normal video signal or luminance signal cannot be directly input, and
The signal is input after FM modulation by the M modulator 10.
Then, the FM-modulated video signal or luminance signal is
After passing through the CMOS inverter delay line 9, F
The signal is demodulated by the M demodulator 11. Next, the extracted time-axis fluctuation in the high-frequency range is appropriately adjusted by the variable gain circuit 8 according to the characteristics of the CMOS inverter delay line 9 to become a control voltage, and the delay time of the video signal or the luminance signal is controlled. You.

Therefore, the video signal or the luminance signal demodulated by the FM demodulator 11 has a time-axis variation in a high frequency region removed.

[0013]

In the prior art shown in FIG. 3, the oscillation frequency of the VCO 9 is controlled by the variable gain circuit 8, and the delay time of the CCD delay line 10 is controlled by the oscillation frequency of the VCO 9. However, CCD
To control the delay time of the delay line 10, the variable gain circuit 8
It is necessary to adjust the DC voltage and to adjust the amplitude value of the variable gain circuit 8, and a total of two adjustments are required.
In addition, after the above adjustment, the characteristics of the VCO 9 change due to temperature characteristics and changes over time, so that the amplitude of the time axis fluctuation is not appropriate, and the fluctuation cannot be sufficiently removed, or the synchronous replacement due to friction of the average delay time. There is a problem that the phase of the synchronization signal to be replaced by the circuit 11 and the phase of the video signal or the luminance signal are shifted.

In FIG. 4 as well, there is a problem in accordance with the characteristics of the CMOS inverter delay line 9 in accordance with the characteristics of the CMOS inverter delay line 9 in the same manner as in the above-described conventional example, which involves two adjustments and a change in the characteristics of the CMOS inverter delay line 9 after the adjustment.

The present invention has been made in view of the above-mentioned drawbacks, and has as its object to provide an accurate time axis correction circuit.

[0016]

According to the present invention, there is provided a first time saw having a first sawtooth wave generating circuit for extracting a time axis fluctuation component from a video signal input to a variable delay line, and a first sample and hold circuit. Axis fluctuation detecting means, a variable gain circuit for amplifying or attenuating the time axis fluctuation component for controlling the variable delay line, and a residual time axis fluctuation component for extracting a video signal output from the variable delay line. A second time axis fluctuation detecting means having a second sawtooth wave generating circuit and a second sample and hold circuit; and a variable gain circuit controlling means connected to the first and second time axis fluctuation detecting means. The outputs from the first time axis fluctuation detection means and the second time axis fluctuation detection means are supplied to the variable gain circuit control means to generate a variable gain circuit control signal, and the variable gain circuit control signal A time base correction circuit which controls the delay time of the variable delay line by controlling the variable gain circuit.

[0017]

According to the present invention, a hold value for a time-axis variation and a residual time-axis variation is detected by a saw-tooth wave generating circuit and a sample-and-hold circuit provided on the input / output side of the delay line. I do. Then, the DC component of the residual time axis fluctuation and the time axis fluctuation are detected by the LPF, and a rub from a predetermined average delay time is detected by comparing these DC components. Next, in accordance with the rubbing, the slope of the sawtooth wave generated by the sawtooth wave generating means on the input / output side is changed, and the average delay time is kept at a predetermined value. At this time, since the ratio of the slope of the sawtooth wave created by both sawtooth wave generation circuits is determined in advance by the value of the average delay time, the slope changes while maintaining this ratio.

Further, the hold value corresponding to the time axis fluctuation is input to the adder, and after full-wave rectification, a DC component is detected via the LPF. On the other hand, the hold value of the residual time axis variation is amplified by an amplifier and then input to an adder. The output of the adder is subjected to full-wave rectification and then passes through an LPF, whereby a DC component is detected. Next, these DC components are compared to detect friction from the optimum value, change the gain of the variable gain circuit, and control the delay time of the variable delay line.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment and a second embodiment of the present invention will be described below with reference to the drawings.

The same parts as those shown in FIG. 3 are assigned the same reference numerals and their explanation is omitted.

The operation until the time axis fluctuation is output from the sample hold circuit 6 is the same as that of the prior art shown in FIG.

In FIG. 1, a video signal or a luminance signal that has passed through the CCD delay line 10 is input to a sync separation circuit 18, and a horizontal sync signal is extracted. The pulse created using the extracted horizontal synchronization signal as a reference signal is:
Sampling hold circuit 1 as sampling pulse
9 is input. On the other hand, the output from the frequency divider 5 is input to the sawtooth wave generating circuit 20, which generates a sawtooth wave, and outputs the sawtooth wave to the sample and hold circuit 19. Then, in the sample and hold circuit 19, the sawtooth wave is sampled and held based on the above-described sampling pulse, and the held value is input to the LPF 16.

The LPF 13 integrates the above hold value and inputs it to the comparator 17. By the way, the time-axis variation extracted by the sample-and-hold circuit 6 is input to the comparator 17 via the LPF 15.
The outputs of 16 are supplied to the saw-tooth wave generating circuits 7 and 20 to change the slope of the saw-tooth wave while maintaining the ratio, and the average delay time of the CCD delay line is set to a predetermined time. Fix it. The time-axis fluctuations and the residual time-axis fluctuations from the sample-and-hold circuits 6 and 19 are added by an adder 23, then full-wave rectified by a rectifier 24, and a DC component is extracted by an LPF 25.
To enter. At this time, the control sensitivity may be increased by amplifying the residual time axis fluctuation by the AMP 27 and then inputting the amplified signal to the addition circuit 23. In this embodiment, the outputs from the sample and hold circuits 6 and 19 are added. However, when the outputs from the sample and hold circuits 6 and 19 have opposite polarities, the output is constituted by a subtraction circuit. On the other hand, the output of the sample and hold circuit 6 is input to the comparator 26 via the rectifier circuit 21 and the LPF 22.

The comparator 26 controls the variable gain circuit 8 based on the voltage difference obtained by comparing the two direct currents, and
9 By adjusting the oscillation frequency, the CCD delay line 10
, And removes axial fluctuations during high frequency.

With the above arrangement, the fluctuation of the time axis in the high frequency range is removed, and a video signal or a luminance signal having a predetermined average delay time is output from the CCD delay line 10. After being replaced by the horizontal synchronizing signal generated from the frequency divider 5, the output terminal b
Is output to

Next, the operation of the present invention will be described.

First, the automatic adjustment of the average delay time will be described.

FIGS. 5 and 6 are diagrams for explaining automatic adjustment of the set average delay time. FIG. 5 shows automatic adjustment when the delay time is smaller than a predetermined value, and FIG. It is a figure showing automatic adjustment when it is larger than.

5 and 6, A denotes a CCD delay line 1.
0 indicates a video signal waveform on the input side, and B indicates a video signal waveform on the output side of the delay line 10.

The waveforms 1 and 3 are represented by a sawtooth wave generating circuit 7,
20 shows the sawtooth wave created at 20, waveforms 2, 4, 6,
Reference numeral 8 denotes a sampling pulse created by using the horizontal synchronization signal separated by the synchronization separation circuits 1 and 18 as a reference signal. Waveforms 5 and 7 show reference sawtooth waves whose amplitude is b.

The above-mentioned sawtooth waves 1 and 3 are created using the output of the frequency divider 5 as a reference signal, and the inclination ratio of both sawtooth waves is determined in advance by the average delay time. The average delay time indicates a delay time between input and output of the CCD delay line 10. Therefore, when the reference point both sawtooth 1,3 rises, may be set so as to be sampled after the A tau _2, also by setting to be sampled in tau after ₃ B, CCD The average delay time of the delay line 10 can be (τ ₃ −τ ₂ ). For this purpose, in the initial state, the slope of the sawtooth wave of B needs to be always τ ₂ / τ _{3 as} compared with A.

When the delay time is shorter than a predetermined value as shown in FIG. 5, the amplitude a of the sawtooth wave becomes smaller than the amplitude b of the reference sawtooth wave. Therefore, assuming that the slope of the sawtooth wave shown by the waveform 1 is a / τ ₁ , the voltage R ₁ sampled by the sampling pulse shown by the waveform 2 after τ ₂
Becomes lower than the voltage R. Note that R is the average delay time (τ ₃ −
τ ₂ ). Since the sampling voltage R ₁ is lower than the reference voltage R, the delay time is shortened, shorter than the delay time tau ₃ of the delay time of the sampling pulse tau ₃ 'is a reference pulse represented by the waveform 4 in the B side.

Accordingly, on the output side of the CCD delay line 10, a sawtooth wave having a waveform 3 having a slope of (a / τ ₁ ) × (τ ₂ / τ ₃ ) is sampled, and a sampling voltage R lower than R is sampled on the B side. It becomes ₂ . Then, the above-described sampling voltage difference is fed back to the sawtooth wave generating circuits 7 and 20, and the slope of both sawtooth waves changes while maintaining the ratio of τ ₂ / τ ₃ .

In this manner, the slopes of the sawtooth waves 1 and 3 are b / τ ₁ in the case of the waveform ₁ , and (b / τ ₁ ) × (τ ₂ / τ ₃ ) in the case of the waveform 3. Is controlled to be
The sampling voltage of the waveforms 1 and 3 becomes equal to R, and is fixed to the set average delay time.

When the delay time is longer than a predetermined value as shown in FIG. 6, the amplitude c of the sawtooth wave becomes larger than the amplitude b of the reference sawtooth wave. Therefore, when the slope of the sawtooth wave shown by the waveform 1 and c / tau _1, the waveform after tau ₂ 2
The voltage R sampled by the sampling pulse shown by
₃ is higher than voltage R. Here, higher than the sampling voltage R ₃ is the reference voltage R, the delay time becomes long, longer than the delay time tau ₃ of the delay time of the sampling pulse tau ₃ 'is a reference pulse represented by the waveform 4 in the B side.

Therefore, on the output side of the CCD delay line 10, a sawtooth wave having a waveform (c / τ ₁ ) × (τ ₂ / τ ₃ ) is sampled, and the sampling voltage R higher than R is sampled on the B side. It becomes ₄ . Then, the above-described sampling voltage difference is fed back to the sawtooth wave generating circuits 7 and 20, and the slope of both sawtooth waves changes while maintaining the ratio of τ ₂ / τ ₃ .

As described above, the slope of the sawtooth waves 1 and 3 is b / τ ₁ in the case of the waveform ₁ , and (b / τ ₁ ) × (τ ₂ / τ ₃ ) in the case of the waveform 3. Is controlled to be
The sampling voltage of the waveforms 1 and 3 becomes equal to R, and is fixed to the set average delay time.

Next, automatic adjustment of the amplitude of the time-axis fluctuation extracted on the input side will be described.

In FIG. 7, a waveform 1 is a waveform at point C which is a time-axis variation extracted at the input, and a waveform 2 is a waveform at point D which is a remaining time-axis variation extracted at the output side. .

The DC component of each of the waveforms 1 and 2 coincides with the voltage R by the above-described automatic adjustment of the average delay time.

The waveforms 1 and 2, which are the detected time axis fluctuation and the remaining time axis fluctuation, are added by an adder 23 and E
The waveform becomes a waveform 3 at the point, and thereafter is subjected to full-wave rectification as shown by a waveform 5 at the point F by the rectifier circuit 24, integrated by the LPF 25 and input to the comparator 26. Further, the waveform 1 is full-wave rectified by the rectifier circuit 21, and becomes the waveform shown in the waveform 4 at the point G. This waveform 4 is integrated by the LPF 22 and input to the other of the comparator 26. Then, the waveforms 4 and 5 are compared by the comparator 26, and the voltage difference (ΔV) is output to the variable gain circuit 8 to control the amplitude of the variable gain circuit 8.

Accordingly, when the waveforms 1 and 2 are in phase, it indicates that the gain of the variable gain circuit 8 is insufficient, and the gain is increased by the voltage difference ΔV. No more components are extracted, and the DC components of waveform 4 and waveform 5 match and converge.

On the other hand, when the waveform 1 and the waveform 2 are out of phase as shown in FIG. 8, it indicates that the gain of the variable gain circuit 8 is too high, and the gain is reduced by the voltage difference ΔV. The residual time axis fluctuation shown is not extracted, and the DC components of the waveform 4 and the waveform 5 match and converge.

In this manner, the automatic control of the amplitude of the time axis fluctuation is performed.

Next, an example in which a CMOS inverter delay line is used as a variable delay line will be described with reference to FIG.

Since the circuit operation is the same as that of FIG. 1, the description is omitted.

The difference of this embodiment from FIG. 1 is that the time constant of the LPF 3 is increased, and the time axis fluctuation (for example, eccentricity of the mechanical system) included in the video signal or the luminance signal input to the input terminal a. (The time axis fluctuation in the low frequency region, and the time axis fluctuation in the high frequency region typified by the impact error caused by vibration of the tape or the like during reproduction), only the time axis fluctuation in the low frequency region is tracked. is there. Therefore, the time axis fluctuation extracted by the sample hold circuit 6 is also only the time axis fluctuation in the high frequency range. In general, the amount of fluctuation differs between the time axis fluctuation in the low frequency region and the time axis fluctuation in the high frequency region, and the amount of fluctuation in the time axis fluctuation in the high frequency region is much smaller. Therefore, in FIG. 2, a CMOS inverter delay line 12 is used as a delay line, and the variable range is reduced by controlling the number of inverter stages.

Since it is necessary to reduce the average delay time by reducing the variable range, the ratio of the inclination of the sawtooth wave generated by the sawtooth wave generators 7 and 20 is set in advance in accordance with the delay time. ing. Other operations are the same as those in FIG.

In this manner, a video signal or a luminance signal from which only the time axis fluctuation in the high frequency region has been removed is output to the output terminal b.

[0050]

According to the present invention, as described above,
The feed-forward time axis correction circuit does not require the adjustment of the average delay time, which is always performed, and the adjustment of the time axis fluctuation extracted from the characteristics of the delay line or the circuit that drives the delay line. In addition, the performance of the present invention does not deteriorate due to temperature characteristics and changes over time.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing another conventional example.

FIG. 5 is a waveform chart for explaining the operation principle of the present invention.

FIG. 6 is a waveform chart for explaining the operation principle of the present invention.

FIG. 7 is a waveform chart for explaining the operation principle of the present invention.

FIG. 8 is a waveform chart for explaining the operation principle of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization separation circuit 2 Comparator 3 LPF 4 VCO 5 Divider 6 Sample hold circuit 7 Sawtooth wave generation circuit 8 Variable gain circuit 9 VCO 10 CCD delay line 11 Synchronization replacement circuit 15 LPF 16 LPF 17 Comparator 18 Synchronization separation circuit 19 Sample hold circuit 20 Saw wave generation circuit 21 Rectifier circuit 22 LPF 23 Addition circuit 24 Rectifier circuit 25 LPF 26 Comparator 27 Amplifier

Claims (1)

(57) [Claims] A first sawtooth wave generating circuit for extracting a time-axis fluctuation component from a video signal input to a variable delay line; a first time-axis fluctuation detection means having a first sample-and-hold circuit; A variable gain circuit for amplifying or attenuating the time axis fluctuation component to control the delay line, a second sawtooth wave generation circuit for extracting a residual time axis fluctuation component of the video signal output from the variable delay line, and A second time-axis fluctuation detecting means having a second sample-and-hold circuit; and a variable gain circuit control means connected to the first and second time-axis fluctuation detecting means. An output from the second time axis fluctuation detecting means is supplied to the variable gain circuit control means to generate a variable gain circuit control signal, and the variable gain circuit is controlled by the variable gain circuit control signal. Wherein the delay time of the variable delay line is controlled by the control circuit.