JPH05244568A - Time base correction circuit - Google Patents

Abstract

PURPOSE:To provide the time base correction circuit with high accuracy in which number of adjustment positions is less. CONSTITUTION:Sawtooth wave generating circuits 7, 20 provided to input and output sides of a CCD delay line 10 respectively and sample-and-hold circuits 6, 19 detect a holding component of a time axis fluctuation and a residual time base fluctuation, LPFs 15, 16 detect a DC component of the time base fluctuation and the residual time base fluctuation and they are compared to detect a delay from a prescribed mean delay time, then the slope of the sawtooth wave is changed accordingly to keep a mean delay time to a prescribed time. Furthermore, the holding value of the time base fluctuation is inputted to an adder 23, and full-wave-rectified and the DC component is detected via an LPF 22, and the result is amplified by an amplifier 27 on the other hand and the amplified signal is inputted to the adder 23, its output is full-wave- rectified and the rectified signal is given to an LPF 25 to detect the DC component, the deviation from an optimum value is detected by comparing them to change the gain of a variable gain circuit 8 thereby controlling the delay time in the CCD delay line 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction circuit (hereinafter TBC) for correcting a time axis fluctuation which occurs when a video disk player, a video tape recorder or the like is reproduced.
Abbreviated as a circuit).

[0002]

2. Description of the Related Art A conventional feed-forward TBC circuit is shown in FIGS.

FIG. 3 shows an example using a CCD as a delay line, and FIG. 4 shows an example using a CMOS inverter delay line as a delay line.

In FIG. 3, the video signal (or luminance signal) input to the input terminal a is input to the CCD delay line 10 and also to the sync separation circuit 1, and the horizontal sync signal is extracted from the signal. Be done. Then, the extracted horizontal synchronizing signal is input to the sample hold circuit 6, and the PLL circuit including the comparator 2, the LPF 3, the VCO 4, and the frequency divider 5. Here, since the time constant of the LPF 3 is set to be extremely large, in this PLL circuit, the time base fluctuation of the high frequency range included in the synchronization signal (for example,
The head is controlled so as not to follow the jitter generated due to the vibration of the magnetic tape caused by the contact with the magnetic tape.

The signal output from the frequency divider 5 is also input to the sawtooth wave generation circuit 7 as a reference signal, and a sawtooth wave is generated with this signal as a reference.

On the other hand, the sample-hold circuit 6 receives the saw-tooth wave created by the saw-tooth wave generating circuit 7 and the horizontal synchronizing signal separated by the sync separating circuit 1,
The sawtooth wave is sampled and held by the sampling pulse created using the horizontal synchronizing signal as a reference signal. Here, since the position of the sampling pulse differs depending on the time base fluctuation in the high frequency region, the held value is different, and the time base fluctuation component in the high frequency region included in the video signal is extracted. Then, the extracted time axis fluctuation of the high frequency region is input to the variable gain circuit 8, and the VCO 9 is controlled by optimally adjusting the variable gain circuit 8 according to the characteristics of the VCO, and the delay of the CCD delay line 10 is delayed. Control the time. As a result, on the output side of the CCD delay line 10, a video signal or a luminance signal from which the time base fluctuation in the high frequency region is removed appears. Next, the video signal or the luminance signal that has passed through the CCD delay line is replaced with the reference signal (pseudo horizontal sync signal) created by the frequency divider 5 by the sync replacement circuit 11, and then output to the output terminal b. ..

In this way, the video signal or the luminance signal from which the time-axis fluctuation in the high frequency range is removed is output.

Next, the conventional example of FIG. 4 will be described.

FIG. 4 shows an example in which the CMOS inverter 9 is used as the variable delay line. The delay time of the CMOS inverter changes according to the VDD voltage, and the number of stages to connect the CMOS inverter is determined according to the required variable range. ..

Since the basic control of the conventional example of FIG. 4 is the same as that of FIG. 3, the description thereof will be omitted.

In this conventional example, a CMO is used as a variable delay line.
Since the S inverter is used, this CMOS inverter does not have that information in the amplitude direction, and therefore a normal video signal or luminance signal cannot be directly input.
It is input after being FM-modulated by the M modulator 10.
The FM-modulated video signal or luminance signal is
F after passing through the CMOS inverter delay line 9
It is demodulated by the M demodulator 11. Next, the extracted time-axis variation in the high frequency range is appropriately adjusted by the variable gain circuit 8 according to the characteristics of the CMOS inverter delay line 9 to become a control voltage, and the delay time of the video signal or the luminance signal is controlled. It

Therefore, the video signal or the luminance signal demodulated by the FM demodulator 11 has the time axis fluctuation in the high frequency range removed.

[0013]

In the conventional example shown in FIG. 3, the variable gain circuit 8 controls the oscillation frequency of the VCO 9, and the oscillation frequency of the VCO 9 controls the delay time of the CCD delay line 10. However, CCD
To control the delay time of the delay line 10, the variable gain circuit 8
It was necessary to adjust the DC voltage and the amplitude value of 8 of the variable gain circuit, and a total of two adjustments were necessary.
Not only that, but after the above adjustment, the characteristics of the VCO 9 change due to temperature characteristics and changes over time, the amplitude of the fluctuation on the time axis becomes inadequate, fluctuations cannot be removed sufficiently, and synchronization replacement is performed due to rubbing of the average delay time. There is a problem that the phase of the synchronizing signal and the video signal or the luminance signal which are replaced by the circuit 11 are out of phase.

Also in FIG. 4, similarly, there are problems associated with the characteristics of the CMOS inverter delay line 9 in the same manner as in the above-described conventional example, in which two adjustments are made and the characteristics of the CMOS inverter delay line 9 after adjustment are changed.

The present invention has been made in view of the above-mentioned drawbacks, and provides an accurate time axis correction circuit.

[0016]

According to the present invention, there is provided a first time period having a first sawtooth wave generating circuit for extracting a time axis fluctuation component from a video signal inputted to a variable delay line, and a first sample and hold circuit. Axis variation detecting means, a variable gain circuit for amplifying or attenuating the time axis variation component for controlling the variable delay line, and a residual time axis variation component of the video signal output from the variable delay line. A second sawtooth wave generating circuit and a second time base fluctuation detecting means having a second sample and hold circuit; and a variable gain circuit control means connected to the first and second time base fluctuation detecting means. The outputs from the 1-time-axis fluctuation detecting means and the second time-axis fluctuation detecting means are supplied to the variable gain circuit control means to create a variable gain circuit control signal, which is preceded by the variable gain circuit control signal. A time base correction circuit which controls the delay time of the variable delay line by controlling the variable gain circuit.

[0017]

According to the present invention, with the above configuration, the hold value for the time axis fluctuation and the residual time axis fluctuation are detected by the sawtooth wave generation circuit and the sample hold circuit provided on the input / output side of the delay line. To do. Then, the LPF detects the DC components of the residual time axis variation and the time axis variation, and compares these DC components to detect rubbing from a predetermined average delay time. Next, in accordance with this rubbing, the slope of the sawtooth wave generated by the sawtooth wave generating means on the input / output side is changed to keep the average delay time at a predetermined value. At this time, since the ratio of the slopes of the sawtooth waves created by the two sawtooth wave generation circuits is determined in advance by the value of the average delay time, the slope changes while maintaining this ratio.

Further, the hold value corresponding to the fluctuation of the time axis is input to the adder and full-wave rectified, and then the DC component is detected via the LPF. On the other hand, the hold value of the residual time axis fluctuation is amplified by an amplifier and then input to an adder. The output of the adder is full-wave rectified and then passes through an LPF to detect a DC component. Next, these DC components are compared to detect rubbing from the optimum value, the gain of the variable gain circuit is changed, and the delay time of the variable delay line is controlled.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described below with reference to the drawings.

The same parts as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted.

The operation until the time-axis fluctuation component is output from the sample hold circuit 6 is the same as in FIG. 3 of the prior art.

In FIG. 1, the video signal or the luminance signal that has passed through the CCD delay line 10 is input to the sync separation circuit 18, and the horizontal sync signal is extracted. The pulse created with this extracted horizontal synchronization signal as the reference signal is
Sampling and holding circuit 1 as sampling pulse
9 is input. On the other hand, the output from the frequency divider 5 is input to the sawtooth wave generation circuit 20, the sawtooth wave generation circuit 20 creates a sawtooth wave, and this sawtooth wave is output to the sample hold circuit 19. Then, in the sample hold circuit 19, the sawtooth wave is sampled and held based on the above-mentioned sampling pulse, and this hold value is input to the LPF 16.

The LPF 13 integrates the above hold value and inputs it to the comparator 17. By the way, the time axis fluctuation component extracted by the sample hold circuit 6 is input to the comparator 17 via the LPF 15, and both LPFs 15,
The outputs of 16 are compared and the difference voltage is supplied to the sawtooth wave generation circuits 7 and 20, the slope of the sawtooth wave is changed while maintaining the ratio, and the average delay time of the CCD delay line is set to a predetermined time. Fix it. The time-axis fluctuation component and the residual time-axis fluctuation component from the sample and hold circuits 6 and 19 are added by the adding circuit 23, then full-wave rectified by the rectifying circuit 24, and the DC component is extracted by the LPF 25, and the comparator 26
To enter. At this time, the control sensitivity may be increased by amplifying the residual time axis fluctuation by the AMP 27 and then inputting it to the adder circuit 23. Further, in the present embodiment, the outputs from the sample hold circuits 6 and 19 are added, but when the outputs from the sample hold circuits 6 and 19 have the opposite polarities, the subtraction circuit is used. On the other hand, the output of the sample hold circuit 6 is input to the comparator 26 via the rectifier circuit 21 and the LPF 22.

In the comparator 26, the variable gain circuit 8 is controlled by the voltage difference obtained by comparing the above-mentioned two direct currents to control the VCO.
9 CCD delay line 10 by adjusting the oscillation frequency
The delay time is controlled to remove the axial fluctuation during high frequency.

With the above configuration, the time base fluctuation in the high frequency range is eliminated, and the video signal or the luminance signal of the average delay time which is a predetermined time is output from the CCD delay line 10 and the sync exchange circuit 11 is provided. After being replaced with the horizontal synchronizing signal generated from the frequency divider 5, the output terminal b
Is output to.

Next, the operation of the present invention will be described.

First, the automatic adjustment of the average delay time will be described.

5 and 6 are diagrams for explaining the automatic adjustment of the set average delay time. FIG. 5 is an automatic adjustment when the delay time is less than a predetermined value, and FIG. 6 is a delay time of a predetermined value. It is a figure which shows automatic adjustment in the case of larger than.

In FIGS. 5 and 6, A is the CCD delay line 1.
0 shows the video signal waveform on the input side, and B shows the video signal waveform on the output side of the delay line 10.

Waveforms 1 and 3 are sawtooth wave generating circuits 7,
20 shows a sawtooth wave created by 20 and has waveforms 2, 4, 6,
Reference numeral 8 denotes a sampling pulse created with the horizontal synchronizing signal separated by the synchronizing separation circuits 1 and 18 as a reference signal. Waveforms 5 and 7 represent reference sawtooth waves having an amplitude of b.

The sawtooth waves 1 and 3 described above are created by using the output of the frequency divider 5 as a reference signal, and the slope ratio of both sawtooth waves is predetermined by the average delay time. The average delay time means the delay time between the input and output of the CCD delay line 10. Therefore, based on the point where both sawtooth waves 1 and 3 rise, the CCD is set to be sampled after τ ₂ in A and to be sampled after τ ₃ in B. The average delay time of the delay line 10 can be (τ ₃ −τ ₂ ). For this purpose, in the initial state, the slope of the sawtooth wave of B must be set to τ ₂ / τ _{3 as} compared with A.

Now, as shown in FIG. 5, when the delay time is shorter than a predetermined value, the amplitude a of the sawtooth becomes smaller than the amplitude b of the reference sawtooth. Therefore, assuming that the slope of the sawtooth wave represented by the waveform 1 is a / τ ₁ , the voltage R ₁ sampled by the sampling pulse represented by the waveform 2 after τ ₂
Becomes lower than the voltage R. R is the average delay time (τ ₃ −
τ ₂ ). Here, since the sampling voltage R ₁ is lower than the reference voltage R, the delay time becomes shorter, and the delay time τ ₃ ′ of the sampling pulse shown by the waveform 4 becomes shorter than the delay time τ ₃ of the reference pulse on the B side.

Therefore, a sawtooth wave having a slope of (a / τ ₁ ) × (τ ₂ / τ ₃ ) of the waveform 3 is sampled on the output side of the CCD delay line 10, and a sampling voltage R lower than R on the B side is sampled. It becomes ₂ . Then, the above sampling voltage difference is fed back to the sawtooth wave generating circuits 7 and 20, and the slopes of both sawtooth waves change while maintaining the ratio of τ ₂ / τ ₃ .

In this way, the slopes of the sawtooth waves 1 and 3 are such that the slope of the waveform 1 is b / τ ₁ and the slope of the waveform 3 is (b / τ ₁ ) × (τ ₂ / τ ₃ ). Controlled to be
The sampling voltage of the waveforms 1 and 3 becomes equal to R and is fixed to the set average delay time.

As shown in FIG. 6, when the delay time is longer than a predetermined value, the amplitude c of the sawtooth wave becomes larger than the amplitude b of the reference sawtooth wave. Therefore, when the slope of the sawtooth wave shown by the waveform 1 and c / tau _1, the waveform after tau ₂ 2
The voltage R sampled by the sampling pulse shown by
₃ becomes higher than the voltage R. Here, since the sampling voltage R ₃ is higher than the reference voltage R, the delay time becomes longer, and the delay time τ ₃ ′ of the sampling pulse shown by the waveform 4 becomes longer than the delay time τ ₃ of the reference pulse on the B side.

Therefore, on the output side of the CCD delay line 10, a sawtooth wave whose slope of the waveform 3 is (c / τ ₁ ) × (τ ₂ / τ ₃ ) is sampled, and on the B side, a sampling voltage R higher than R is sampled. It becomes ₄ . Then, the above sampling voltage difference is fed back to the sawtooth wave generating circuits 7 and 20, and the slopes of both sawtooth waves change while maintaining the ratio of τ ₂ / τ ₃ .

In this way, the slopes of the sawtooth waves 1 and 3 are such that the slope of the waveform 1 is b / τ ₁ and the slope of the waveform 3 is (b / τ ₁ ) × (τ ₂ / τ ₃ ). Controlled to be
The sampling voltage of the waveforms 1 and 3 becomes equal to R and is fixed to the set average delay time.

Next, automatic adjustment of the amplitude of the time-axis fluctuation component extracted on the input side will be described.

In FIG. 7, waveform 1 is a waveform at point C which is the time-axis variation extracted by the input, and waveform 2 is a waveform at point D which is the residual time-axis variation extracted at the output side. ..

The DC components of both waveforms 1 and 2 match the voltage R by the above-mentioned automatic adjustment of the average delay time.

Waveforms 1 and 2 which are the detected time-axis fluctuation amount and the residual time-axis fluctuation amount are added by the adder 23 to obtain E.
The waveform becomes the waveform 3 at the point, and thereafter, the full-wave rectification is performed at the point F by the rectifier circuit 24 as shown in the waveform 5, and integrated by the LPF 25 and input to the comparator 26. Further, the waveform 1 is full-wave rectified by the rectifying circuit 21, and becomes a waveform 4 at the point G. The waveform 4 is integrated by the LPF 22 and input to the other side of the comparator 26. Then, the waveform 4 and the waveform 5 are compared by the comparator 26, the voltage difference (ΔV) is output to the variable gain circuit 8, and the amplitude of the variable gain circuit 8 is controlled.

Therefore, when the waveform 1 and the waveform 2 are in phase, it indicates that the gain of the variable gain circuit 8 is insufficient, and the gain is increased by the voltage difference of ΔV, and eventually the residual time axis fluctuation shown by the waveform 2 is obtained. Minutes are no longer extracted, and the DC components of waveform 4 and waveform 5 match and converge.

On the other hand, as shown in FIG. 8, when the waveform 1 and the waveform 2 are out of phase, it means that the gain of the variable gain circuit 8 is too high, and the gain is lowered by the voltage difference of ΔV, and the waveform 2 is obtained. The indicated residual time axis variation is no longer extracted, and the DC components of waveform 4 and waveform 5 coincide and converge.

In this way, the automatic control of the amplitude of the time axis fluctuation is performed.

Next, an example using a CMOS inverter delay line as the variable delay line will be described with reference to FIG.

Since the circuit operation is similar to that of FIG. 1, its explanation is omitted.

The difference of this embodiment from FIG. 1 is that the time constant of the LPF 3 is increased and the time axis fluctuation contained in the video signal or the luminance signal input to the input terminal a (for example, eccentricity of the mechanical system is represented. Of the time axis fluctuations in the low frequency range, and the time axis fluctuations in the high frequency range represented by impact errors due to vibration of the tape during playback, etc.), only the time axis fluctuations in the low frequency range are tracked. is there. For this reason, the time axis fluctuations extracted by the sample hold circuit 6 are only the time axis fluctuations in the high frequency range. In general, the fluctuation amount differs between the low-frequency time axis fluctuation and the high-frequency time axis fluctuation, and the fluctuation amount of the high-frequency time axis fluctuation is considerably smaller. Therefore, in FIG. 2, the CMOS inverter delay line 12 is used as the delay line, and the variable range is reduced by controlling the number of inverter stages.

Since it is necessary to reduce the average delay time by reducing the variable range, the slope ratio of the sawtooth wave created by the sawtooth wave generators 7 and 20 is preset according to the delay time. ing. Other operations are the same as those in FIG.

In this way, the video signal or the luminance signal from which only the time base fluctuation in the high frequency range has been removed is output to the output terminal b.

[0050]

EFFECTS OF THE INVENTION The present invention is constructed as described above,
The feedforward type time axis correction circuit does not require the average delay time adjustment and the time axis variation adjustment extracted from the characteristics of the delay line or the circuit that drives the delay line, which are always performed. Moreover, the performance of the present invention does not deteriorate due to temperature characteristics and changes with time.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing another conventional example.

FIG. 5 is a waveform diagram for explaining the operation principle of the present invention.

FIG. 6 is a waveform diagram for explaining the operation principle of the present invention.

FIG. 7 is a waveform diagram for explaining the operation principle of the present invention.

FIG. 8 is a waveform diagram for explaining the operation principle of the present invention.

[Explanation of symbols]

 1 Sync Separation Circuit 2 Comparator 3 LPF 4 VCO 5 Frequency Divider 6 Sample Hold Circuit 7 Sawtooth Wave Generation Circuit 8 Variable Gain Circuit 9 VCO 10 CCD Delay Line 11 Sync Replacement Circuit 15 LPF 16 LPF 17 Comparator 18 Sync Separation Circuit 19 Sample hold circuit 20 Sawtooth wave generation circuit 21 Rectifier circuit 22 LPF 23 Adder circuit 24 Rectifier circuit 25 LPF 26 Comparator 27 Amplifier

Claims (1)

[Claims] 1. A first time-axis fluctuation detecting means having a first sawtooth wave generation circuit for extracting a time-axis fluctuation component from a video signal input to a variable delay line, and a first sample-and-hold circuit; A variable gain circuit for amplifying or attenuating the time axis fluctuation component for controlling the delay line; a second sawtooth wave generation circuit for extracting a residual time axis fluctuation component of the video signal output from the variable delay line; The second time-axis fluctuation detecting means having a second sample-hold circuit and the variable gain circuit control means connected to the first and second time-axis fluctuation detecting means comprise the first time-axis fluctuation detecting means and the The output from the second time axis fluctuation detecting means is supplied to the variable gain circuit control means to generate a variable gain circuit control signal, and the variable gain circuit is controlled by the variable gain circuit control signal. The time axis correction circuit is characterized in that the delay time of the variable delay line is controlled by.