JPH10248021A - Synchronizing feedback circuit and synchronizing feedback method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the synchronizing feedback circuit by which disturbance of an image and fluctuation in a gain or the like are not caused even on the occurrence of noise in an input signal such as a video signal and to provide the synchronizing feedback method. SOLUTION: A SYNC separator 2 separates a horizontal synchronizing pulse from an input image signal Vin from a DC offset circuit 1 and provides an output of it to a pulse generator 3 as a separator output signal S. The pulse generator 3 generates a clamp pulse K delaying the separator output signal S by a width of the horizontal synchronizing pulse and the clamp pulse K is fed to an operating pulse control section 30. When a pulse resulting from noise is included in the clamp pulse K, the operating pulse control section 30 interrupts the noise pulse and provides an output of a clamp pulse K' including only a proper pulse to a clamp detector 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous feedback circuit and a synchronous feedback method for clamping an input image signal such as a video signal to a reference voltage level and adjusting the gain thereof.

[0002]

2. Description of the Related Art Conventionally, as a synchronous feedback circuit of this kind, there is a clamp circuit as shown in FIG. This clamp circuit is a circuit used for a video tape recorder, and includes a DC offset circuit 1 and a sync separator 2.
, A pulse generator 3, a clamp detector 4, and a voltage / current conversion circuit 6. FIG. 9 is a time chart of signals indicating the operation of the clamp circuit. An input image signal Vin such as a video signal as shown in FIG.
Is input to the DC offset circuit 1 shown in FIG.
The input image signal Vin from the C offset circuit 1 is output to the sync separator 2 and the clamp detector 4. Then, in the sync separator 2, the vertical synchronizing pulse V and the horizontal synchronizing pulse H are separated as shown in FIG. 9B, and these are input to the pulse generator 3 as a separator output signal S. Then, as shown in FIG. 9C, the clamp pulse K is generated at the timing of the pedestal level of the input image signal Vin in the pulse generator 3 and output to the clamp detector 4.
As a result, the clamp detector 4 outputs the clamp pulse K
, The pedestal level of the input image signal Vin input from the DC offset circuit 1 is compared with the reference DC voltage V0, and the voltage difference ΔV is converted to the difference current ΔI by the voltage / current conversion circuit 6. . As a result, the DC offset circuit 1 clamps the pedestal level of the input image signal Vin to the reference DC voltage V0 so that the difference current ΔI becomes zero. By such a loop operation, the clamp circuit clamps the input image signal Vin so that the pedestal level becomes equal to the reference DC voltage V0 to suppress the fluctuation of the pedestal level.

[0003]

However, the above-described clamp circuit has the following problems. In a video tape recorder or the like, if the tape is played back fast forward or rewinded, noise is generated in the input image signal Vin, and the image in the noise portion disappears. That is, as shown in FIG. 10A, when a noise bar N occurs in an image A portion within one horizontal period of the input image signal Vin, as shown in FIG. Not only the synchronization pulse H but also the pulse S corresponding to the noise bar N
1 is also separated. As a result, as shown in FIG. 10C, the pulse generator 3 outputs not only a pulse corresponding to the horizontal synchronization pulse H but also a clamp pulse K including an extra pulse K1 to the clamp detector 4. . As described above, the clamp detector 4 is operated by the input of the clamp pulse K. Accordingly, 10 pulses of the image A are generated by the pulse K1 in the clamp pulse K.
The 0% white portion is leveled down to the reference DC voltage V0, and the image A disappears.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a synchronous feedback circuit and a synchronous feedback circuit that do not generate disturbances such as an image and a gain even if noise occurs in an input signal such as a video signal. It is intended to provide a way.

[0005]

In order to solve the above-mentioned problems, a synchronous feedback circuit according to the present invention is operated by a predetermined operation pulse, and adjusts a voltage level or a gain of an input image signal; An operation pulse generation unit that generates an operation pulse synchronized with the synchronization signal of the image signal or delayed by the synchronization signal width, and is interposed between the adjustment unit and the operation pulse generation unit. An operation pulse control unit for interrupting the pulse is provided. With this configuration, when the input image signal is input to the operation pulse generation unit, an operation pulse that is synchronized with the synchronization signal of the input image signal or delayed by the synchronization signal width is generated. At this time, if a pulse generated by noise is included in the operation pulse, the operation pulse is cut off by the operation pulse control unit, and only a normal operation pulse is output to the adjustment unit.
Then, the adjusting section is operated by the operation pulse, and the voltage level or the gain of the input image signal is adjusted. Further, the present invention generates an operation pulse synchronized with the synchronization signal of the input image signal or delayed by the synchronization signal width, and compares the pedestal level or the sync tip level of the input image signal with the constant reference voltage level by the operation pulse. In the synchronous feedback method of adjusting the voltage level or the gain of the input image signal based on the comparison result, a pulse generated due to noise among the operation pulses is cut off.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a synchronous feedback circuit according to a first embodiment of the present invention. Note that the same elements as those shown in FIG. 8 are described with the same reference numerals. This synchronous feedback circuit is a clamp circuit applied to a video tape recorder, and includes an adjustment unit 10, an operation pulse generation unit 20, and an operation pulse control unit 30, as shown in FIG.

The adjusting section 10 is a section for clamping the input image signal Vin, and has a DC offset circuit 1, a clamp detector 4, a voltage / current conversion circuit 6, and a time constant capacitor 7. The DC offset circuit 1 receives the input image signal Vin based on the difference current ΔI from the voltage / current conversion circuit 6.
Is output to the reference DC voltage V0. The output side of the circuit is a clamp detector 4 and an operating pulse generator 2.
0. The input side of the clamp detector 4 is connected to the output side of the operation pulse generator 20, and the output side is connected to the voltage / current conversion circuit 6 and the time constant capacitor 7. The clamp detector 4 is operated by the clamp pulse K 'from the operation pulse control section 80 for the pulse width time.
Has a function of comparing the pedestal level of the input image signal Vin from the DC voltage V0 with the reference DC voltage V0 and outputting a difference voltage ΔV. The voltage / current conversion circuit 6 converts the difference voltage ΔV from the clamp detector 4 into a difference current ΔI,
This circuit outputs to the offset circuit 1 and has a time constant capacity of 7
Is a capacitor for holding the difference voltage ΔV from the clamp detector 4.

The operation pulse generating section 20 is a section for generating a clamp pulse K (operation pulse) of the input image signal Vin from the DC offset circuit 1 at a pedestal level timing, and has a sync separator 2 and a pulse generator 3. doing. The sync separator 2 outputs a vertical synchronization pulse V of the input image signal Vin from the DC offset circuit 1.
And a horizontal synchronizing pulse H, and outputs a separator output signal S, the output side of which is connected to the pulse generator 3. The pulse generator 3 outputs the separator output signal S from the sync separator 2
Has the function of generating a clamp pulse K at the timing of the pedestal level based on
The operation pulse control unit 30 is connected.

The operation pulse control section 30 is a section for outputting only a pulse corresponding to the pedestal level to the clamp detector 4 among the clamp pulses K from the pulse generator 3. FIG. 2 is a circuit diagram of the operation pulse control unit 30. As shown in FIG.
Is a grounded PNP type bipolar transistor 31 having a base as an input terminal of the control pulse C, an emitter connected to the emitter of the transistor 31, a connection point to which a constant current source is connected, and a base connected to the control pulse C. A PNP-type bipolar transistor 32 to which a slice voltage V1 is applied. The collector of the transistor 32 grounded via the resistor 33 is connected to the base of the NPN bipolar transistor 34, and the emitter of the transistor 34 is grounded. The collector of the transistor 34 is connected to the output terminal of the pulse generator 3, and the collector connection point is set as the output terminal 35 and connected to the input terminal of the clamp detector 4. With such a circuit configuration, when the control pulse C is at the high level, the clamp pulse K from the pulse generator 3 is set to the ground level and erased. When the control pulse C is at the low level, the clamp pulse K is output from the output terminal 35 as it is. Output. The control pulse C input to the operation pulse control unit 30 is a dropout pulse output from a head amplifier (not shown) of the video tape recorder. That is, a dropout pulse, which is a reproduction envelope of a missing signal, is input to the base of the transistor 31 as a control pulse C.

Next, the operation of the clamp circuit of this embodiment will be described. It should be noted that the clamp circuit of this embodiment also specifically achieves the synchronous feedback method of claim 4 during its operation. FIG. 3 is a time chart of each signal during operation. As shown in FIG. 3A, when a noise bar N is generated in the image A portion of the input image signal Vin due to reproduction fast forward or fast rewind of the video tape recorder, the noise bar N is output from the sync separator 2 of the operation pulse generator 20. Separator output signal S
Includes a pulse S1 corresponding to the noise bar N as shown in FIG. Therefore, as shown in FIG. 3C, the clamp pulse K including the extra pulse K1 is output to the operation pulse control unit 30.
In parallel with the above operation, signal loss due to the noise bar N is detected by a head amplifier or the like, and a control pulse C indicating the envelope is input from the head amplifier or the like to the base of the transistor 31 of the operation pulse control unit 30. . Specifically, as shown in FIG. 3D, a high-level control pulse C having a width substantially equal to the width of the noise bar N, that is, a width including all the pulses K1, is applied to the transistor 31
Is input to Therefore, when the pulse K1 is input from the pulse generator 3 to the output terminal 35 side of the operation pulse control unit 30, the output terminal 35 becomes the ground level, the pulse K1 is erased, and there is no output to the clamp detector 4. When a normal clamp pulse K generated at the timing of the pedestal level is input to the output terminal 35, the control pulse C becomes low level.
The data is output from the output terminal 35 as it is. As a result, as shown in FIG. 3E, the normal clamp pulse K ′ from which the extra pulse K1 caused by the noise bar N has been removed is input from the output terminal 35 to the clamp detector 4.

When the clamp pulse K 'is input to the clamp detector 4, the clamp detector 4 operates for the width time of the clamp pulse K', and the pedestal level of the input image signal Vin input from the DC offset circuit 1 and the reference DC. Is compared with the voltage V0, and the difference voltage ΔV is
It is output to the current conversion circuit 6 and the time constant capacitor 7. Then, the difference voltage ΔV is converted into a difference current ΔI in the voltage / current conversion circuit 6 and input to the DC offset circuit 1.
In the DC offset circuit 1, the pedestal level of the input image signal Vin is moved so that the difference current ΔI becomes zero, and the pedestal level is offset to the reference DC voltage V0.

As described above, according to the clamp circuit of this embodiment, even if the noise bar N occurs in the image A portion of the input image signal Vin and the pulse K1 caused by the noise bar N occurs in the clamp pulse K, The pulse K1 is erased by the operation pulse control unit 30, and the clamp pulse K 'including only the normal pulse generated at the timing of the pedestal level is output to the adjustment unit 10, so that noise occurs at the time of fast forward reproduction or fast rewind. However, a normal clamping operation can be performed without being affected by the noise.

(Second Embodiment) In the first embodiment, a dropout pulse is used as the control pulse C to be input to the operation pulse control unit 30.
The second embodiment differs from the first embodiment in that a pulse synchronized with the horizontal synchronization pulse H is used as the control pulse C instead of the dropout pulse. FIG.
FIG. 3 is a circuit diagram of a control pulse generation circuit that generates the control pulse C as described above. As shown in FIG. 4, the control pulse generation circuit 40 includes a collector-connected NPN type bipolar transistor 41 having a collector connected to a constant current source and inputting a clock f from a base via a resistor, and a collector of the transistor 41. The connected capacitor 42 and a PN connected after the capacitor 42 and functioning as a limiter of the limiter voltage V2.
P-type bipolar transistor 43 and transistor 43
An NPN-type bipolar transistor 44 having a base connected to the subsequent stage, and an emitter connected to the transistor 44;
An NPN bipolar transistor 45 having a constant current source connected to the connection point is provided. The adjustable slice voltage V3 is applied to the base of the transistor 45, and the collector of the transistor 44 is connected to the output terminal 46 via a current mirror circuit. The clock f is a clock pulse synchronized with the horizontal synchronization pulse H of the input image signal Vin, and is formed by a microcomputer (not shown).

With this configuration, when the clock f shown in FIG. 5A is input to the base of the transistor 41,
Transistor 41, capacitor 42, transistor 43
As shown in FIG. 5B, a constant-level clock fl having a ramp a is generated and input to the base of the transistor 44. Then, the clock fl is shaped by the transistor 44 and the transistor 45 at the level of the slice voltage V3, and as shown in FIG. 5C, has a low level with a width up to the intersection of the ramp a of the clock fl and the slice voltage V3. Control pulse C
Is generated. This control pulse C is output from the output terminal 4
6 to the operation pulse control unit 30.

Next, the operation of the clamp circuit of this embodiment will be described. FIG. 6 is a time chart of each signal during operation. In the first embodiment, the case where the noise bar N occurs only within one horizontal period of the input image signal Vin has been described. However, actually, FIG.
As shown in (1), the noise bar N often occurs over several horizontal periods. In such a case, in the clamp circuit according to the first embodiment, as shown in FIG. 6B, the operation pulse control unit 30 is operated with the control pulse C having the noise bar N width, so that the noise bar N width is reduced. Since the pulses included in the section are deleted, even the normal clamp pulse K2 corresponding to the horizontal synchronization pulse H2 during that period is deleted. As a result, as shown in FIG. 6C, the clamp pulse K ′ from which the normal clamp pulse K2 has passed is input from the operation pulse control unit 30 to the clamp detector 4. 1 missing clamp pulse K2
In this case, the pedestal level of the input image signal Vin can be maintained at the reference DC voltage V0 by the charging power of the time constant capacitor 7, but when the noise bar N extends over many horizontal periods, a large number of Clamp pulse K2
, And cannot be maintained with the time constant capacity 7. On the other hand, according to the second embodiment, the magnitude of the slice voltage V3 applied to the transistor 45 shown in FIG. 4 is adjusted, and the sync tip level width and the pedestal level are adjusted as shown in FIG. The control pulse generation circuit 40 generates a control pulse C which has a width substantially equal to the sum of the widths and becomes a low level. As a result, the operation pulse control unit 30
Will output only a normal clamp pulse corresponding to the horizontal synchronizing pulse H among the clamp pulses K input from the pulse generator 3, and as shown in FIG. K ′ is input to the clamp detector 4.

As described above, according to the clamp circuit of this embodiment, even when the noise bar N occurs over many horizontal periods, a normal clamp operation can be performed without any movement. The other configuration and operation and effect are the same as those of the first embodiment, and thus description thereof is omitted.

The present invention is not limited to the above-described embodiment, and various modifications and changes can be made within the scope of the present invention. In the above embodiment, the case where the pedestal level of the input image signal Vin is clamped to the reference DC voltage V0 has been described.
By generating a clamp pulse synchronized with the separator output signal S from the pulse generator 3 in the pulse generator 3, the sync tip level of the input image signal Vin can be clamped to a predetermined voltage level. In the above embodiment, the operation pulse control unit 30 cuts off the clamp pulse due to the noise from the pulse generator 3 when the control pulse C is at the high level. 30 may cut off the clamp pulse K. Further, in the above-described embodiment, the clamp pulse K from the pulse generator 3 is limited by configuring the operation pulse control unit 30 as shown in FIG. 2, but the current source of the pulse generator 3 is turned on and off. Thus, only a normal clamp pulse can be output. FIG. 7 is a circuit diagram showing an example of such an operation pulse control unit. The operation pulse control unit 50 includes a PNP-type bipolar transistor 51 having a base as an input terminal of the control pulse C;
A transistor 51 has a PNP-type bipolar transistor 52 connected to the emitter, a constant current source is connected to the emitter connection point of the transistors 51 and 52, and a slice voltage VI of the control pulse C is applied to the base of the transistor 52. ing. The collector of the transistor 51 is connected to the collector of an NPN bipolar transistor 53 whose emitter is grounded. The collector and the base of the transistor 53 are short-circuited, and the base is connected to the base of the NPN bipolar transistor 54. Transistor 5
The emitter of 4 is grounded, and the collector is connected to the current source of pulse generator 3. Thus, when the control pulse C is at a high level (or a low level), the transistor 54 is turned on, the current of the pulse generator 3 is released, and the pulse generator 3 can be turned off. Further, the direction of the constant current source of the operation pulse control unit 30 in the above embodiment is reversed, and the NPN transistor is replaced with a PNP transistor.
Even if the PNP transistor is changed to the NPN transistor, the same function can be obtained. further,
In the above-described embodiment, an example in which the synchronous feedback circuit is applied to the clamp circuit has been described. However, for example, the present invention can also be applied to an AGC circuit that adjusts the gain of the input image signal Vin at the sync chip level. That is, the input image signal Vin
It is also possible to generate an AGC pulse synchronized with the horizontal synchronization pulse H in the operation pulse generator, and to cut off a pulse generated by noise from the AGC pulse in the operation pulse controller. As a result, it is possible to obtain a high-performance AGC circuit in which the gain does not vary due to noise.

[0018]

As described above in detail, according to the first and fourth aspects of the present invention, even if a pulse generated by noise is included in the operating pulse, the operating pulse control unit controls these pulses. Since the cutoff is performed and only the normal operation pulse is output to the adjustment unit, there is an excellent effect that the voltage level or the gain of the input image signal can be accurately adjusted.

According to the second aspect of the present invention, since the operating pulse generating section is operated by the control pulse having a width corresponding to the width of the noise, even if the pulse generated by the noise is included in the clamp pulse, the operation pulse is generated. The pulse is cut off, and there is an effect that an accurate clamping operation can be performed.

According to the third aspect of the present invention, even if a normal clamp pulse is mixed in a pulse generated by noise, the clamp pulse is reliably passed without being cut off by the operation pulse control unit. There is an effect that a more accurate clamping operation can be guaranteed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a synchronous feedback circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an operation pulse control unit of FIG. 1;

FIG. 3 is a time chart of each signal during operation.

FIG. 4 is a circuit diagram of a control pulse generation circuit which is a main part of a synchronous feedback circuit according to a second embodiment of the present invention.

FIG. 5 is a time chart illustrating an operation of the control pulse generation circuit.

FIG. 6 is a time chart of signals when the synchronous feedback circuit according to the second embodiment operates.

FIG. 7 is a circuit diagram showing a modification of the operation pulse control unit.

FIG. 8 is a block diagram of a clamp circuit according to a conventional example.

FIG. 9 is a time chart of signals showing the operation of the clamp circuit of FIG. 8;

FIG. 10 is a time chart of a signal when noise occurs.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DC offset circuit, 2 ... Sink separator, 3 ... Pulse generator, 4 ... Clamp detector, 6 ... Voltage / current conversion circuit, 1
0: adjustment unit, 20: operation pulse generation unit, 3
0 ... operation pulse control unit.

Continuation of the front page (72) Inventor Taketoshi Nishi 5-1 Noguchikita, Kokubu City, Kagoshima Prefecture Sony Kokubu Corporation

Claims (4)

[Claims] 1. An adjusting unit which is activated by a predetermined operation pulse and adjusts a voltage level or a gain of an input image signal, and generates the operation pulse synchronized with a synchronization signal of the input image signal or delayed by a synchronization signal width. An operating pulse generating unit that is interposed between the adjusting unit and the operating pulse generating unit, and an operating pulse control unit that blocks a pulse generated by noise among the operating pulses. Synchronous feedback circuit. 2. The synchronous feedback circuit according to claim 1, wherein the adjusting unit is operated by a clamp pulse, and the pedestal level or the sync tip level of the input image signal is equal to a constant reference voltage level. The operation pulse generator is configured to clamp the input image signal, wherein the operation pulse generator is configured to generate the clamp pulse synchronized with the synchronization signal of the input image signal or delayed by a synchronization signal width. A synchronous feedback circuit which is operated by a control pulse having a width corresponding to the width of the noise, and interrupts a pulse from the operation pulse generating section only during this operation. 3. The synchronous feedback circuit according to claim 1, wherein the adjusting unit is operated by a clamp pulse, and the pedestal level or the sync tip level of the input image signal matches a constant reference voltage level. The operation pulse generator is configured to clamp the input image signal, wherein the operation pulse generator is configured to generate the clamp pulse synchronized with the synchronization signal of the input image signal or delayed by a synchronization signal width. The control pulse is synchronized with the clamp pulse and is activated by a control pulse having a width not less than the clamp pulse width and not more than the sum of the pedestal level width and the sync tip level width. A synchronous feedback circuit for passing pulses from 4. An operation pulse synchronized with a synchronization signal of the input image signal or delayed by a synchronization signal width is generated, and the operation pulse compares a pedestal level or a sync tip level of the input image signal with a fixed reference voltage level. A synchronous feedback method for adjusting a voltage level or a gain of the input image signal based on a result of the comparison, wherein a pulse generated by noise among the operation pulses is cut off; .