JPS6276387A - Afc detection circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a frequency fluctuation in a phase-locked point by providing a circuit that generates a detection current in a period when the output of a voltage controlled oscillator is shifted from the fixed width to a dividing signal in the phase-locked point. CONSTITUTION:As for a phase difference between a horizontal synchronizing pulse and the dividing signal of the voltage controlled oscillator, the polarity of the detection current is switched within a horizontal synchronizing period according to the position of the period at the circuits of transistors TRs 6-10. By changing the voltages of output terminal capacitors C1 and C2 in the circuit, a negative feedback loop as the control voltage of the voltage controlled oscillator is formed. A pulse having a fixed width to the dividing signal of the voltage controlled oscillator at the phase locked point of the output of the voltage controlled oscillator from a horizontal synchronizing pulse (a) is generated with a monostable multivibrator and a pulse signal generated in the period shifted from the phase locked point is generated at the circuit of TRs 15-20, thereby generating the detection current only in the period.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a home video tape recorder (hereinafter referred to as VT).
This invention relates to an AFC detection circuit in a color synchronization circuit (referred to as R).

[Technical background of the invention]

In a VTR, for example, when recording an 8■VTR, a signal with a sum frequency of 4.27 MHz, which is a combination of a reference 3.58 MHz signal locked to a burst signal and a signal with a horizontal frequency of 47·τX fl, and a recording color are used. Combined with the signal and the difference frequency is 47.7fii (743kHz)
Perform low-frequency conversion of the color signal to YFM signal and AFM
The superimposed signal of the 1st signal and the girot signal is recorded on the υ tape using a video nit.

Furthermore, during reproduction, the reproduced low-frequency conversion color signal is converted to 3.58 MHz using an AFC (automatic frequency control) and APC (automatic phase control) loop as shown in Figure 4, and is overlapped with the reproduced Y signal. There is a color signal reproduction method to obtain the video signal.

In the AFC loop 100 shown by the dotted line in FIG. The output of the city counter 3 is also input to the phase comparator 1.

This counter 3 counts down the output of the voltage controlled oscillator 2 at intervals of t and outputs No. 11. The phase with this fyo signal is compared with the phase comparator 1, and the deviation is calculated as a voltage. Controlled oscillator 2VC voltage iti! I (i+-41) The excavator 2 outputs the horizontal synchronizing signal a and the center frequency of 378fH to the sensor 3 so that there is no difference in center frequency, thereby forming a negative feedback loop f. A signal having a frequency 378 times the horizontal synchronization frequency is obtained.

The output of the voltage controlled oscillator 2 is also sent to the pilot signal generating circuit 200 and the centrifuge frequency divider 4.

In addition, the 1 frequency divider 4 divides the frequency of the entire output of the voltage controlled oscillator 2 and is also used to generate the color conversion signals 47 and 7fEL and the pilot signal for ATF. The 4.3 kHz signal output from 7 and the 3.58 MHz signal from variable voltage oscillator 6 are applied to frequency converter 5 to convert the frequency to 4.27 MHz and send it to frequency converter IO. It has become.

This frequency converter 10 outputs 4.2 of the output of the frequency converter 5.
7 MHz and the reproduced low frequency conversion color signal b (743 kHz) are all input, frequency conversion is performed, and the output is sent to the comb filter 9, which outputs a 3.58 MHz signal.

This output signal is sent to a phase comparator 7, where the phase is compared with a 3.58 MHz reference signal from a reference signal generator 8, and the comparison result is output to a fully variable voltage oscillator 6.

In FIG. 4, a circuit as shown in FIG. 5 is sometimes used as the phase comparator 1 constituting the AFC loop ZOO. In this figure 5, figure 6 (for)
A horizontal synchronizing signal a as shown in 1 constitutes a differential amplifier.
In addition to the pace of the pair of transistors Tr1 t Trl, both emitters of which are grounded via a constant current source 300, turn on transistors Tr1 + Tr2 during the horizontal synchronization pulse of this horizontal synchronization signal a, and turn on transistors T
A power supply vce is supplied to the collector of rl, and the output from the collector of transistor Tr2 is applied to the emitters of a pair of transistors Tr3 and Tr4 forming a differential amplifier.

Figure 6 also shows the pace of transistors Tr3 and Tr4.
The output of the fourth "counter" is added. Therefore, the phase comparison is performed by the transistors Trs and Tr4 during the horizontal synchronization pulse period of the horizontal synchronization signal a.

The collectors of the transistors Tr3 + Tr4 are connected to the collectors of the transistors Trs r Trg and the paces of the transistors 'pr7 and Trs, respectively. The collector and pace of the transistors Tr6 r Trg are connected to each other, and each emitter is connected to the power supply Vcc via resistors R1, R,', respectively.

The emitter of the transistor "7rTrg" is connected to the power supply vac via resistors R3 and R4, respectively.

The collectors of the transistors Tr, lTrs are connected to the collectors of the transistors Tr1G, rTrg, v), respectively.

The emitter of transistor Tr161 Trg is resistor R5
, Ft6' (grounded through the transistor Tr1
The pace and collector of transistor 6 are directly connected to the pace of transistor Tr.

The collector of the transistor Tr8 is grounded via a capacitor C1, and also connected to the ground via a resistor R7 and a capacitor C2, and further connected to the input terminal of the voltage fiil controlled oscillator 2 shown in FIG.

Transistor Trl l Tr! A horizontal synchronizing signal a is added to the pace of the transistor Tr during the pulse period.
When l is on, the constant flow ■. flows to the transistor Trl, and during the horizontal synchronizing pulse period of the horizontal synchronizing signal a by the transistors Tr31 to Tr4 (due to the phase difference with the -L vco signal), the transistor Tr3 or Tr4 is turned on and the transistor Tr6 is turned on. p Trs k Turn on or off δ.

When the transistor Tr is on, the transistor Tr8
is turned on, and at this time the transistor Tr5 y Tr
7 # T'rlOI Trg is turned off. When the transistor 'frl is turned on, the capacitor C1 is photoelectrically charged.

Furthermore, when the transistor Tr8 is off, the transistor T
ry + Trl(1p Trg is turned on and the charge of capacitor C1 is discharged through transistor Tre.

In this way, the charging and discharging time of the capacitor C1 is changed by p depending on the phase difference between the horizontal synchronizing signal and the 378 VCO, and the current 2 is changed as shown in Section 6 (c). Control voltage to voltage controlled oscillator 2 (Fig. 6(d)
The voltage at point A shown by K) is changed.

During other periods, transistors Tr. and Trg are cut off. In the case of phase locking, if the charging current and the discharging current are selected so that the charging charge of the capacitor C1 and the discharging charge are approximately equal, the charging period and the discharging period can be made equal. are equal.

Note that it is desirable that the voltage at point A in FIG. 5 not have a dotted line portion, as shown in FIG. 6 (6).

[Problems with the backloft technique]

In the above case, during the horizontal synchronization period a, the voltage at point A rises as shown in Figure 6, the frequency of the voltage controlled oscillator becomes flat during that period, and during the other periods it becomes lower than the target frequency. The phase will be locked so that the sum of the shim-cycle period and the 379 period of the voltage controlled oscillator match.

Additionally, if a phase complement tl such as resistor R2 and capacitor C2 and a gain adjustment circuit are installed, charge will be charged to capacitor C2 during the horizontal synchronization period, so charge will move from capacitor C2 to 01 during periods other than horizontal synchronization. As a result, the phase lock point is slightly shifted from the center, resulting in A as shown in Figure 6(d).
The voltage at the point 9 and the frequency gradually change.

As described above, the color conversion frequency and the ATF/#lot signal deviate from the target frequency, and frequency changes occur within the IH period, resulting in adverse effects such as a change in one hue and fluctuations in the ATF detection signal9.

[Purpose of the invention]

The present invention was made to eliminate the above-mentioned conventional drawbacks, and an object of the present invention is to provide an AFC detection circuit in which no frequency change occurs at the phase lock point.

[Summary of the Invention] The AFC detection circuit of the present invention has a phase difference between a horizontal synchronizing pulse and a frequency-divided signal of a voltage-controlled oscillator. By switching the polarity in the first circuit and changing the voltage of the capacitor connected to the output terminal of this first circuit in the second circuit,
Form a negative feedback loop as a voltage controlled oscillator control voltage,
A fixed-width pulse from the horizontal synchronization pulse to the divided signal of the voltage-controlled oscillator at the phase-lock point of the output of the voltage-controlled oscillator is generated using a gold monomultivibrator. The circuit of No. 3 is designed to generate a detection current only during the operation period.

[Embodiments of the invention]

Embodiments of the 0AFC detection circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of one embodiment. Components in FIG. 1 that are the same as the circuit in FIG. 4 are given the same reference numerals, and their explanation will be omitted, and only the parts that are different from FIG. 4 will be explained.

The transistor T'rtt l Trl2 is made of a differential annealing metal, and both bases are applied with the horizontal synchronizing signal a, and both emitters are grounded via a constant current source SOO. The base is connected to the collector of the transistor Tr1.

The collector of the transistor Tr1z is the transistor Tr1
3 t Connected to the emitter of Trs4. The collector of the transistor Tr13 is connected to the collector and base of the transistor TrlB. Similarly, the collector of the transistor Tr14 is connected to the transistor T'! '1
It is connected to the collector and base of g.

Each emitter of the transistor Tr15+T'rts is connected to the power supply vecVc via resistors R8 and R9f. The bases of the transistors TrlsF and Tr16 are connected to the bases of the 5° transistors Tr+y r and Trlg, respectively. The collector of the transistor Tr17 is connected to the base and collector of the transistor TrG, and the collector of the transistor Tr2 (+) is connected to the base of the transistor TrB.

The collector of the transistor TrH is connected to the collector VC of the transistor TrB, and the collector of the transistor TrH is connected to the collector VC of the transistor TrB.
r8 r Connected to the collector of Tr@. Each emitter of transistor Tr2o+ Trlg is connected to resistor R12
, RI3.

On the other hand, the horizontal synchronization signal a is transmitted to the mono multivibrator 4.
00 is becoming more manpower intensive.

The output terminals of this mono multivibrator 400 are resistor R
It is connected to the base of the transistor Tr14 via I6f.

Output terminal Q of mono multivibrator 40θ (d resistance R
It is connected to the base of the transistor Tr13 via the resistor R17f, and further connected to the base of the transistor Tr14 via the resistor R15°R14. A connection point between resistors R14 and R15 is connected to the base of transistor Tr4.

Next, the operation of the AFC detection circuit of the present invention will be explained in FIGS. 2 and 3.
This will be explained using the time chart shown in the figure. Figure 2 is AF
Fig. 3 shows the case where C. Rogue pulls in, and a y s
This shows a case where the phase of the VCO is shifted.

In the conventional example shown in Fig. 4, if the resistor R7 and capacitor C2'f are ignored, at the lock point, if the charging current and discharging current are set equal, the rising point of the VCO signal will be the horizontal synchronizing signal. At the center position of a,
Charge charge and release of C1! Since the charges are equal, the voltage at both ends of the capacitor CI remains constant during periods other than horizontal synchronization and zeros.

That is, the horizontal synchronizing signal A (Fig. 2(&)) and 3
7s vco (Fig. 2(b)) is synchronized, the horizontal synchronizing signal a is
Z is turned on and 5Z is applied to transistor Tr2! flowing ro
flows, transistors Tr41 and Tr6 turn on and 71
p, transistor TrB is turned on. At this time, transistor Tr3 * Tr61 Tr7 r Trto
1Tr9 is turned off. When the transistor Trg is turned on, a charging current 1 of the current C flows as shown in FIG. 2(C) at the point P and A.

Also, horizontal synchronization signal a or mono multivibrator 400
1d shown in FIG. 2(d) is output from the output terminal Q of this mono-multivibrator 4θ0. This output is applied to the base of the transistor T'r13TTiB2, which turns on the transistor Tr14, which turns on the transistor Tr1g, whose collector is connected to the output of the capacitor CI as shown in Figure 2 (6) VC. 'Mixed flow r2 flows. At this time, as shown in FIG. 2(f), electric current! is 0, and the voltage at point A is shown in Figure 2-)
It is constant like .

Next, a case where the phase of the 378 VCO deviates from the horizontal synchronization signal a will be described. In this case, with respect to the horizontal synchronization signal shown in Figure 3 (-), as shown in Figure 3 (b), the phase of the VCO is shifted, as shown in Figure 3 (C). , charging current It of capacitor CI
and the discharge current 1 of the capacitor C1 shown in FIG. 3(f). becomes unbalanced, and the voltage across capacitor C1 changes as shown in FIG. 3(d) without the circuit added by the present invention.

In the example of FIG. 3, this voltage is high. As a result, the charge increased during the period other than the horizontal synchronization is charged to the capacitor C2 through the resistor R7, resulting in a waveform as shown in FIG. 3(d). Therefore, the voltage at point A gradually increases, and the phase 4) becomes positive.

However, in the present invention, a Norse with a width of 1/2 of the synchronizing signal is generated from the horizontal synchronizing signal a using a monomultipibrator 400, and its output terminal Q is generated.

It is added to the pace of the transistor Tr1g*Tr14 of the differential amplifier via the Qf resistors R16 and R17.

In addition, the horizontal synchronization period 8 is the transistor Trll 1Tr
A constant current of 1.2 is applied to the 12 differential amplifiers and is applied to the transistor Tr1H only during the horizontal synchronization period. flows.

During the first half of the horizontal synchronization period, transistor Tr15 turns on, and transistor Tr17 +Tr2
No current is applied to @l'rr1e, and a discharge current (1. in FIG. 3(f)) is applied to point N. A charging current is applied during the latter 172 periods. Therefore, at the lock point, the current flowing into and out of capacitor CI is almost 0.
become. However, a photoelectric current that compensates for the slight escape of charge during the holding period is generated due to a slight shift in the lock point.

Therefore, there is almost no voltage change at point A, and constant oscillation of the voltage controlled oscillator continues. When the phase shifts, as shown in Figure 3-) in the example of Figure 3, twice the charging current flows only during the phase shift, causing the same amount of voltage change across capacitor C1 as in the conventional example. Born, conventional f! /1
j Generate a correction voltage roughly the same as that of j.

In this example, the photoelectric current and discharge current were set equal, but
Even if they are different, it is possible if the pulse width of the output of the mono multivibrator 400 is set to the same position as the lock point.

〔Effect of the invention〕

As explained above, according to the AFC detection circuit of the present invention, it is possible to eliminate the change in the control voltage of the voltage controlled oscillator at the phase lock point, and it is possible to configure an AFC Luso with little frequency change of the voltage controlled oscillator. As a result, a color synchronization circuit with little hue change can be realized, and a stable ATF-matrix signal can be generated.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the AFC detection circuit according to the present invention, Figure 2 is a time chart when the loop of the above AFC detection circuit is pulled in, and Figure 3 is a case where the phase of the above AFC circuit is shifted. Fig. 5 is a circuit diagram of the AFC detection circuit in the color synchronous circuit of Fig. 4, and Fig. 6 is a circuit diagram of the AFC detection circuit in the color synchronous circuit of Fig. 5.
It is a waveform diagram of each part of an FC detection circuit. Trl~Trz6...transistor, C1, C2...
・Capacitor, R1-R15...Resistance, 400...
Monomulti pipe lake. Patent attorney Suzue Takehiko (f) Dent.
130-Once 112--211 Upper 11 Figure 2 Figure 3 Figure 6

Claims (1)

[Claims] a first circuit that changes the phase difference between the horizontal synchronization pulse and the frequency division signal of the voltage controlled oscillator and switches the polarity of the detection current within the horizontal synchronization period according to the position of the frequency division signal within the horizontal synchronization period;
A second circuit constitutes a negative feedback loop as a control voltage of the voltage controlled oscillator by changing the voltage of the capacitor connected to the output terminal of the circuit, and the phase of the output of the voltage controlled oscillator from the horizontal synchronizing pulse is changed. A mono multivibrator that generates a fixed-width pulse up to the voltage-controlled oscillator frequency division signal at the lock point, and a third device that generates a pulse signal that occurs during a period deviated from the phase lock point and generates a detection current only during that period. An AFC detection circuit comprising a circuit.