JPS6273742A - Laying out method for integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the integration of an integrated circuit by alternately disposing wiring layers of multilayer low resistance metal in a direction perpendicular to a channel direction and a direction parallel thereto. CONSTITUTION:The channel directions of P-channel MOS transistors 17, 18 and N-channel MOS transistors 19, 20 are X-direction, and aluminum wirings 4-9, 10-14, F of the first layer are disposed in Y-direction. Aluminum wirings A, B, C, D, E, G H, VCC and VSS of the second layers are disposed in X- direction, the electrodes of the transistors 17-30 and polycrystalline silicon layers 21-25 are connected through a contacting region 16 with aluminum wirings of the first layer, which is connected via a through hole 15 with the aluminum wirings of the second layer. When thus layed out, the transistors 17-20 can be formed under the aluminum wirings, and the channel lengths and widths of the transistors 17-20 are not limited in size, thereby setting them in the optimum size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention is directed to a toy-out method for integrated circuits, particularly in which a low-resistance metal wiring layer is used. [Regarding the circuit design and Iaud method.

[Conventional technology]

In the conventional integrated circuit layerer 1 method, which uses a single layer of low-resistance metal wiring R (mostly Ae wiring), a MOS transistor is placed under the wiring layer and used as a gate electrode. A method of wiring between transistors using a polycrystalline silicon layer and a diffusion layer, which is also used as the source and drain of a transistor, in combination with a wiring layer. There is a gate matrix method in which a lattice is formed, MOS transistors are formed at the intersections thereof, and interconnections between the MOS 1 and the transistors are made using a wiring layer 3.

Layer 1 methods using two wiring layers include gate array and building pro ivy layout methods.

(Problems to be Solved by the Invention) In the conventional integrated circuit layerer method described above, as the number of integrated gate circuits increases, the wiring overhead increases to 1.5 times the number of circuits. The wiring situation becomes dramatically more complicated, and the layout method based on the - layer wiring layer C1: requires extensive use of diffusion layers or polycrystalline silicon layers as wiring, or There is no choice but to perform wiring at the expense of increased wiring, but in the former case, this leads to increased wiring resistance and increased parasitic capacitance, deteriorating the performance of the integrated circuit, and in the latter case, the increase in chip area is This has the disadvantage that the number of integrated circuit chips that can be obtained from one single wafer is reduced, making the chips more expensive.

Furthermore, there is a drawback that it takes a very long time to install the wiring due to the complexity of the wiring situation.

On the other hand, in the layout using the gate matrix method,
The wiring condition is simple, and the wiring period is short, but since the polycrystalline silicon layer is used as wiring and is arranged in parallel at a constant pitch, the degree of integration is low, and the long wiring in the polycrystalline silicon layer is easy to use. However, the parasitic resistance deteriorates the performance.

In addition, in the layout method of the G/Array/I and building block method using two low-resistance metal layers as wiring layers, NA, ND, and N are used.

Because the layout area for cells containing circuits and the interconnection area between cells are separately provided to perform layerer I, the chip area becomes large and
), the cell is created with a margin in the fan-out I-number, so the size of the Mo3t-transistor constituting the cell is not optimal, and there is a drawback that the performance as an integrated circuit chip is degraded.

An object of the present invention is to provide an integrated circuit layerer 1 method that can realize a high-integration, high-performance integrated circuit, improve layout complexity, and shorten the layerer 1 period.

[Means for solving problems]

In the integrated circuit layerer method 1 of the present invention, the channel directions of the MOS transistors constituting at least two or more logic gate circuits are the same, and the J-th layer of low resistance metal is arranged in the direction perpendicular to the channel direction. Layer wiring layer 1
, a second layer of low-resistance metal is disposed on top of the first wiring layer in a direction parallel to the channel direction, and the first wiring layer and the second layer are connected to each other. The wiring layers are arranged alternately.

1. Examples] Next, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an integrated circuit constructed as a layerer 1 using an embodiment of the present invention.

In FIG. 11, P-channel type MOS transistors 17 and 18 and N-channel type MOS transistors 19
．． The channel direction of No. 20 is the X direction, and the Ag of the first layer
Wirings 4 to 9, 10 to 14, and F are arranged in a direction perpendicular to this, that is, in the Y direction. Also, the second layer Ae wiring A, B, C, D.

E, G, H, Vcc and V55 are arranged in the same X direction as the channel direction, and MOS 1 to transistors 17 to 2
0 and polycrystalline silicon layers 21 to 25 are connected to the first layer AC wiring through the contact region 16, and the first layer Ae wiring is connected to the second and fourth layer Ae wiring through the through hole 15. has been done.

This layout makes it possible to form MO8+ to transistors 17 to 20 under the Ae wiring, and also makes it possible to form the transistors 17 to 20 under the Ae wiring, and also to reduce the size of the transistor length and width of the MOS transistors 1 to 20. Since there are no restrictions, the dimensions can be set to the optimum size.

Furthermore, power is supplied to the MOS) transistors 17 and 1.8 via the Ae wiring VCC through the Ag wiring 4 to 6, and the connection to the ground terminal of the MOS) transistors 19 and 20 is via the Aee wiring 7 to 9 and the Ae wiring V55. Further, the connection between the Mo5t transistors 17 and 19 is made on the first layer Aee wire 11.12 and the second layer Ae wiring, and the MOS transistors 18 and 2
Since the connection between 0 and 0 is made on the Aee wires 13 and 14 on the first layer and the Ae wiring on the second layer, the parasitic DC resistance is small, and the ability of the MOS transistor directly affects the performance of the integrated circuit chip. Therefore, a high performance jA product circuit can be realized.

Since the first wiring layer is arranged in the X direction and the second layer in the Y direction, it is easy to understand the wiring situation and the layout is simple.9 Next, Figure 2 shows the integrated circuit shown in Figure 1. FIG.

In FIG. 2, 2 is a 3-input NAND circuit, 3 is a 2-input NOR circuit, and their reference symbols are A, B, C, and D.

The connection lines labeled E, F, and G correspond to the Ae wiring with the same symbol shown in FIG. 1, respectively.

As mentioned above, this example shows the case of two wiring layers, but when laying out using three wiring layers, the wiring of the third layer should be in the same direction as the first layer, and within the block. When laying out four wiring layers, use the third layer as the wiring that passes through the block in the same direction as the first layer, and set the fourth layer in the same direction as the second layer. By using it as a wiring that passes through the block in the direction, it is possible to realize a layout of an integrated circuit chip that is integrated at a higher density without sacrificing the advantages of the present invention.

[Effects of the Invention] As explained below, the layerer 1 of the integrated circuit of the present invention
- method can realize a highly integrated and high-performance integrated circuit by arranging multilayer low-resistance metal wiring layers alternately in directions perpendicular and parallel to the channel direction. This has the effect that the complexity in is improved and the I/I period can be shortened.

[Brief explanation of drawings]

FIG. 1 is a plan view of an integrated circuit implemented as a layered circuit using an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the integrated circuit shown in FIG. 2... 3-input NAND circuit, 3... 2-input NOR circuit, 4-9. 11-14... Ag wiring, 15... Through hole, 16... Contact area, 17-20.
...MOS transistors, A, B, C, D, E, F. G, H/Ag wiring, V cc, V ss-A e wiring.

Claims (1)

[Claims] MO constituting a logic gate circuit with at least two inputs
The channel directions of the S transistors are the same, a first layer wiring layer of a low resistance metal is arranged in a direction perpendicular to the channel direction, and a first layer wiring layer of a low resistance metal is arranged above the first layer wiring layer in a direction parallel to the channel direction. A second wiring layer of low-resistance metal is placed on the
A layout method for an integrated circuit, characterized in that the first wiring layer and the second wiring layer are arranged alternately.