JPS6273351A - Buffer storage substituting system - Google Patents

Abstract

PURPOSE:To access a buffer storage at a high speed by using a block having a one-bit error in a set as the substitution object if the one-bit error is detected in this set of an address array. CONSTITUTION:Read signals of blocks 30, 31-33 of an address array 3 are compared with a high-order address stored in a register 2. If they do not coincide with each other, an error of read data is detected by a logic circuit 5 in parallel with this comparison, and '1' is sent to a register 102 for the presence of correctable errors but '0' is sent to the register 102 for the absence of the correctable errors. The block address indicating the block where correctable errors exist is stored in a register 101. If contents of the register 102 are '0', the output of a substitution block determining array 6 is selected by a selecting circuit 103 and is stored in a register 9; but if contents of the register 102 are '1', the output of the register 101 is selected by the circuit 103 and is stored in the register 9. Thus, the one-bit error is corrected by writing on the array 3 accompanied with the write to a main storage and the buffer storage if the one-bit error exists in the array 3, and the output of the array and the array of the register 2 are compared with each other at a high speed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a buffer storage replacement method.
The present invention relates to a buffer storage replacement method suitable for when a correctable error is detected in an address array of a buffer storage.

[Background of the invention]

As instruction processing devices become faster, buffer storage (cache) is used to reduce memory access time.
A method with the following is known.

A set associative method is generally used to control the mapping between main memory and buffer storage, and an address play is provided to maintain the mapping information. Additionally, in order to improve reliability, there is a system that adds ECC to the address array to enable single-bit error correction and multiple-bit error detection. Such a system is described, for example, in "General-Purpose Large Combeater" published by Nikkei McGraw-Hill on May 51, 1982, pages 381-699, "
This is shown in the M-380/382, a large computer with improved performance using a three-layer memory system and high-density technology.

A control method when the address array has ECC will be explained with reference to FIG.

When a memory access request occurs in the instruction processing device, the memory address of the data is transferred to the address array 6 via the address line 1 in order to determine whether the requested data exists in the buffer storage 22. Store it in register 2. Address array 6 is accessed using part of the address as a set address, and blocks 30, 31, 32, and 33 in the set are read. In this example, the association level is set to 4, so
There are four blocks of reading, but any number of associative levels may be used. Further, at the same time as reading the address array, ECC4o is read from the ECC array 4 corresponding to the set. After error detection and correction is performed in the logic circuit 5 based on the four read blocks and ECC, the comparator 3 compares the upper address stored in the register 2 with the address of each block.
4 to 37, and if it matches any block, the OR gate 18 generates an access permission signal for the buffer storage 22, and the encoder 19 encodes the comparison result and integrates it with the set address. Generate an access address for buffer storage 22. If it does not match any block, replace any block in the sector with the block in the middle memory containing the data χ requested by the command execution leader. Decide which block in the set to replace by reading the contents of the child Reiro for determining the replacement block.The algorithm is FIFO (First-In, First-In).
t-α+1) and LRU (Leasr Recent
ly Used ) method is common.

The data read from the replacement block determination array 6 is 4.
Show any one of the blocks.
The information (flock address) is encoded by the encoder 8 and stored in the register 9. When the replacement of the data on the main memory and the buffer storage is completed, the upper bits of the memory access address are registered in the block of the address array.

The processing method described above has the following problems: The read data of the address array is processed using ECC.

Since the comparison with the access address is performed after error detection and correction, it takes a long time to obtain the comparison result. moreover,
Even if there is a correctable one-bit error in the data registered in the address array, it is not corrected, which may lead to an uncorrectable multiple-bit error. Also, if you detect a correctable error and try to correct it,
A control logic for rewriting the address play is required, which complicates the control and increases the amount of material.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to increase the speed of access to buffer storage and the reliability of address play.

[Summary of the invention]

The feature of this invention is that the read data of the address array is compared before being corrected, and if there is a correctable error, the erroneous block is replaced and the main memory and buffer storage are replaced. and rewrite the corresponding block in the address array.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Blocks 60, 31, 32 read from address array 6
．． 33 is compared with the upper address stored in register 2 as it is without performing correction by ECCK. If the comparison results in a match with any block, the buffer storage is accessed using the same processing as in the conventional example.

If they do not match, a logic circuit 5 detects an error in the read data of the address array in parallel with the above comparison.
If there is a correctable error, "1" is sent, otherwise "0" is sent and stored in the register 102.Furthermore, the block address indicating the block in which the correctable error exists is stored in the register 7p101.Replacement The block address read from the block determination array 6 and the register 10
Which of the block addresses stored in 1 is to be the replacement target block is determined by the value of register 102. If register 102 is 0, the block address read from the replacement block determination array, register 1
If 02 is 01', the block address stored in register 101 is selected by selection circuit 103 and stored in register 9. The subsequent replacement of data in the main memory and buffer storage and registration in the address array remain the same as before.

FIG. 2 shows the inside of the data error detection circuit 5 in detail. In this example, it is assumed that 2 bytes of data are stored in each block of the address array. 6
00-605 are blocks 30-56 of the address array
The extracted data line 304 represents the read data line from the ECC array. A syndrome is generated in a circuit 505 from 305 to 504 and input to a syndrome decoder 307 via 506. At 607, the byte position where the correctable error exists is decoded from the syndrome, and if there is an error at byte 0, @1'' is sent to 310.

@0' is sent to 311-517. If there is an error in byte 1, 511 K @1', 510,512~
Sends @0 to 317. If there is an error in bytes 2 to 7, it similarly sends 0 or 1 to 510 to 317. 320 to 526 and 350 to 532 are OR gates. , @1 when there is a correctable error in 642
When there is no ', add' is sent and transferred to the register 102. Also, a block address with a correctable error is sent to 540-541 and transferred to the register 101.

In the present invention, since the read data from the address array is compared with the memory access address without correcting the error, there is a risk that the comparison result will be mistakenly determined to be a match. Each block of the address array has a parity, and the parity is compared with the parity of the upper bits of the access address, and only when both the address part and the parity part match, the comparison result is considered to be a match. This eliminates the possibility of a erroneous determination of a match due to a 1-bit error in the address array.

〔Effect of the invention〕

According to the present invention, it is possible to speed up the comparison between the read data from the address play and the upper bits of the memory access address, and when there is a 1-bit error in the address array.

It can be repaired by writing to the address array, which is associated with normal main memory and buffer storage replacement processing, and reliability can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention, FIG. 2 is a block diagram showing an error detection circuit, and FIG. 3 is a block diagram showing a conventional example. 2...Memory access address storage register, 6
...Address array, 4...ECC array, 5...Error detection circuit, 6...Replacement block determination array, 22...Buffer storage, ICI...Error block address storage register ,1
02...1-bit error detection signal storage register.

Claims (1)

[Claims] Main memory and a buffer that copies some data in main memory.
storage, and addresses that map buffer storage and main memory in a set-associative manner.
In a storage control device that has an array and an ECC that can correct 1-bit errors for the same set of data in the address array, if a 1-bit error is detected in a certain set of the address array, one bit error in that set is A buffer storage replacement method characterized in that blocks with bit errors are targeted for replacement.