JPH0353660A - Picture reader - Google Patents

Abstract

PURPOSE:To simplify the circuit scale by binarizing picture information from plural photoelectric conversion elements and detecting a duplicate read area of the plural photoelectric conversion elements based on the binarized picture information. CONSTITUTION:Duplicate area detection circuits 12, 13 are operated identically and adopt common circuit configuration. The duplicate area detection circuits 12, 13 use a binarizing element to binarize a multivalue digital signal inputted via a multiplex demultiplex circuits 14, 15 from A/D converters 11a-11c and a binarizing signal detects the duplicate read area of plural photoelectric conversion elements 9a-9c. Thus, the circuit scale is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reading device used in copying machines, facsimile machines, etc. [Prior art] A plurality of photoelectric conversion elements are used to partially overlap document image information with adjacent photoelectric conversion elements, and the image information is multi-valued using an analog/digital (A/D) converter. Image reading devices that perform A/D conversion into digital values are generally well known. Usually, the A/D converter has 6 to 8 b in order to faithfully reproduce image information from the photoelectric conversion element.
A device with a resolution of IT is used. In addition, in this image reading device, the photoelectric conversion element reads a specific detected document near the overlap reading area of each photoelectric conversion element, and the overlap reading area detection circuit uses the regularity of the read image information to perform each photoelectric conversion. The overlapping reading area of the element is detected and held, and based on the detection signal from this overlapping reading area detection circuit, the overlapping reading area correction circuit prevents the image information from each A/D converter for a normal document from being duplicated. There are known devices that can be combined (both image information in the overlapped reading area can be switched and continued in the middle of the overlapped reading area). The above-mentioned detected original is placed by the user in place of a normal original when the overlapping reading area detection circuit detects the overlapping reading area of each photoelectric conversion element, and is kept by the user at other times. Currently, the above-mentioned image reading devices have read image modes, such as a mode in which document image information is read using a reference white plate as a white level reference, and an automatic background removal mode in which document image information is read using the background part of the document as a white level reference. There are different output values when the same document image information is read in these modes. [Problems to be Solved by the Invention] In the above image reading device, the overlapping reading area correction circuit
Since the multivalued digital information from the converter is collected without duplication, the circuit scale becomes large. In addition, the overlapping reading area detection circuit detects the overlapping reading area of each photoelectric conversion element using the regularity of the read image information of each photoelectric conversion element with respect to the detected original, so the user can place the detected original at a position slightly lower than the normal position. However, if it is placed out of alignment, the regularity of the read image information will be disrupted, leading to false detection by the overlapped reading area detection circuit, and the user will have to place the detected document precisely in the correct position, which is a hassle. It is. Furthermore, the user must detect and store the original, and if the detected original is soiled, folded, or torn during storage, it will directly lead to false detection by the overlapped reading area detection circuit, which is a burden on the user. is very large. SUMMARY OF THE INVENTION An object of the present invention is to provide an image reading device that can improve the above-mentioned drawbacks, simplify the circuit scale, and reduce the burden on the user. [Means for Solving the Problem] In order to achieve the above object, the invention of claim 1 includes a plurality of photoelectric conversion elements that read document image information in adjacent ones in a partially overlapping manner; an overlapping reading area detection means for detecting overlapping reading areas of the plurality of photoelectric conversion elements based on image information from the plurality of photoelectric conversion elements; an overlapping reading area information providing means for giving information to the photoelectric conversion element to detect the overlapping reading area; and an overlapping reading area that combines image information from the plurality of photoelectric conversion elements so as not to overlap based on a detection signal of the overlapping reading area detection means. In the image reading device having a correction means, the overlapping reading area detection means has a binarization means for binarizing the image information from the plurality of photoelectric conversion elements, and the binarization means binarizes the image information from the plurality of photoelectric conversion elements. An overlapping reading area of the plurality of photoelectric conversion elements is detected from the image information obtained by reading the image. In the image reading apparatus according to claim 1, the invention further comprises a threshold value input means for arbitrarily inputting a threshold value. It consists of a predetermined pattern placed at a predetermined position that can be read inside. [Function] In the invention of claim 1, the overlapping reading area detection means binarizes the image information from the plurality of photoelectric conversion elements by the binarization means, and converts the plurality of photoelectric conversion elements based on the binarized image information. Detects overlapping reading areas of conversion elements. In the invention of claim 2, the binarization threshold of the binarization means is arbitrarily inputted by the threshold input means. In the third aspect of the present invention, the overlapping reading area detection means detects overlapping reading areas of the plurality of photoelectric conversion elements based on image information from the plurality of photoelectric conversion elements for the pattern. [Example] Figure 2 shows an outline of an example of the present invention. The inserted document is sub-scanned by being conveyed in the direction of the arrow shown in the figure by conveyance rollers l to 4, and is transferred to a transparent document table 5 and a guide plate 6.
When passing between the
D (charge-coupled element) is imaged on a photoelectric conversion element 9. The CCD 9 is disposed facing the main scanning direction perpendicular to the conveyance direction of the document, and photoelectrically converts the optical image formed by the optical lens 8 and outputs it in time series.

Since the number of effective reading pixels per CCD 9 is determined, once the original reading density is determined, the maximum readable original width that can be read is determined, but if the original is larger than the maximum reading original width, multiple CODs are used. In this embodiment, the number of effective reading pixels per CCD 9 is sooo
The maximum width of the document to be read is 917 pixels, the reading density is 16 pixels/III, and the maximum number of pixels to be read (for one line) is 14,672 pixels, as shown in Figure 3.
CD9 is composed of three CCDs 9a, 9b, and 9c. These CCDs 9a, 9b, and 9c are arranged in a line in the main scanning direction, and when the M document passes on the reading line perpendicular to the conveying direction, the reflected light image is reflected by the optical lenses 8a, 8b.
, 8c, images are formed so that x' and y' partially overlap, and this is photoelectrically converted. In Fig. 3, D is the maximum width of the document to be read, and the widths X' and Y' of the overlapping reading areas of CCDs 9a, 9b, and 9C are calculated from the above values (1500
The arrangement of each component is adjusted so that the number of pixels is within 0-14672)/2=164 pixels. Figure 1 shows the circuit configuration of this embodiment. CCD9a,9
The respective document image information from 9c and 9c is an extremely small analog signal, which is amplified by amplifiers 10a, 10b and 10c, and A/D converted by A/D converters 11a, 1lb and lie. Overlapping area amount detection circuit 12.13
In the overlapping area amount detection mode, a specific detection document 16 as shown in FIG. 4(a) is used and the A/D converters 11a, l
The image data obtained from lb and llc is sent to the synthesis separation circuit 1.
4.15, and the amount of image data overlap area is detected from this data. The overlap separation circuit 14.15 selects A based on the detection signal from the overlapping area amount detection circuit 12.13.
The image data from the /D converters 11a, llb, and llc are output together so as not to overlap (both image data in the overlapping reading area are switched and concatenated in the middle of the overlapping reading area).
If you try to perform processing to express halftones in the output image data of the synthesis/separation circuits 14 and 15, such as dither processing, the output image data usually requires at least 64 levels of gradation, so this implementation is necessary. In the example, the A/D converters 11a, llb, and llc have a resolution of 6 bits. Therefore, the combined command separation circuit 14.1
The output image data No. 5 is a 6-bit multivalued digital image signal, and is output to a processing circuit that performs subsequent MTF correction processing, dither processing, image editing processing, etc. Next, an outline of the operation of this embodiment will be explained. Each CCD9a, 9b
, 9c simultaneously scan in the same direction and output image data. As shown in Fig. 8, the scanning synchronization signal ◎(IN L
The main scanning direction of each COD 9a, 9b, 9c is synchronized by the input control signal (IN LGATII:), and the effective image data from each CCD 9a, 9b, 9c is
Controlled by ■. In the sub-scanning direction of the original, the transporting speed of the original is controlled so that the scanning synchronization signal ◎ is output 16 times per sub-scanning of one stamp. In the synthesis/separation circuit 14J5, each CCD 9a, 9b,
9c to amplifiers 10a, 10b, foe. The image data inputted through the A/D converters 11a, 1lb, and ie is corrected and output to the CCDs 9a, 9b, and 9b as shown in FIG.
The overlapping reading areas x', y'' of adjacent CCDs 9c can be connected at intermediate DX and DY. In this case, CCDs 9a and 9b
, 9c during the period of the scanning synchronization signal ◎.
When corrected (combined) into lines, the processing speed per pixel is 3 times faster than the image reading speed of CCDs 9a, 9b, and 9c.
It will double. During the scan synchronization signal ◎ interval of 312.5μs, CCD9a,
If 5,000 pixel signals for each of CCDs 9b and 9c are processed by the synthesis/separation circuit 14.15, the processing time per pixel will be 62.5ns, but the image data from CCDs 9a, 9b, and 9c will be processed into one line. Scan synchronization signal for correction◎
If the image data from the three CCDs 9a, 9b, and 9c are corrected to one line during the period, the processing time per pixel is reduced to 2.
The time becomes 1/3 of 0.8 ns. In this embodiment, as shown in FIG. 3, the maximum width D of the document to be read is divided into left and right parts at the center (1/2) 17, and the data of 7500 pixels on each of the right and left sides are scanned and synchronized.
The processing time is 41.6ns.
becomes. Currently, considering the processing time for elements such as ICs,
1.6 ns is the limit.

The clock (CLKI) shown in FIG. 8 indicates a processing time of 62.
It is a 16MHZ clock corresponding to 5ns. The scanning synchronization signal ◎, the input control signal ◎, and the image data from the CCDs 9a, 9b, and 9c are synchronized with the clock ■. In this embodiment, the time required to read image information is 62.5 ns.
, the processing time is converted by assuming that the output processing time for concatenating and outputting image data into one line is 41.6 ns.
The clock (CLK2) shown in FIG. 8 indicates a processing time of 41,
24M}12 clocks, which corresponds to 6ns. Further, the output control signal (OUT LGATE) (2), the scanning synchronization signal ((7) OUT LSYNC in FIG. 10), and the output data of the combination/separation circuits 14 and 15 are synchronized with the clock (2).

5 and 6 show the structure of the synthesis/separation circuit 15. The overlap/separation circuit 15 corrects the overlapping reading area
It can be switched and connected using 11DX, which is half the number of digits, and has almost the same structure as the combination/separation circuit 14. In FIGS. 5 and 6, 21 is an overlapping area amount detection circuit 1.
An element that outputs 1/2 of the data from 3 (hereinafter referred to as a 1/2 frequency divider). 22.23 is the inverter, 24, 27
．． 28 is an addition circuit that calculates the sum, 25, 26, 29, 32,
35, 36, 41, 42, 59, 60, 61 are data selectors, 30, 31, 37.38 are address counters,
33, 34, 39.40 are comparators, 43, 44,
45, 46, 50 are flip-flops, 47 is a delay element, 4g, 49 are AND gates, 51, 52, 53.54
is Takuri D flip-flop, 55,56.57.58
is toggle RAM (statisk RAM). The operation of this combination/separation circuit 15 will be explained with reference to the timing charts of FIGS. 8 and 9. Multi-input D flip-flops 51 and 52 are CCD9
c to amplifier 10c. The image data Dc input through the A/D converter lie is latched by the latch signal k (■) and selectively output to the toggle RAMs 55 and 56 by the selection signals a and b ([F], ◎), respectively. , multi-input D flip-flops 53 and 54 connect the CCD 9b to the amplifier 10.
b. The image data Db input through the A/D converter 1lb is latched by the latch signal k and toggled by the selection signals a and b ([F], @) in RAMs 57 and 58, respectively.
Selectively output to. In this case, the multi-input D flip-flops 5l, 52, 53, and 54 latch the image data when the selection signals a and b become low level. As shown in FIG. 8, the image data Da and Db from the A/D converters 11c and llb are synchronized with the clock ■ and become valid when the input control signal ◎ is at a high level. The latch signal k is the clock ■, and the flip-flop 43 latches the scanning synchronization signal ◎ based on the clock ■. The flip-flop 44 transfers the inverted output signal to the flip-flop 4.
The non-inverted output signal [F] and the inverted output signal @ as shown in FIG. 8 of this flip-flop 44 are latched by the output signal of 3.
53 and 54 as selection signals. Therefore, the durable D flip-flop 51.53 and the multi-input D flip-flop 52.54 alternately latch the image data in synchronization with the scanning synchronization signal ◎, and the durable D flip-flop 51.53 latches the image data Dc , Db at the same time, and the durable D flip-flops 52 and 54 simultaneously latch the image data Dc and Db. Data writing/reading of the toggle RAMs 55 to 58 is controlled by the input signals of the 111E and CS terminals, and the toggle RAMs 55 and 57 are connected to the AND gate 4 by inputting the inverted output signal @(b) of the flip-flop 44 to the WE terminal.
9's output signal (d) is input to the Go terminal. Toggle R
In AM56.58, the non-inverted output signal [F] (a) of the flip-flop 44 is input to the W terminal and the AND gate 48
The output signal (C) is inputted to the 8th terminal, and the clock ■ is delayed by the delay element 47, resulting in a signal ■ as shown in FIG. The AND gate 48 ANDs the signal ■ from the delay element 47 and the non-inverted output signal [F] of the flip-flop 44, and the AND gate 49 takes the AND between the signal ■ from the delay element 47 and the inverted output signal @ of the flip-flop 44. Take an and. Therefore, toggle RAM55. 57 and the toggle RAMs 56 and 58 alternately perform write operations and read operations. For example, if the toggle RAMs 55 and 57 are in the read operation, the toggle RAM 56. 58 performs a write operation. Then, only when the toggle RAMs 55 and 57 are in writing operation, the multi-input D flip-flop 5
Toggle RAM55 from 1,53. Image data D to 57
C, Db are output and toggle RAM55. 57 is in the process of reading, the output sides of the durable D flip-flops 51, 53 become high impedance and toggle the RAM 55.57.
Data is read from 57. Similarly toggle RAM
56. Toggle RAM 56 . 58
The image data Dc and Db are output to the toggle RAM 56.
．． When RAM 58 is being read, the output sides of multi-input D flip-flops 52 and 54 become high impedance and toggle RAM 56.58. Data is read from 58. The addresses of the toggle RAMs 55 to 58 are specified by the output signals of the address counters 30, 31, and 37.38, respectively, and the clocks to each address counter 30, 31, and 37.38 are the clocks CLK1 and CLK1 output from the data selectors 41.42, respectively. CLK2, and as mentioned above, clock C
LK 1 is a clock that can process 5000 pixels during the period of the scan synchronization signal ◎, and clock CIJ 2 is a clock that can process 7500 pixels during the period of the scan synchronization signal ◎.

The data selectors 41 and 42 select and output signals at the input terminals according to the level of the non-inverted output signal [F](a) of the flip-flop 44.

When the toggle RAM 57 is in the process of writing, the clock to the address counter 37 is the signal ■ from the data selector 41, and this signal ■ is the clock CLKI (■). At this time, the initial count value of the address counter 37 becomes O. This is because the fixed value 3 is O, the selection signal of the data selector 35 is the non-inverted output signal [F] (a) of the flip-flop 44, and the fixed value 3 is input to the address counter 37 when writing to the toggle RAM 57. It is from. Further, the count start/end signal of the address counter 37 is the signal ◎(e) from the data selector 41, and this signal ◎ is the signal ◎ obtained by latching the input control signal INLGATE by the flip-flop 45 with the clock ■. Therefore, the toggle RAM 57 writes all of the 5000 pixel image data Db from the large power D flip-flop 53 according to the count value of the address counter 37.

While writing to the toggle RAM 57, the toggle RAM 55 also performs a writing operation. The clock to the address counter 30 is the signal (g) from the data selector 41, similar to the clock to the address counter 37, and the initial count value is O. The fixed value 1 is O, the selection signal of the data selector 25 is the non-inverted output signal [F] (a) of the flip-flop 44, and the fixed value 1 is input to the address counter 30 when writing to the toggle RAM 55. It is from. Also, the count start/end signal of the address counter 30 is the signal [F] from the data selector 4l.
(f), and this signal ■ is the output signal ◎ of the flip-flop 45. Therefore, the toggle RAM 55 writes all of the 5000-pixel image data Dc from the durable D flip-flop 51 according to the count value of the address counter 30.

While the toggle RAM 57 is being written, the toggle RAM 58 is reading the image data written one line before, and the clock to the address counter 38 is the signal ■ (j) from the data selector 42, and this signal ■ is the same as the above clock. ■It is. At this time, the address counter 38 has an initial count value of 2500. This is fixed value 9 is 250
This is because the data selector 32 inputs the fixed value 9 to the address counter 38 by the selection signal z2.

The selection signal z2 is a signal at a constant level, and is applied via a jumper wire or a date switch. Further, the count start/end signal of the address counter 38 is the signal (2) (h) from the data selector 42, and this signal (2) is the signal (2) obtained by latching the output control signal OUT LGATE by the flip-flop 46 with the clock (2). Therefore, the toggle RAM 58 is the address counter 3.
Image data is read out according to the count value of 8.
Continue even if the valid data area is exceeded from the 0th pixel. The comparator 40 compares the count value of the address counter 38 and the output signal of the data selector 27, and outputs a match signal ■ when the address counter 38 reaches (4999-X/2). Here, the data detected by the overlapping area amount detection circuit 13 (overlapping area amount data 2, which is added to the fixed value 6 by the adder circuit 27 and input to the comparator 40. This fixed value 6 is 4999, and the output signal of the adder circuit 27 is (49
99-X/2). The match signal ■ from the comparator 40 is input to the data selector 41, and the signal ◎ is output from the data selector 41. This signal ■ clears the flip-flop 50, and the output signal ■ of the flip-flop 50 changes from a low level to a high level. Switch. Therefore, the count start/end signal to the address counter 38 switches from high level to low level, and the toggle R
AM58 reads image data from the 2500th pixel to the (4999-X/2)th pixel. When the toggle RAM 55 is performing a write operation, the toggle RAM 56 is reading the image data written one line before, and the clock to the address counter 31 is the signal ■ (j) from the data selector 42, and this signal ■ is the clock ■ above. At this time, the initial count value of the address counter 31 becomes X/2. This is because X/2 from the 172 frequency divider 21 and the fixed value 1 are input to the data selector 26, and the data selector 26 receives the selection signal ◎(b) from the flip-flop 44 to
This is because X/2 from the frequency divider 21 is input to the address counter 31. Further, the count start/end signal of the address counter 31 is the signal (i) from the data selector 41, and this signal ■ is the output signal ■ of the flip-flop 50. Therefore, the toggle RAM 56 reads image data from X/2 according to the count value of the address counter 31. - The comparator 34 compares the count value of the address counter 31 and the output signal of the data selector 29, and the address counter 31 compares (483
50X/2), outputs a match signal ■. Here, the data X detected by the overlapping area amount detection circuit 13 is added to the fixed value 5 in the adding circuit 24 and inputted to the data selector 29, and the data selector 29 selects the output signal of the adding circuit 24 by the selection signal z1. Select and output to comparator 34. The fixed value 5 is 4835, and the output signal of the adder circuit 24 is 4835 + X /2.
The selection signal z1 is a signal at a constant level, and is applied via a jumper wire or a dip switch. The match signal ■ from the comparator 34 is sent to the data selector 42
The signal ■ is input from the data selector 42, and the flip-flop 50 is set by this signal ■, and the output signal ■ of the flip-flop 50 is switched from a high level to a low level. Therefore, the count start/end signal to the address counter 31 switches from high level to low level, and the toggle RAM 56 reads out image data from the X/2 pixel to the (4835+X/2) pixel.

The data selector 59 selects the image data read out alternately from the toggle RAMs 55 and 56 using the non-inverted output signal [F](a) of the flip-flop 44, and the data selector 60 selects the image data read out alternately from the toggle RAMs 55 and 56 using the non-inverted output signal [F](a) of the flip-flop 44. a
) selects the image data read out alternately from the toggle RAMs 57 and 5g. Therefore, the image data output from the data selector 59 becomes the UP data Dc shown in FIG. 9, and the image data output from the data selector 60 becomes the UP data Db shown in FIG. The data selector 61 is the output signal of the flip-flop 50 (m)
selects and outputs the image data Dc from the data selector 59 and the image data Db from the data selector 59, and the image data from the data selector 6l becomes output data l (UP) shown in FIG. This is the center l of the maximum width D of the document to be read as shown in Figure 3.
This means that the copying data read by the CCDs 9c and 9b on the right side of 7 can be concatenated by switching at the position DX, which is half of the overlapping reading area. Next, the operation of the combining/separating circuit 14 will be explained.

The combination/separation circuit 14 has almost the same configuration as the combination/separation circuit 15, and the selection signals Zl, Z2 are connected to the combination/separation circuit 15.
It's on the opposite level. Therefore, in order to simplify the explanation, the operation of the combination/separation circuit 14 will be explained with reference to FIGS. 5 and 6, in a manner different from that of the combination/separation circuit 15.

Durability D flip-flops 51, 52 connect the CCD 9b to the amplifier 10b. The image data ob input through the A/D converter 1lb is latched by the latch signal k (■) and selectively output to the toggle RAM 55.56 by the selection signals a, b ([F], ■), respectively. , multi-input D flip-flops 53, 54 connect CCD 9a to amplifier 1
0a. The image data Da input through the A/D converter 11a is latched by the latch signal k and selectively output to the toggle RAMs 57 and 58 by the selection signals [F] and ◎, respectively. The write operation of the toggle RAMs 55 to 58 is the same as that of the combination/separation circuit 15, and the toggle R
The read operation of AM55 to AM58 will be explained. During the write operation of toggle RAM55 and 57, the toggle RAM
56 and 58 perform a read operation. While the toggle RAM 57 is being written, the toggle RAM 58 is reading the image data that was written one line before, and the clock to the address counter 38 is the signal ■ (j) from the data selector 42, and this signal ■ is the same as the above clock. ■It is. Further, the data detected by the overlapping area amount detection circuit 12 (overlapping area amount data Y) is transferred to the inverter 2.
3, and is added to the fixed value 7 in the adder circuit 28.

This fixed value 7 is 164, and the output signal of the adder circuit 28 is (164-Y).

The data selector 32 selects the adder circuit 28 using the selection signal z2.
The data selector 36 selects the output signal of the data selector 32 based on the inverted output signal ◎ (b) of the flip-flop 44 and outputs it to the address counter 38 . Therefore, the initial count value of address counter 38 is (164-Y)
becomes. The count start/end signal to the address counter 38 is the signal (h) from the data selector 42,
This signal (2) is the output signal (2) of the flip-flop 46. Therefore, the toggle RAM 58 reads the image data Da from the (164-Y)th pixel even beyond the effective data area. Data Y from the overlap area amount detection circuit 12 is 1
The 72 frequency divider 21 divides the signal into 1/2, the inverter 22 inverts the signal, and the adder circuit 27 adds the fixed value 6. This fixed value 6 is 4999, and the output signal of the adder circuit 27 is (4
999-Y/2). The comparator 40 compares the output signal of the adder circuit 27 and the count value of the address counter 38, and the address counter 38
−Y/2), outputs a match signal ■. This match signal ■ is input to the data selector 41, a signal ⊚ is output from the data selector 4l, and the flip-flop 50 is cleared.

When the toggle RAM 55 is performing a write operation, the toggle RAM 56 is reading the image data written one line before, and the clock to the address counter 3l is the signal ■(j) from the data selector 42, and this signal ■ is the above clock ■.

At this time, the address counter 31 has an initial count value of Y.
/2. This is because the data selector 26 uses the selection signal ◎(b) from the flip-flop 44 to select the 172 frequency divider 2.
This is because Y/2 from 1 is input to the address counter 31. Further, the count start/end signal to the address counter 31 is the signal ■(i) from the data selector 41, and this signal ■ is the output signal ■of the flip-flop 50.
It is. Therefore, the toggle RAM 56 reads image data from Y/2 according to the count value of the address counter 31.

The comparator 34 compares the count value of the address counter 31 and the output signal of the data selector 29, and outputs a match signal ■ when the address counter 31 reaches 2499. This is because the data selector 29 selects the fixed value 8 based on the selection signal Z1 and outputs it to the comparator 34, and this fixed value 8 becomes 2499. The match signal ■ from the converter 34 is input to the data selector 42, and the signal ■ is output from the data selector 42. This signal ◎ sets the flip-flop 50, and the output signal ■ of the flip-flop 50 changes from high level to low level. Switch. Therefore, the count start/end signal to the address counter 31 switches from high level to low level, and the toggle RAM 56 stops reading the image data by Y/2.
This is performed from the pixel to the 2499th pixel.

The data selector 59 selects the image data alternately read out from the toggle RAM 55.56 using the non-inverted output signal [F](a) of the flip-flop 44, and the data selector 60 selects the image data read out alternately from the toggle RAM 55.56 using the non-inverted output signal [F](a) of the flip-flop 44. ]
Image data read out alternately from the toggle RAMs 57 and 58 in (a) is selected. Therefore, the image data output from the data selector 59 is dn shown in FIG.
The image data output from the data selector 60 becomes data Db, and the image data output from the data selector 60 becomes dn data Da shown in FIG. The data selector 61 receives the output signal of the flip-flop 50 (
m) selects and outputs the image data Db from the data selector 59 and the image data Da from the data selector 59, and the image data from the data selector 6l becomes output data 2 (down) shown in FIG. . This means that, as shown in Figure 3, the image data read by the CCDs 9b and 9a from the left side of the center l7 in the maximum width D of the original to be read can be switched and spliced at a position DY that is half of the overlapping reading area. FIG. 4(a) shows the overlapping area amount detection circuit 12, . 1 3
FIG. 4(b) shows a detection original 16 for obtaining an image signal as a basis for detection processing, and FIG. 4(b) shows how the detection original 16 is read in the overlapping area amount detection mode.

The detected original 16 has a white background, and a black line 1 is parallel to the original insertion direction in this embodiment and perpendicular to the scanning direction of the CCDs 9a to 9C.
It has 61 to 164. Black lines 161 to 164 are black line 16
The image signal switching positions DX and DY from the CCD 9a=CCD 9c are entered between D3 between 1 and 162, and D4 between the black lines 163 and 164, respectively, and the distance D1 between the rear ends of the black lines 161 and 162 in the main scanning direction is Di. >X', black ml63,
164 so that the distance D2 between the rear ends in the main scanning direction satisfies 02>Y'. The detected original 16 having such regularity is inserted in place of a normal original in the overlapping area amount detection mode, and is transported by the transport rollers 1 to 4 to the CC.
Read by D9a-9c. The image signals from the CCDs 9a to 9C are input to a combination/separation circuit 14.15 via an amplifier 10a"lOc and an A/D converter 1la to llc, and the output data 1 (up) of the combination/separation circuit 14 is the amount of overlapping area. The output data 2 (down) of the combination/separation circuit 15 is input to the detection circuit 12 and is input to the overlap area amount detection circuit 13.The output data of the overlap area amount detection circuit 12 is input to the combination/separation circuit 14, and the The output data of the area amount detection circuit 13 is input to the combination/separation circuit 15.The overlapping area amount detection circuits 12 and 13 have the same operation and have a common circuit configuration. is switched from the reading mode by an instruction from the numeric keypad on the operation panel, the illumination device 7 lights up, and the control signal FGA is switched on.
After TE rises and the amount of overlapping area is detected, the control signal FGATE falls and the illumination device 7 is turned off to switch to the reading mode and return to the standby state.

FIG. 7 shows a specific configuration of the overlapping area amount detection circuit 12. In the figure, 100 is a binarization element, 101 to 104 are flip-flops, 105 and 106 are counters, 107 is a comparator, 108 is a data selector, 109 is an AND element, 110 and 111 are OR elements, and 112 is an inverter.

The operation of this overlapping area amount detection circuit 12 will be explained with reference to the timing chart of FIG.

In the overlapping area amount detection mode, output data 1 (up) of the synthesis/separation circuit l4 is input to the binarization element 100 and threshold value 1 is inputted to the binarization element 100.
It is binarized with . This threshold value 1 is set using a dip switch or the like, and can be arbitrarily varied. The threshold value is varied by a dip switch or the like to prevent illegal binarization of the binarization element 100 due to variations in sensitivity density or differences in reading modes between image reading devices. In the overlapping area amount detection mode, the detected document 16 is detected by CCDs 9a to 9.
A control signal FGATE indicating the effective number of sub-scanning lines as shown in FIG. 10 is input to the AND element 109.

The output signal AI of the binarization element 100 is as shown in FIG. 10, where white is O and black is 1. flip flop 1
01 latches the inverted output signal at the rising edge of the output signal 0 of the binarization element 100 and outputs a non-inverted output signal ◎ as shown in FIG. is entered as . Further, the initial count value of the counter 105 is O, and the aforementioned clock CLK 2 is inputted as the count clock. Therefore, the output signal ◎ of the counter 105 becomes as shown in FIG. 10, and is compared with the set value 1 by the comparator 107. This setting value 1 corresponds to the center reference 17 of the detected document 16 in FIG. 4(a).
From the black drawn on the right side [161 and 162, the width DI from the point where white changes to black for the first time to the point where it changes from white to black when viewed from the reading direction is calculated from the reading density etc. of this embodiment. is set to the number of pixels. If 01=96
(pixel), the coincidence signal 0 from the comparator 107 becomes as shown in FIG. 1O, and becomes one input signal of the OR element 110. The other input signal of the OR element 110 is the output signal 0 of the OR element 111, and the flip-flop 102 latches the output signal O of the flip-flop 101 using the clock CLK2, and the output signal 0 of the flip-flop 101 and the output signal 0 of the flip-flop 102 are latched. The output signal of is input to the OR element 111. As shown in FIG. 10, when the output signal Φ of the OR element 110 becomes a low level, it is when the output signal of the counter 105 and the set value l match, and the output data l(up) of the synthesis/separation circuit l4 This indicates that appropriate overlap correction has been performed.

Next, the flip-flop 103 is cleared by the output signal -4 of the OR element 110, and the output signal of the flip-flop 103 and the control signal FGATE are ANDed by the AND element 10.
9 and the output signal 0 of the AND element 109 is the first
The result will be as shown in Figure 0. Counter 106 is AND element 1
The output signal 0 of 09 is input as a count start/end signal, and the scan synchronization signal OUT LSYNC is input as a count clock. This counter 106 has an initial count value of O and outputs an output signal @ as shown in FIG. The output signal of the flip-flop 103 is inverted by the inverter 112 to become a signal O as shown in FIG. 10, and the flip-flop 104 receives the signal O as a clock and latches the output value of the counter 106. The data selector 108 receives the output signal ◎ of the AND element 109 as a selection signal, and selectively outputs the output value of the counter 106 and the output value of the flip-flop 104. The output signal {circle around (2)} of the data selector 108 becomes as shown in FIG. 10, and in the overlapping area amount detection mode, it is directly outputted to the synthesis/separation circuit 14 as detection data.

That is, reading of the detected original 16 is started and the control signal FGA is
When TE rises, the scanning synchronization signal OUT LSYNC
The value counted up from 1 every time is added to the separation circuit 14.
When the value is counted up to a proper value, the value (X) is held.

The overlapping area amount detection circuit 13 is the same as the overlapping area amount detection circuit l2.
The configuration is almost the same as that of the overlapping area amount detection circuit 12, and the setting value 1 input to the comparator 107 is different from that of the overlapping area amount detection circuit 12. This setting value 1 is determined by the black lines 163 and 164 drawn to the left of the center reference 17 of the detected document l6 in FIG. The width D2 from the point where the color changes to black is set to the number of pixels calculated from the reading density of this embodiment.

In the overlapping area amount detection mode, the overlapping area amount detection circuit 12.1
The detection data from the data selector 108 in step 3 is sent as is to the combination separation circuit 14.15, and from the combination separation circuit 14.15, the image data of the detected document 16 read by the CCDs 9c, 9b, and 9a is divided into half of the overlapped reading area. Position D
The data that is connected by switching with X and DY is output, but the detected data from the data selector 108 in the overlapping area amount detection circuit 12 and 13 at this time is held in the hold circuit, and in the read mode, the data from the hold circuit is The detected data is input to the combination/separation circuits 14 and 15 and the CCD 9
The image data of the normal document read in c, 9b, and 9a is switched and spliced at half positions DX and DY of the overlapping reading area and is output.

In this embodiment, the overlapping area amount detection circuits 12 and 13 are A/D
From the converter 11c*1lb+11a to the synthesis/separation circuit 14.
Since the multivalued digital signal inputted through the circuit 15 is binarized by the binarization element 100 and the amount of overlapping area is detected from the binarized signal, the circuit scale can be reduced and simplified. Currently, there are widely used reading modes, such as a normal mode in which a document is read using a reference white board as a white level, and an automatic background removal mode in which a document is read with the background part of the document as a white level. In the removal mode, the output value when reading the same original is different. Therefore, the optimal threshold value 1 of the binarization element 100
differs depending on the reading mode, and if the threshold value 1 is set to a fixed value, noise is likely to be picked up and the overlapping area amount detection circuit 12
．． 13 erroneous detection occurs, and unauthorized read image information is generated, making it impossible to reliably obtain proper read image data. In this embodiment, the threshold value 1 of the binarization element 100 can be arbitrarily varied using a dip switch or the like, so the optimal threshold value 1 can be set regardless of the reading mode (normal mode, automatic background removal mode). Erroneous detection by the overlapping area amount detection circuits 12 and 13 due to the generation of read image information can be prevented. FIG. 11 schematically shows another embodiment of the present invention. In this embodiment, a CCD is used instead of the guide plate 6 in the above embodiment.
A guide plate 150 is used which is marked with a mark for detecting the amount of overlapped reading areas 9a to 9c.
is not used. As shown in FIG. 12, mounting members 151 are fixed to the guide plate 150 on the left and right sides, and pins for positioning the guide plate 150 are inserted into holes in the mounting members 151. This pin keeps the guide plate 150 parallel to the original platen 5.
The positioning is done so that the gap between the FIG. 13(a) shows the guide plate 150, and FIG. 13(b) shows how marks on the guide plate 150 are read in the overlapping area amount detection mode.

The guide plate 15G has a white background and has marks 151 to 154 made of black lines parallel to the original insertion direction and perpendicular to the scanning direction of the CCDs 9a to 9c in this embodiment.

The black lines 151 to 154 are provided with accurate dimensions by printing and thin grooves. Black lines 151 to 154 are black lines 151,
D3 between 152 and D4 between black lines 153 and 154 contain switching positions DX and DY of image signals from CCDs 9a to 9c, respectively, and the distance D1 between the rear ends of black lines 151 and 152 in the main scanning direction is DI>X ', black line 153, 15
The distance D2 between the rear ends of the four main scanning directions is set such that D2>Y'.

The black 4@151-154 having such regularity is read by the CCDs 9a to 9c in the overlapping area amount detection mode, and the overlapping area amount is detected by the overlapping area amount detection circuits 12 and 13 as in the above embodiment. ．． This overlapping area amount detection mode is switched from the reading mode by an instruction from the numeric keypad on the operation panel, for example, the illumination device 7 lights up and the control signal FGATE rises, and after the overlapping area amount is detected, the control signal FGATE is switched. The lighting device 7 turns off, switches to reading mode, and returns to standby mode. In this embodiment, since the marks 151 to 154 are provided on the guide plate 150, the detected original 16 is not required, and the user does not need to insert or store the detected original 16, which greatly reduces the burden on the user. Furthermore, false detection of the amount of overlapping area due to misalignment, dirt, folds, cuts, etc. of the detected document 16 is eliminated, and the user can detect the amount of overlapping area anytime and anywhere in real time. 14 and 15 show a part of another embodiment of the present invention. In this embodiment, a roller 155 is provided in place of the guide plate 150 in the above embodiment, and this roller 155 is white and is driven to rotate at the same linear speed as the conveyance rollers 1 to 4.
or it may be stopped). The roller 155 has a shaft 156 at its center, and the shafts 156 at both ends are supported on the document table 5 by bearings 157, and are driven by a drive section. Further, the roller 155 has marks 151 to 154 made of black lines like the guide plate 150 described above.

〔Effect of the invention〕

As described above, according to the invention of claim 1, there is provided a plurality of photoelectric conversion elements that partially overlap read document image information adjacent to each other, and based on the image information from the plurality of photoelectric conversion elements. Overlapping reading area detection means for detecting overlapping reading areas of the plurality of photoelectric conversion elements of the lever, and information to the photoelectric conversion elements to cause the overlapping reading area detection means to detect the overlapping reading areas of the plurality of photoelectric conversion elements. An image reading device comprising an overlapping reading area information adding means for giving an overlapping reading area information, and an overlapping reading area correction means for combining image information from the plurality of photoelectric conversion elements so as not to overlap based on a detection signal of the overlapping reading area detecting means, The overlapping reading area detection means has a binarization means for binarizing the image information from the plurality of photoelectric conversion elements, and the image information binarized by the binarization means is used to detect the plurality of photoelectric conversion elements. Since it detects overlapping reading areas of elements, it is possible to simplify the circuit scale.
According to the second aspect of the invention, the image reading apparatus according to the first aspect includes threshold input means for arbitrarily inputting the binarization threshold of the binarization means, so that the circuit scale can be simplified. Moreover, it is possible to set an optimal threshold value regardless of the reading mode, and it is possible to prevent false detection by the overlapping area detection means. Furthermore, according to the invention of claim 3, in the image reading device of claim 1, the overlapping reading area information providing means is provided at a predetermined readable position within the image reading area of the photoelectric conversion element. Since the system is structured using patterns, the user does not need to insert or store detected manuscripts, reducing the burden on the user.
In addition, false detection of the amount of overlapping area due to misalignment, dirt, folds, cuts, etc. of the detected document is eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of one embodiment of the present invention, FIGS. 2 and 3 are a schematic front view and a schematic side view showing the same embodiment, and FIGS. 4(a) and (b) 5 and 6 are block diagrams showing the combination/separation circuit of the same embodiment, and FIG. FIGS. 8 and 9 are a block diagram showing an example of the overlapping area amount detection circuit, FIGS. 8 and 9 are timing charts showing the operation of the above-mentioned combination or separation circuit, and FIG. 1
Figure 1 is a schematic diagram showing another embodiment of the present invention, Figure 12 is a perspective view showing a part of the guide plate of the same embodiment, and Figure 13 (a).
(b) is a plan view showing the guide plate and a schematic diagram showing how marks are read on the guide plate, FIG. 14 is a schematic diagram showing another embodiment of the present invention, and FIG. 15 is an example of the same embodiment. FIG. 9a, 9b, 9c”・CCD, ll
a, llb, 11c...A/B converter, 14.1
5...Synthesis/separation circuit, 12.13...Overlapping area amount detection circuit, 151-154...Mark. Form 1 phantom i2 Houki Z mouth O δen j L flea 75 inside 111~r1-11 Sousha way j Ashikane 75 mouth form 4 mouth (a) Form 7 day form 74 day form lZ mouth η death ii Cwore] (Ku)

Claims (1)

[Scope of Claims] 1. A plurality of photoelectric conversion elements that partially overlap and read document image information on adjacent ones; overlapping reading area detection means for detecting overlapping reading areas of the photoelectric conversion elements; and overlapping reading for providing information to the photoelectric conversion elements to cause the overlapping reading area detection means to detect overlapping reading areas of the plurality of photoelectric conversion elements. In an image reading device, the image reading device has an area information adding unit and an overlap reading area correction unit that collects image information from the plurality of photoelectric conversion elements so as not to overlap based on a detection signal of the overlap reading area detection unit. The detection means has a binarization means for binarizing image information from the plurality of photoelectric conversion elements, and double reading of the plurality of photoelectric conversion elements is performed from the image information binarized by the binarization means. An image reading device characterized by detecting an area. 2. The image reading apparatus according to claim 1, further comprising threshold input means for arbitrarily inputting a binarization threshold value of said binarization means. 3. The image reading device according to claim 1, wherein the overlapping reading area information providing means is constituted by a predetermined pattern provided at a predetermined readable position within the image reading area of the photoelectric conversion element. image reading device.