JPS6267879A - Field effect transistor - Google Patents

Abstract

PURPOSE:To enable the accurate pattern transfer to a resist by bringing source and drain electrodes in contact with a semiconductor wafer at the bottom of the electrodes and on the side planes on the gate side so as to level the surface of the semiconductor wafer and that of the source and drain electrodes on nearly the same plane. CONSTITUTION:On a semi-insulating GaAs substrate 1, an N-type buffer layer 2 and an N-type active layer 3 are epitaxially grown continuously and a resist 8 is selectively formed in a channel region. The active layer 3 is etched by dry etching using the resist 8 as a mask. AuGe-Ni-Au as an ohmic metal is vapor-deposited to obtain a source electrode 4 and a drain electrode 5. The resist 8 is removed together with the ohmic metal and a resist 9 is spread. The resist 9 in the position where a gate electrode is to be arranged is window- opened and is subjected to chemical etching for obtaining a recess 6. Furthermore, aluminum as a Schottky metal is vapor-deposited to obtain a gate electrode 7. Lastly, the Schottky metal on the resist is removed together with the resist 9 to complete the device.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Field of Industrial Application The present invention relates to a field effect transistor (hereinafter referred to as FET) for ultra-high frequencies using a Schottky barrier.

2. Description of the Related Art Schottky barrier qFETs using GaAs have a high electron density and are used as ultra-high frequency devices. Conventionally, as described in Japanese Patent Application Laid-open No. FF158-54980, FETs have been developed to reduce the resistance between the gate and the source in order to improve the microwave characteristics of FETs, especially the noise IfjI.
Various proposals have been made for improving ET.

FIGS. 4A to 4E schematically show the conventional FET O) manufacturing process. On the semi-insulating GaAs substrate LAD, an n-type buffer layer is formed by successively epitaxially growing a main nfMvJ layer (FIG. 4A), and selectively depositing an ohmic metal on the young layer (43). Source electrode n4) and drain electrode ta1 are obtained (Fig. 4B).Next, resist 1 is applied to the entire surface and an opening is made at the part where the gate electrode is to be applied (Fig. 4C).Recessed portion After etching to obtain +47), Schottky gold x(n (for example, At for GaAs) is evaporated (FIG. 4D) to form the gate electrode (48a). (4
8 is removed together with the resist material to complete the FET (
Figure 4E).

In the step shown in FIG. 4C, the pattern is transferred to the resist mold by closely covering the resist with a photomask. If there is a gap between the photomask and the resist, the intensity of the light will be weakened to less than half due to light diffraction, and the exposure will be incomplete in the thick part. Furthermore, the desired line width cannot be obtained. When performing electron beam exposure, the energy intensity of the beam is constant, so uniformity in film thickness is required.

However, if the resist is applied to the uneven surface where the source electrode and drain electrode are located,
Not only will the resist surface not be flat, but the film thickness will also be non-uniform. If the resist surface is not flat, there will always be a gap between the resist and the photomask. In other words, accurate pattern transfer cannot be performed.

Problems to be Solved by the Nori Invention The invention was made in view of the above-mentioned points.
ET.

2) Means of rounding to resolve the interset point t--The present invention provides a method for forming a source electrode on a semiconductor wafer including an active layer;
FET with gate'@pole and drain electrode arranged
In this case, the source electrode and the drain electrode are in contact with the calyx body wafer at the bottom surface of the four electrodes and the side surface on the gate side, and the surface of the calyx body wafer and the upper surface of the source electrode and the drain electrode are approximately These are FETs located on the same plane.

e) Operation Since the surface of the semiconductor wafer and the upper surfaces of the source and drain electrodes are almost on the same plane, the resist applied to form gates and electrodes by lift-off technology has a uniform thickness without any unevenness, and the mask pattern Transfer to the resist is performed accurately.

f) Implementation example Figure fJ1 is a schematic composition diagram of an example of the present invention.

(1) is a semi-insulating GaAs substrate, 121 μn-type expansion layer, (3) is n-type active layer, (4) is a source electrode, (5
) is a drain electrode, and the source electrode (4) and drain electrode (5) are connected to the active layer (3) as both electrodes +4)! The thickness partial pressure 5) is formed in the etched region, and the upper surfaces of these two electrodes +41'51 and the surface of the curved spinning layer (3) are substantially on one plane.

(6) is a recessed portion for one drain saturation current, and (7) is a gate electrode provided in the recessed portion (6).

First, the manufacturing process of the present invention FET L2) will be explained. N-type buffer layer (2) on semi-insulating GaAs thread plate (1)
, N-type previous product JijI (31) is epitaxially grown continuously by vapor phase epitaxy (@2 Figure A). A resist I8) is selectively formed in the channel region, and the resist (8
) as a mask for the above operation/i! t31t-CCf2F
Dry etching is performed to a depth of 4000 mm according to 2 (Fig. 2B).AuGe-N is used as an ohmic metal.
The source electrode (
4) and obtain the drain electrode (5) (No. 2-0). The resist (8) is removed together with the ohmic metal on the U resist (8), and a resist (9) is overlaid (Fig. 2D)
. At this time, the resist (9) is coated on a flat surface with no unevenness, so the surface of the resist (9) has no unevenness and the film thickness is uniform. The resist (
9), and perform chemical etching with alcoholic acid-based etchant to obtain the recessed part (6).

Furthermore, At as a Schottky metal was used as a black gate electrode (7
) is obtained (fJ2 Figure E). Finally, the Schottky metal on the resist (9) is removed together with the resist (9) to complete the FET of the present invention (FIG. 2F).

In the FET of the present invention, since the resist for transferring the photomask pattern is applied on a flat surface, the surface of the resist is also flat and has no unevenness, so that the thick film is also uniform. Therefore, when the photomask is brought into close contact with the resist, there is no gap between the photomask and the resist, so the pattern can be transferred to the toe, which greatly contributes to improving the yield. A similar effect can be obtained even in the case of electron beam exposure.

Furthermore, as shown in FIG. 1, the FET of the present invention has a source electrode (
4) and the drain electrode (5) have a structure in which the channel @ station (gate) is facing down, so these source electrodes (4)
A current flows through the side surface of the drain electrode (5) on the gate side,
Compared to conventional NETs, the distance traveled by carriers is reduced, that is, the series resistance is reduced. Microwave wood (especially 5l)
For devices used in the F band and higher), a slight reduction in series resistance has a large effect on the characteristics (for example, heat-generating wax,
(bias level and amplification degree change), this effect is very large.

FIG. 6 shows another ash embodiment of the present invention. Semi-insulating GaAS
An n-type first layer (3) is grown on the substrate (1), and ions are implanted into the drain region (5a) of the drain region (4a) to form carriers. ! -I'm raising it. Parts of this source@station (4a) and drains 3K (5a) are never etched, and a source electrode (4) and a drain electrode (5) are formed in the etched portions. In (6), the recessed part (7) closes at the gate's pole. fJ
In the other embodiment shown in FIG. 6, a significant reduction in series resistance can be expected.

In this example, GaAs was used as the substrate, but
The present invention is not limited to this.

g) Effects of the Invention As is clear from the above description, in the original example, the resist is formed with a flat and uniform thickness, so that 100,000,000 patterns can be transferred to the resist, and the yield can be improved. Also, its characteristics as a FET for Micro i are well established.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an embodiment of the present invention, and FIG. 2 is a diagram of a manufacturing process of a conventional FET. (1)...Semi-insulating GaAs substrate, (3)...
Operating layer, (4)...Source electrode group i+5+...Drain electrode, (7)...Gate electrode.

Claims (1)

[Claims] 1) In a field effect transistor in which a source electrode, a gate electrode, and a drain electrode are arranged on a semiconductor wafer including an active layer, the bottom surface and the side surface on the gate side of the source electrode and the drain electrode, respectively, are in contact with the semiconductor wafer. death,
A field effect transistor characterized in that a surface of the semiconductor wafer and upper surfaces of the source and drain electrodes are substantially on the same plane.