JPH04186639A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a gate electrode with T-shaped cross section by exposing the part of an upper gate electrode part other than an upper gate electrode region through using optical exposure at the time of forming the upper gate electrode part and by exposing a part of resist film through the electron beam exposure of only a region other than that corresponding to the lower gate electrode in the upper gate electrode region. CONSTITUTION:On a semi-insulating GaAs substrate 1, an active layer 2 is formed by the use of epitaxial growth and a negative type resist 7 is formed by application. Then, an optical exposure region 8 is subjected to optical exposure, e.g. deep UV exposure (wavelength < 300nm) for this negative type resist 7 so that the negative type resist 7 of only that region is completely made negative. Electron beam is applied to a region other than that corresponding to the lower gate electrode in the optical exposure region 8, i.e., only a region Lc on both sides of the region La of the lower gate electrode in the middle of the width Lu of an upper gate electrode by electron- beam exposure. The negative type resist 7 is made negative by the optical exposure and electron-beam exposure, subjected to baking after exposure and developed by alkali developer, etc. After that, a gate metal material such as Al, Ti and Au is deposited on the whole surface so that a gate electrode 5 with a T-shaped cross section is formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, for example, a method of forming a low resistance fine gate of a high frequency field effect semiconductor device such as a high electron mobility transistor (HEMT). It is.

[Prior Art] In order to improve the characteristics of high frequency field effect transistors made of gallium arsenide (GaAs), gate electrodes are particularly required to have a short gate length and low resistance.
Therefore, research is being carried out on techniques for forming gates with a T-shaped cross section.

FIGS. 5(a) to 5(e) are, for example, Japanese Patent Application Laid-Open No. 61-7737.
FIG. 2 is a process cross-sectional view of a conventional method for forming a gate electrode having a T-shaped cross section as disclosed in Publication No. 0;

In this figure, 21 is a semi-insulating GaAs substrate, 22 is a non-doped GaAs buffer layer, and 23 is an n-GaAs active layer (n=IX1017~2X108/cm3
), 24 is a lower resist film, 25 is an upper resist film,
26 is a line indicating gate pattern electron beam exposure, 27 is a line indicating electron beam auxiliary exposure, and 28 is upper resist film 2.
5, 29 is an opening in the lower resist film 24, 30 is a gate recess, 31 is a gate metal material, and 32 is a gate electrode. This manufacturing method will be explained below.

As shown in FIG. 5(a), a semi-insulating GaAs substrate 21
Non-doped GaAS buffer layer 22, n-Ga
The As active layer 23 is sequentially grown epitaxially, and further,
A lower resist film 24 of resist CMR (CMR is a resist disclosed in JP-A-54-66829) and an upper resist film 25 of resist EBR-9 (trade name of a resist manufactured by Toshi) are formed by coating.

Next, these upper and lower resist films 25 and 24 are irradiated with an electron beam at a dose of line 26 and 27 shown in the diagram of FIG. 5(b). In this line section, the horizontal axis shows the position of the upper resist film 25, the vertical axis shows the irradiation intensity, and the irradiation amount shown by line 27 is shown by line 26 showing auxiliary exposure that exposes only the upper resist film 25. The irradiation amount and Do indicate the irradiation amount for exposing up to the lower resist film 24, respectively.

Electron beam exposure was performed at the dose indicated by the line in Figure 5(b), Do, and then methyl isobutyl ketone (MIBK
) and isopropyl alcohol (TPA).
The lower resist films 25 and 24 are developed to obtain the pattern shown in FIG. 5(C).

Note that the semi-insulating GaAs substrate 21 is omitted from FIG. 5(c) onwards.

Next, as shown in FIG. 5(d), a gate recess 30 is formed by wet etching using the lower resist film 24 in which the opening 29 is formed as a mask. This gate recess 30 is formed so as to interrupt the current flowing through the n-GaAs active layer 23 and leave the active layer 23 with an appropriate thickness. Next, a gate metal material 31 such as Ti or Au is deposited at A° C. and unnecessary gate metal material 31 is removed by lift-off, resulting in a lower gate length Lg and an upper gate length Lh as shown in FIG. 5(e). A gate electrode 32 having a T-shaped cross section is obtained.

[Problems to be Solved by the Invention] As described above, when the lower gate length Lg is made smaller, the resistance of the gate electrode 32 becomes larger. The gate electrode 32 having a T-shaped cross section was developed to reduce the lower gate length Lg, reduce the resistance of the gate electrode 32, and increase the cross-sectional area of the gate electrode 32.

The conventional method for manufacturing the gate electrode 32 with a T-shaped cross section uses a two-layer resist structure and forms the upper and lower gate electrode parts by electron beam exposure technology. When forming the resist, the resist shape of the upper gate electrode part must be inverted tapered, otherwise there is a problem that the gate electrode metal will be deposited and the upper gate electrode part will also be removed by the lift-off method. In particular, in the case of conventional positive resists, the shape of the resist produced by electron beam exposure technology becomes a reverse tapered shape if the base of the resist is a substrate, but since the resist is located underneath, it does not become a reverse tapered shape. Due to the above-mentioned problems, the yield was poor, which hindered mass production.

There is also a method of forming a single-layer resist structure using electron beam exposure technology by changing the irradiation dose of the upper and lower gate electrodes, but this requires a long electron beam exposure time and has the same problems as the above, such as poor reprintability. There was a problem.

Furthermore, conventional resists use a positive resist, which results in poor sensitivity and long exposure times, making it difficult to mass-produce.Furthermore, since it is a positive resist, it has poor adhesion to the substrate, resulting in When forming the recess, there were problems such as the resist peeling off due to wet etching.

This invention was made in order to solve the above-mentioned problems, and uses a small negative die for electron beams.
In order to reduce the area for electron beam exposure, the area excluding the upper gate electrode part is made negative by optical exposure, and the area within the upper gate electrode part excluding the part corresponding to the lower gate electrode is exposed to a part of the resist film by electron beam exposure. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can form a gate electrode having a T-shaped cross section, which requires a small amount of electron beam exposure, can be formed stably, and is suitable for mass production, by making the gate electrode negative.

[Means for Solving the Problems 1] The method for manufacturing a semiconductor device according to the present invention uses a single-layer resist structure, which is a negative resist with high sensitivity to electron beam exposure, and uses optical exposure to form the upper gate electrode portion. By exposing a part of the resist film other than the upper gate electrode area using electron beam exposure, and exposing a part of the resist film except for the area corresponding to the lower gate electrode within the upper gate electrode area using electron beam exposure, it is possible to make the resist film negative up to the middle of the thickness direction. After forming an opening corresponding to the upper and lower dimensions of the electrode and forming a gate recess through this opening, a gate metal material is deposited, and the gate metal material other than the gate electrode is removed by a lift-off method, thereby forming a cross-sectional shape. This forms a T-shaped gate recess.

[Operation] In the present invention, in order to form a fine gate with low resistance, a region excluding the upper gate electrode portion is exposed by optical exposure using a negative single layer resist structure, and the upper gate electrode portion is exposed by electron beam exposure. The area other than the area corresponding to the lower gate electrode in the part is exposed to a dose that does not completely turn the resist negative.
By negativeizing halfway in the thickness direction, a resist pattern with a T-shaped cross section is obtained, with the upper dimension being large and the lower dimension corresponding to the gate length being small. Gate metal material is deposited, and a gate with a T-shaped cross section is formed through a lift-off process. Electrodes are formed with good reproducibility.

[Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. In this figure, 1 is a semi-insulating GaAs substrate;
Reference numeral 2 indicates an active layer, 3 a source electrode, 4 a drain electrode, 5 a gate electrode having a T-shaped cross section consisting of a lower gate electrode with a short gate length and an upper gate electrode with a long gate length, and 6 a gate recess. Current flows horizontally in the semi-insulating GaAs substrate 1 in the figure, and the length of the portion of the gate electrode 5 that controls the current that is in contact with the active layer 2, that is, the gate length is no j1.
If this is the case, a product with better characteristics can be obtained.

The process of forming the gate electrode 5 having a T-shaped cross section is shown in FIG.
) to (d).

In FIG. 2, 1 is a semi-insulating GaAs substrate, 2 is an active layer, 7 is a negative resist, 8 is an optical exposure area, 9 is an electron beam exposure area, 1o is an upper resist opening, and 11 is a lower resist opening. show.

First, as shown in FIG. 2(a), an active layer 2 is formed on a semi-insulating GaAs substrate 1 by epitaxial growth, and then a negative resist is applied. The negative resist is, for example, 5AL601-ER7 (trade name of resist manufactured by Sibley Far East Co., Ltd.) and has a film thickness of 0.5 to 1.3 μm.

Next, as shown in FIG. 2(b), this negative resist is subjected to optical exposure, for example, deep TJV exposure (wavelength < 300 nm), to remove the pattern corresponding to the upper gate electrode (for example, the upper gate electrode If the width is Lu, then L
The area where u is 0.5 to 1.5 .mu.m), that is, the optical exposure area 8 shown in FIG. At this time, the negative resist is made negative as shown in the diagram in FIG.

In FIG. 4, the vertical axis shows the negative conversion rate of the negative resist, and the horizontal axis shows the position of the negative resist. As shown in Figure 4,
The optical exposure area 8 is completely negative (negative conversion rate 1).

Next, by electron beam exposure, areas other than the area corresponding to the lower gate electrode in the optical exposure area 8, that is, areas on both sides of the area La of the lower gate electrode between the width Lu of the upper gate electrode shown in FIG. 2(b). Only Lc is irradiated with an electron beam. For example, when Lu=1.0μm, the gate length Lg is 0.2μm.
When necessary, the area La is set as La=axLg (a is 1 to 2
If a is 1.5 in the width of the relationship (value of )', then La = 0.3
μm, and only the region Lc=0.35 μm is the electron beam exposure region 9. At this time, the area Lc is 0°35 μm
There is no problem even if it becomes thicker (a is the coefficient by which the pattern shifts due to electron beam exposure.The irradiation amount is determined when the remaining film rate of the resist is 0.2 to 0.5, as shown in Fig. 3). The irradiation amount Dg, that is, Dg is about 5 to 30 uC/cm
In step 2, the electron beam exposure area 9 is exposed to an electron beam. Figure 3 shows the sensitivity curve of a negative resist. The horizontal axis shows the irradiation dose and the vertical axis shows the residual film rate (standard value) of the resist. Di is the irradiation dose at which the resist starts to turn negative, and Dh is the dose at which it becomes completely negative Indicates the irradiation amount. The above-mentioned 5AL601-ER7 has a high sensitivity with Di of 1 to 5 μc/cm2, so when Dg is exposed with the above-mentioned irradiation amount, the resist has a negative conversion rate of 0 as in the electron beam exposure area 9, as shown in FIG. A resist can be formed with a concentration of .2 to 0.5.

The electron beam exposure area 9 is shown in FIG. 4 as an example with a negative conversion ratio of 0.5. In the above process, the negative resist is made negative by optical exposure and electron beam exposure, baked after exposure, and developed with an alkaline developer, etc., as shown in Figure 2 (
A resist pattern having the opening width Lu of the upper resist opening 10 and the opening width Ld of the lower resist opening 11 shown in c) is obtained. At this time, when the negative resist is exposed by optical exposure, negativeization progresses from the upper part of the resist, so that a reverse tapered pattern can be easily obtained. Next, a certain thickness of the active layer 2 is removed by wet etching using the lower resist opening 11 as a mask to form a gate recess 6. After that, gate metal materials such as Ti and Au are deposited on the entire surface at A℃, and unnecessary gate metal materials are removed by a lift-off method, resulting in a lower gate electrode and an upper gate electrode, as shown in Figure 2(d). A gate electrode 5 having a T-shaped cross section is formed to form the semiconductor device shown in FIG.

It has been confirmed that the exposure time of the electron beam exposure according to the present invention is 115 to 1/10 the irradiation amount of the conventional method, and is effective for mass production. Note that the source and drain electrodes are omitted from FIG. 2 onwards.

[Effects of the Invention] As explained above, the present invention uses a single layer of negative resist, completely negativeizes the area except for the upper gate electrode by optical exposure, and forms the upper gate electrode by electron beam exposure. The upper resist opening is formed using optical exposure by exposing the area in the resist part except for the lower gate electrode part with a dose that does not completely make it negative, and making it negative halfway in the thickness direction. The pattern is stably formed, and the dose of electron beam exposure is 115 to 1/10 of that of the conventional method using positive resist, making it possible to mass-produce the device at low cost and making it possible to achieve fine gate lengths. High performance GaAs MESFET with low gate resistance, Ga
It is effective in manufacturing As low noise HEMTs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the present invention, and FIG. 3 is a view showing a sensitivity curve of a negative resist.
FIG. 4 is a diagram showing the negative conversion rate of a negative resist and its position, and FIG. 5 is a process sectional view showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an active layer,
3 is a source electrode, 4 is a drain electrode, 5 is a gate electrode,
Reference numeral 6 indicates a gate recess, 7 indicates a negative resist, 8 indicates an optical exposure area, 9 indicates an electron beam exposure area, 10 indicates an upper resist opening, and 11 indicates a lower resist opening. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1' Figure 2 (Part 1) Figure 2 (Part 2) ] 1 Figure 3 Figure 4 LCLC Figure 5 (Zone 1) Figure 5 ( Part 2) 11-Lh:

Claims (1)

[Claims] In a method of manufacturing a semiconductor device having a fine gate having a T-shaped cross section, consisting of a lower gate electrode and a larger upper gate electrode on a semiconductor substrate, a negative resist is applied on the semiconductor substrate; A step of optically exposing a region excluding the pattern corresponding to the gate electrode to completely make the resist negative, and completely removing the negative resist in the region of the upper gate electrode region excluding the lower gate electrode region by electron beam exposure. A process of making the part of the thickness negative with a dose that does not make it negative, developing and removing the part that is not negative, forming a gate recess, depositing gate metal material, and removing unnecessary gate metal material by lift-off. A method for manufacturing a semiconductor device, comprising a step of removing.