JPH09266216A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the height from a semiconductor substrate to the upper part of a gate electrode and to reduce gate-source and gate-drier capocitances, by providing a source electrode and a drain electrode on a semiconductor substrate, and constructing a gate electrode located therebetween into an inverted step type cross sectional shape. SOLUTION: A Y shaped cross sectional gate electrode 6 has an inverted step type where a cross sectional shape is gradually increased stepwise in the width toward the upper portion, and includes a lower electrode part 6a fixed to a semiconductor substrate and having width L1 (gate length), a middle electrode part 6b having slightly wider width L3, and an upper electrode part 6c having further wider width L2. Thus, an adjustment of the cross section ensures to form arbitrarily lower gate electrode. The height from the semiconductor substrate 1 to the upper electrode part 6 of the Y shaped cross sectional electrode 6 can be increased to the height corresponding to the total thickness of the resist 2 and the resist 3, and hence gate-source capacitance and gate-drain capacitance can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a Y-shaped cross-section gate electrode and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art FIG. 33 is a sectional view showing a method of manufacturing a semiconductor device having a conventional gate electrode having a T-shaped cross section. As shown in FIG. 33C, the T-shaped cross-section gate electrode 25 has a portion in contact with the semiconductor substrate 20 (hereinafter, referred to as the support portion 2).
5a. ) And a portion supported by the supporting portion (hereinafter referred to as the upper portion 15b). The T-shaped cross-section gate electrode 25 has a fine width (gate length) Lg and is extended in the horizontal direction to increase the horizontal cross-sectional area, so that the gate resistance can be lowered, and thus the high frequency HEMT (High Electron Mobility Transistor), which requires low noise performance in
It has been applied to.

A method of forming a gate electrode having a T-shaped cross section will be described below. First, as shown in FIG. 33A, an active layer 20B is formed on a semi-insulating GaAs substrate 20A by an epitaxial growth method or the like. Next, the source electrode 26 and the drain electrode 27 are formed on the active layer 20B by using an optical exposure method.
To form In other figures, the source electrode 26
The drain electrode 27 and the drain electrode 27 are omitted for simplification of the drawing, and the active layer 20B and the semi-insulating GaAs substrate 20A are collectively referred to as a compound semiconductor substrate or a semiconductor substrate 20.

Next, as also shown in FIG. 33 (a),
A relatively low-sensitivity electron beam positive resist 21 is formed to a thickness of about 0.2 μm, and a relatively high sensitive electron beam positive resist 22 is formed to a thickness of 0.7 μm. Forming a two-layer resist structure. Here, as the material of the resists 21 and 22, for example, high molecular weight PMMA (polymethylmethacrylate) which has low sensitivity to the resist 21, low molecular weight PMMA (polymethylmethacrylate) which has high sensitivity to the resist 22 and the like can be used. Used. Next, the resist 22 in the region where the T-shaped gate electrode is formed is irradiated with an electron beam 23 with a width of about 1.0 μm. The exposure of the electron beam 23 at this time is performed with an exposure amount that does not expose the resist 21. Subsequently, the resist 22 in the T-shaped gate electrode formation region is irradiated with the electron beam 24 with a width narrower than the previous exposure (width of about 0.2 μm) and with an exposure amount larger than the previous exposure.

Next, the exposed regions, that is, the resist 21 having a width of 0.2 μm and the resist 22 having a width of 1.0 μm, are removed by developing with a mixed solution of MIBK (methyl isobutyl ketone) and IPA (isopropyl alcohol). Then, a T-shaped cross-sectional resist pattern having a T-shaped lower electrode portion pattern width of 0.2 μm and a T-shaped upper electrode portion pattern width of 1.0 μm is formed. Next, as shown in FIG. 33 (b),
A metal 24 such as Pt / Au which is a gate electrode metal is deposited. At this time, the metal 24 adheres to the resist 22 as well, but is lifted off by organic cleaning or the like, so that the resist 2 is removed.
2 together with the metal 24 on the resist 2 and the resist 2
2 is removed, and the gate length Lg as shown in FIG.
A T-shaped gate electrode 25 of 0.2 μm is formed.

[0006]

The gate electrode 25 having a T-shaped cross section in the conventional semiconductor device has a height from the semiconductor substrate 20 to the upper portion 25a of the gate electrode 25, that is, the length in the height direction of the supporting portion 25b. Corresponds to the film thickness of the resist 21 described above, and is therefore about 0.2 μm at present. Therefore, the gate-source capacitance and the gate-drain capacitance at this time have low noise in the millimeter wave band of a frequency of 40 GHz or more. However, there was a problem that it was not possible to achieve higher efficiency and higher gain.

In addition, from the semiconductor substrate 20 to the gate electrode 25
In order to increase the height up to the upper portion 25a of the above, the thickness of the above-mentioned resist 21 must be increased, which makes it difficult to miniaturize because the resist becomes thick and the metal 24
However, there is a problem in that the upper portion 25a of the gate electrode 25 and the supporting portion 25b are not connected to each other due to the lateral growth, and it is impossible to form the gate electrode 25 having a T-shaped cross section.

The present invention has been made in order to solve the above-mentioned problems, and the height from the semiconductor substrate to the upper part of the gate electrode can be increased to reduce the gate-source capacitance and the gate-drain capacitance. An object of the present invention is to obtain a high-performance semiconductor device and a manufacturing method thereof.

[0009]

A semiconductor device according to the present invention comprises a semiconductor substrate, a source electrode and a drain electrode provided on the semiconductor substrate, and a gate electrode located between them. It has a step-shaped side sectional shape.

Further, the gate electrode is provided on the semiconductor substrate and has a support portion having a first width, an upper portion provided on the support portion and having a second width wider than the first width, and the support portion. And an upper portion, which is composed of an intermediate portion having a width wider than the first width and narrower than the second width, and a total height of the support portion and the intermediate portion is 0.4 μm. .

Further, the supporting portion is provided coaxially with the upper portion.

Further, the support portion is provided eccentrically with respect to the upper portion.

A method of manufacturing a semiconductor device according to the present invention is directed to a support portion provided on a semiconductor substrate and having a first width, and an upper portion provided on the support portion and having a second width wider than the first width. And a gate electrode having an inverse step type side cross-sectional shape, which is formed between a supporting portion and an upper portion and has an intermediate portion having a width wider than the first width and narrower than the second width. A method for manufacturing an apparatus, comprising a step of applying a first resist on the entire surface of a semiconductor substrate, and a second resist having a higher sensitivity than the first resist and a developing solution different from that of the first resist. A step of applying on one resist, a step of exposing a region of the second resist where the gate electrode is to be formed with a width wider than the first width and narrower than the second width; The first resist in the exposed area is exposed through the resist. The step of exposing the first resist to the first width, and developing the second resist only to remove the second resist in the exposed portion, and then the second resist on the first resist. A step of forming a blank pattern and a third resist which can be developed with a developing solution for the first resist,
Coating the second resist and the first resist in the blank pattern, exposing the third resist with a second width, and developing the third resist and the first resist Then, the step of removing the third resist and the first resist in the exposed portion and forming a punching pattern of the side cross-sectional shape of the reverse step type, Deposit metal for gate electrode,
The method includes a step of forming a gate electrode and a step of removing the first, second and third resists in the unexposed portion.

Between the support part and the upper part, which is provided on the semiconductor substrate and has a first width, and an upper part which is provided on the support part and has a second width wider than the first width. And an intermediate step having a width wider than the first width and narrower than the second width, and a supporting portion is provided eccentrically with respect to the upper portion and has a reverse step type side cross-sectional shape. A method of manufacturing a semiconductor device having a gate electrode, comprising: a step of applying a first resist on the entire surface of a semiconductor substrate; A step of applying the second resist on the first resist, a step of applying a third resist having a higher sensitivity than the second resist and a developing solution different from that of the second resist on the second resist, The first against the third resist and the first resist Exposing a region where a gate electrode is to be formed with a width wider than the second width, and forming a gate electrode with a first width through the third resist with respect to the second resist The step of exposing the predetermined area by offsetting, and developing only the third resist to remove the third resist in the exposed portion, and the third resist on the second resist. A step of forming a removal pattern, a step of applying a fourth resist which can be developed with a developing solution for a second resist, onto the third resist and the second resist in the removal pattern, and a fourth resist A step of exposing the second width to the fourth resist,
Develop the second resist and the first resist to remove the exposed fourth resist, the second resist and the first resist, and form a reverse step type side cross-section punching pattern. And a step of forming a gate electrode by vapor-depositing a metal for a gate electrode in a reverse step type side cross-sectional shape removal pattern, and the first, second, third and And a step of removing the fourth resist.

Further, the source electrode and the drain electrode provided on the semiconductor substrate, the support portion provided on the semiconductor substrate and having a first width, and the support portion provided on the support portion and having a width larger than the first width. It has a reverse step type side cross-sectional shape composed of an upper part having a second width and an intermediate part provided between the support part and the upper part and having a width wider than the first width and narrower than the second width. A method of manufacturing a semiconductor device including a gate electrode, comprising: a step of applying a first resist on the entire surface of a semiconductor substrate; A step of applying a second resist on the first resist, and a step of exposing a region of the second resist on which the gate electrode is to be formed with a width wider than the first width and narrower than the second width. , The source voltage of the first resist and the second resist And a step of exposing the region where the drain electrode is to be formed, and developing only the second resist to remove the second resist in the exposed portion, and to form a second resist on the first resist. A step of forming a resist removal pattern, a step of applying a third resist that can be developed with a developing solution for the first resist on the second resist and the first resist in the removal pattern, and a third step The step of exposing the regions where the source electrode and the drain electrode of the resist are to be formed, and the step of exposing the third resist and the first resist to expose the exposed first and third resists. A step of removing the source electrode and the drain electrode, and forming a blank pattern in the region where the source electrode and the drain electrode are to be formed; By depositing the genus,
A step of forming a source electrode and a drain electrode, a step of removing the third resist in a portion not exposed to light,
A step of applying a fourth resist of the same material as the third resist on the source electrode, the drain electrode, the second resist and the first resist, and exposing the fourth resist with a second width. Steps to be performed and developing the fourth resist and the first resist to remove the exposed first resist and the fourth resist to form a reverse-step-shaped side cross-section punching pattern. Step, the step of forming a gate electrode by vapor-depositing a metal for a gate electrode in a reverse step type side cross-sectional shape punching pattern, and the first, second and fourth resists of the unexposed portion. And a step of removing.

Further, the source electrode and the drain electrode provided on the semiconductor substrate, the support portion provided on the semiconductor substrate and having a first width, and the support portion provided on the support portion and having a width larger than the first width. It has a reverse step type side cross-sectional shape composed of an upper part having a second width and an intermediate part provided between the support part and the upper part and having a width wider than the first width and narrower than the second width. A method of manufacturing a semiconductor device including a gate electrode, comprising: a step of applying a first resist on the entire surface of a semiconductor substrate; and a developing solution having a sensitivity lower than that of the first resist and a developing solution different from that of the first resist. A step of applying a second resist on the first resist, a step of applying a third resist having a higher sensitivity than the second resist and a developer different from the second resist on the second resist, Third resist and first resist are exposed Exposing the area where the gate electrode is to be formed with a width wider than the first width and narrower than the second width with an exposure dose of And a step of performing exposure by offsetting the area where the gate electrode is to be formed, and the source electrodes of the first resist and the second resist with the exposure amount that the second resist and the first resist are exposed. And a step of exposing the region where the drain electrode is to be formed, and developing only the third resist to remove the third resist in the exposed portion, and the third resist on the second resist. A step of forming a removal pattern of the second resist, a step of applying a fourth resist which can be developed with a developing solution of a second resist on the third resist and the second resist in the removal pattern, Source electrode and drain of resist And a step of exposing the fourth electrode, the second resist, and the first resist to the exposed area, and developing the fourth resist, the second resist, and the first resist to expose the fourth resist, the second resist, and A step of removing the first resist and forming a blank pattern in the regions where the source electrode and the drain electrode are to be formed, and a metal for the source electrode and the drain electrode is formed in the blank pattern in the regions where the source electrode and the drain electrode are to be formed. A step of forming a source electrode and a drain electrode by vapor deposition, a step of removing the fourth resist in an unexposed portion, a fifth resist of the same material as the fourth resist, a source electrode,
The step of applying the drain electrode, the second resist and the third resist, the step of exposing the fifth resist with the second width, the fifth resist, the second resist and the first resist. The step of developing the resist to remove the fifth resist, the second resist, and the first resist in the exposed portions, and forming a reverse-step type side cross-section punching pattern; A step of vapor-depositing a metal for a gate electrode in a punched pattern of a side cross-sectional shape to form a gate electrode, and a step of removing the first, second, third and fifth resists in a portion which has not been exposed. Is equipped with.

Further, the first resist and the second resist are applied so that the total layer thickness of the first resist and the second resist becomes 0.4 μm.

The first resist and the second resist are made of materials that do not cause mixing with each other.

Further, the first resist, the second resist and the third resist are applied so that the total layer thickness of the first resist, the second resist and the third resist becomes 0.4 μm. .

Further, the first resist and the second resist are composed of materials which do not cause mixing with each other,
The second resist and the third resist are composed of materials that do not mix with each other.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Hereinafter, a method of manufacturing a semiconductor device having a Y-shaped cross-section gate electrode according to an embodiment of the present invention using a three-layer resist will be described with reference to FIGS. The gate electrode 6 having a Y-shaped cross section formed here
As shown in FIG. 6, has a reverse step type whose side cross-sectional shape gradually increases in width upward in a stepwise manner. The Y-shaped cross-section gate electrode 6 is fixed to the semiconductor substrate and has a width L1 (gate length Lg = L1).
a, the middle electrode portion 6 having a width L3 slightly wider than the lower electrode portion 6a
b, and the upper electrode portion 6c having a width L2 wider than the middle electrode portion 6b (L1 <L3 <L2).
Since the gate electrode 6 having a Y-shaped cross section is provided to extend in the horizontal direction on the semiconductor substrate, the gate resistance can be arbitrarily lowered by adjusting the cross-sectional area according to the length thereof.
First, as shown in FIG. 1, a source electrode 8 and a drain electrode 9 are formed on a compound semiconductor substrate 1 in which an active layer 1B is formed on a semi-insulating GaAs substrate 1A using an epitaxial growth method or the like. Note that in the drawings after FIG. 2, the semi-insulating GaAs substrate 1A and the active layer 1B are omitted for simplification of the drawing, and are simply (compound) semiconductor substrate 1.

Next, as shown in FIG. 1 as well, on the compound semiconductor substrate 1, the resist 2 which becomes the resist of the lowermost layer is applied in a thickness of 0.2 μm, and the resist 3 which becomes the resist of the intermediate layer is formed thereon. With a thickness of 0.2 μm. The resist 2 is an electron beam (hereinafter referred to as EB), Deep UV,
A positive resist that is sensitive to X-rays, has a lower sensitivity than Resist 3, and does not dissolve in the developer of Resist 3, such as PMGI
(Polydimethylglutarimide).
On the other hand, the resist 3 is a positive resist that is sensitive to electron beams, deep UV, and X-rays, has higher sensitivity than the resist 2, does not dissolve in the developer of the resist 2, and does not mix with the resist 2. For example, the product name ZEP520 manufactured by Nippon Zeon Co., Ltd. is used.

As shown in FIG. 2, from the top of the resist 3 E
The width L1 of the lower electrode portion of the Y-shaped cross-section gate electrode 6 with respect to the resist 3 in the region where the Y-shaped cross-section gate electrode 6 (see FIG. 6) to be formed in a later step is exposed using the B exposure 10. Is wider than the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 (L1 <L3 <L3 ′ <L).
2, for example, L3 ′ = 0.35 μm, where L
3 is the width of the middle electrode portion 6b of the gate electrode 6 having a Y-shaped cross section,
The difference between L3 and L3 ′ corresponds to the layer thickness of the mixing layer 4 described later. ), And exposure is performed with a low exposure amount such that the resist 2 is not exposed. Next, the resist 2 is exposed through the resist 3 with the width L1 of the lower electrode portion of the Y-shaped cross-section gate electrode 6 and with an exposure amount larger than that described above. In addition, with respect to a region where the gate pad electrode 7 (see FIG. 6) is to be formed in a later step, the width of the gate pad electrode 7 is slightly wider than that of the gate pad electrode 7 and the resist 2 is formed by EB exposure 10 or optical exposure. The exposure is performed with the exposure amount for exposing. In the figure, the length of the arrowed line of the EB exposure 10 indicates the exposure amount.

Next, as shown in FIG. 3, with a developing solution for the resist 3, for example, xylene as an organic solvent, only the resist 3 in the region where the gate electrode 6 having the Y-shaped cross section is to be formed has a width L3 '.
A blank pattern (for example, 0.35 μm) is formed. At this time, the resist 2 is not dissolved by xylene,
A pattern is formed only on the resist 3. At the same time,
Also in the resist 3 in the area where the gate pad electrode 7 is to be formed,
A blank pattern having a width slightly wider than the width of the gate pad electrode 7 is formed.

Next, as shown in FIG. 4, a resist 5 which is an optical exposure resist and can be dissolved in a developing solution for the resist 2.
For example, 1 image reversal resist
Apply with a film thickness of μm. At this time, the mixing layer 4 having a thickness of about 200Å is formed between the resist 3 and the resist 5. Next, with respect to the resist 5 in the region where the Y-shaped cross-section gate electrode 6 is to be formed, the exposure amount is such that the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 and the resist 2 is not exposed. Optical exposure. At the same time,
Optical exposure is performed in a region where the gate pad electrode 7 is to be formed with a width slightly wider than the width of the gate pad electrode 7.

As shown in FIG. 5, after the exposure, the image is inverted, the resist 2 and the resist 5 are subjected to organic alkali development, and the exposed Y-shaped gate electrode is formed in a region where the Y-shaped cross-section gate electrode 6 is to be formed. Width L2 of the upper electrode portion 6c of 6
The resist 5 (for example, 0.7 μm) and the resist 2 having the width L1 (for example, 0.2 μm) of the lower electrode portion of the Y-shaped gate electrode 6 are removed to form a blank pattern. At the same time, in the region where the gate pad electrode 7 is to be formed, the resist 2 and the resist 5 having a width slightly wider than the exposed width of the gate pad electrode 7 are removed to form a blank pattern. In addition, in FIG.
The B exposure 10 is used to form a pattern by coating, exposing, and developing the resist 5 without exposing the resist 2 to the width L1 of the lower electrode portion in the region where the Y-shaped cross-section gate electrode 6 is to be formed. Width L3 for resist 2 using 10
The inside may be exposed to the width L1 and then the organic alkali development may be performed. In that case, the structure shown in FIG. 5 can be obtained.

Further, as shown in FIG. 6, the semiconductor substrate 1
Of the lower electrode portion of the Y-shaped cross-section gate electrode 6, respectively, in the regions where the Y-shaped cross-section gate electrode 6 is to be formed and the gate pad electrode 7 are to be formed. After forming the recess 12 having a width slightly larger than the width L1 and the width of the gate pad electrode 7, a metal such as Pt / Au, which is a material of the gate electrode metal 6 and the gate pad electrode 7, is 6000Å. The metal film deposited on the resist 5 and the resist 5, the resist 3 and the mixing layer 4 are removed by a lift-off process so that the gate length L1 is 0.2 μm and the Y-shaped cross section is 0.2 μm as shown in FIG. The mold gate electrode 6 and the gate pad electrode 7 are formed. Thereby, the semiconductor substrate 1
Since the height from the gate electrode 6 to the upper electrode portion 6c of the Y-shaped cross-section electrode 6 can be increased to about 0.4 μm, which is the combined thickness of the resist 2 and the resist 3,
The source capacitance and the gate / drain capacitance can be reduced.

As described above, in this embodiment,
The height from the semiconductor substrate 1 to the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 can be increased to about 0.4 μm, which corresponds to the total thickness of the resist 2 and the resist 3, and the gate-source capacitance and The gate-drain capacitance can be reduced, and high gain and high output can be achieved in the high frequency band. Further, the middle electrode portion 6a allows the upper electrode portion 6a to
Since the joint portion between c and the lower electrode portion 6a can be thickened, the mechanical strength can be improved and the reliability of the gate electrode 6 can be improved.

Embodiment 2 Hereinafter, a method of manufacturing a semiconductor device in which a Y-shaped cross-section gate is formed by self-alignment according to another embodiment of the present invention will be described with reference to FIGS.
First, as shown in FIG. 7, as in the first embodiment, a resist 2 having a thickness of 0.2 μm and a resist 3 having a thickness of 0.2 μm are formed thereon, and two layers are formed on the compound semiconductor substrate 1. Form a resist.

In this embodiment, the source electrode and the drain electrode are formed in self-alignment with the gate electrode. Therefore, as shown in FIG. With respect to the resist 3 in the region where the type gate electrode 6 is to be formed, the width is wider than the width L1 of the lower electrode portion of the Y-shaped cross-section gate electrode 6, and is greater than the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6. With a narrow width L3 '(L
1 <L3 <L3 '<L2, for example, L3' = 0.35μ
m), and exposure is performed with a low exposure amount such that the resist 2 is not exposed. Next, an area for forming the source electrode 8 and the drain electrode 9 (see FIG. 12) to be formed in a later step is exposed with an exposure amount enough to expose the resist 2. Note that the gate pad electrode 7 (see FIG. 6) is omitted in FIGS. 7 to 15.

As shown in FIG. 9, a developing solution for the resist 3,
For example, an organic solvent, xylene, is used to form a blank pattern having a width L3 ′ (eg, 0.35 μm) in a region where the gate electrode 6 having a Y-shaped cross section is to be formed, and at the same time, the source electrode 8 and drain electrode 9 are formed. A blanking pattern having a width corresponding to the above is formed in the formation scheduled region. At this time, the resist 2 is not dissolved by xylene.

Next, as shown in FIG. 10, a resist 5 for optical exposure, for example, image reversal (image reversal).
Apply a resist of 1 μm. At this time, the mixing layer 4 is formed between the resist 3 and the resist 5. Next, the resist 5 in the regions where the source electrode 8 and the drain electrode 9 are to be formed is exposed by optical exposure.

As shown in FIG. 11, after the exposure, the image is inverted, and the resist 5 and the resist 2 in the blank pattern portion for the source electrode 8 and the drain electrode 9 are removed by organic alkali development to remove the source electrode 8 A region for forming the drain electrode 9 is opened. Here, since the regions where the source electrode 8 and the drain electrode 9 are to be formed of the resist 2 are exposed by the EB exposure of FIG. 8, they are removed at the same time as the resist 5 by the above-mentioned development to form a blank pattern. Is.

Next, after the metal for forming the source electrode 8 and the drain electrode 9 is vapor-deposited using the resist 5 as a mask, an organic solvent in which the resist 2 and the resist 3 are not dissolved but only the resist 5 is dissolved, For example, the resist 5 is lifted off with acetone. As a result, FIG.
As shown in FIG. 4, the source electrode 8 and the drain electrode 9 are left while leaving the resist 2, the resist 3 and the mixing layer 4.
Is formed.

As shown in FIG. 13, a resist 5A made of the same material as the above-mentioned resist 5, that is, a material which is for optical exposure and is soluble in a developing solution for the resist 2, for example, image reversal (image reversal). The resist is applied to the entire surface by 1 μm. Then, the resist 5A is subjected to optical exposure with a width corresponding to the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6.

After the exposure, the image is inverted, and the resist 2 and the resist 5A are removed by organic alkali development, as shown in FIG. As a result, the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 is 0.7 μm, for example, to the resist 5A, and the width L1 of the lower electrode portion of the Y-shaped cross-section gate electrode 6 is 0. A blank pattern is formed on the resist 2 with a thickness of 2 μm.

As shown in FIG. 15, after the active layer 1B (see FIG. 1) is etched to form the recess 12, the resist 5A is used as a mask to remove the metal such as Pt / Au forming the gate electrode 6. , Vapor deposition with a layer thickness of about 6000Å. Next, the resist 2, the resist 3, the mixing layer 4, and the resist 5A are removed by lift-off, so that a Y-shaped cross-section gate electrode 6 having a gate length Lg of 0.2 μm is formed as shown in FIG.

Thus, in this embodiment,
The gate electrode 6 having a Y-shaped cross section can be formed on the source electrode 8 and the drain electrode 9 by EB exposure 10 in FIG. Also,
The height from the semiconductor substrate 1 to the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 can be increased to about 0.4 μm, which corresponds to the total thickness of the resist 2 and the resist 3, and the gate-source capacitance and The gate / drain capacitance can be reduced. In the method of manufacturing a semiconductor device having an electrode structure with a Y-shaped cross-section according to the present invention, the gate, source, and drain electrodes can be formed in a self-aligned manner, so that they can be easily formed and the yield can be improved.

Embodiment 3 Hereinafter, another embodiment of a manufacturing method for forming a semiconductor device having a Y-shaped cross-section gate electrode using a four-layer resist will be described with reference to FIGS. First, similarly to the first embodiment, as shown in FIG. 16, the source electrode 8 and the drain electrode 9 are formed on the semiconductor substrate 1. Next, on the semiconductor substrate 1, the lowermost layer resist 11 has a thickness of 0.1 μm, the intermediate layer resist 2 has a thickness of 0.1 μm, and the uppermost layer resist 3 has a thickness of 0 μm. Apply at 2 μm. Resist 11
Has sensitivity to electron beam (EB), Deep UV, X-rays, higher sensitivity than resist 2 and almost the same sensitivity as resist 3, and does not dissolve in the developer of resist 2
On the other hand, it is a positive resist that does not generate mixing, and is composed of, for example, a trade name ZEP7100 manufactured by Nippon Zeon Co., Ltd. For the resist 2, electron beam (EB), DeepU
A positive resist that has sensitivity to V and X-rays, is less sensitive than resist 3, and does not dissolve in the developing solution of resist 3, such as P
MGI (polydimethylglutarimide) is used. Resist 3 has sensitivity to electron beam, Deep UV, X-ray,
Higher sensitivity than resist 2, resist 2 and resist 11
A positive resist that does not dissolve in the developing solution and does not cause mixing with the resist 2, for example, ZEP520 manufactured by Nippon Zeon Co., Ltd. is used.

As shown in FIG. 17, EB exposure 10 is applied from above the resist 3 to the resist 3 and the resist 11, which is wider than the width of the lower electrode portion of the Y-shaped cross-section gate electrode 6 and has a Y-shaped cross section. The width L3 'of the mold gate electrode 6 narrower than the upper electrode portion 6c is exposed with a low exposure amount. Also, the resist 2
For the lower electrode portion L1 of the gate electrode 6 having a Y-shaped cross section.
With a high exposure amount, the region of the recess 12 to be formed is offset and exposed. Here, the offset means that the center line is displaced leftward or rightward by a predetermined distance (eccentricity). Therefore, as described above, the L1 has a recess 12 (of the recess 12) as shown in FIG. It means that the center line of the area to be formed does not share the center line and the center line is displaced by a predetermined distance in the left or right direction (right direction in FIG. 22). In addition, the gate pad electrode 7 (see FIG. 22)
The area planned to be formed by EB exposure 10 or optical exposure,
The resist 2 is exposed to light with an exposure amount.

As shown in FIG. 18, the resist 3 is developed with a developing solution of the resist 3, for example, xylene which is an organic solvent.
A width L3 ′, for example, a punching pattern having a width of 0.35 μm and a punching pattern corresponding to the width of the gate pad electrode 7 are formed. At this time, the resist 2 and the resist 11
Is not dissolved in xylene.

As shown in FIG. 19, a resist 5 for optical exposure, which is soluble in the developing solution of the resist 2, for example, an image reversal resist 5 is applied to a thickness of 1 μm. At this time, the mixing layer 4 having a thickness of about 200Å is formed between the resist 3 and the resist 5. Next, the resist 5 is exposed by optical exposure with the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6.

As shown in FIG. 20, after the exposure, the image is inverted, and the resist 2 and the resist 5 are subjected to organic alkali development, and a blank pattern having a width L2, for example, 0.7 μm is formed in the resist 5.
Then, a blank pattern having a width L1, for example, 0.2 μm is formed in the resist 2. At the same time, the resist 2 and the resist 5 in the region where the gate pad electrode 7 is to be formed are opened. At this time, in the step of FIG. 17, since the width of the lower electrode portion of the Y-shaped cross-section gate electrode 6 is offset from the region where the recess 12 is to be formed and exposed,
The resist 2 with respect to the blank pattern of the width L2 of the resist 5
The blank pattern having the width L1 is offset.

As shown in FIG. 21, only the resist 11 is
For example, by developing with methyl isobutyl ketone, a punched pattern is formed with a width L4 (= L3 ′) corresponding to the width of the recess 12, for example, 0.3 μm. This punched pattern has a width L1 of the resist 2. Offset is applied to the blank pattern.

The recess 12 is formed by etching the active layer 1B (see FIG. 1) of the semiconductor substrate 1, and the resist 5 is masked to form Pt / Au, which is a metal forming the Y-shaped cross-section gate electrode 6. After depositing about 6000Å, lift-off is performed to remove the resist 5 and the like.
When the gate length Lg = 0.2 μm as shown in FIG.
Y-shaped cross-section gate electrode 6 with offset inside
Can be formed without misalignment due to superposition, and the gate pad electrode 7 can be formed at the same time.

As a result, the height from the semiconductor substrate 1 to the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 is set to the resist 2
The total thickness of the resist 3 and the resist 3 can be increased to about 0.4 μm.
The drain capacitance can be reduced, and the lower electrode portion of the Y-shaped cross-section gate electrode 6 is recessed by the method described above.
Since the offset can be easily applied within 2, the source resistance and the source / drain capacitance can be reduced when the lower electrode portion of the Y-shaped cross-section gate electrode 6 is brought closer to the source electrode 8 side in the recess 12. Further, the recess 12 in the present invention
The structure of the Y-shaped cross-section gate electrode 6 having an offset inside reduces the damage to the semiconductor substrate such as plasma processing in a later step because the upper electrode portion 6c is provided so as to cover the upper portion of the recess 12. be able to.

Embodiment 4 23 to 32, another embodiment of the method of manufacturing a semiconductor device according to the present invention for forming a Y-shaped cross-section gate by self-alignment will be described.
First, as in the third embodiment, first, as shown in FIG. 23, a lowermost layer resist 11 having a thickness of 0.1 μm is formed on a semiconductor substrate 1, and an intermediate layer resist 2 having a thickness of 0.1 μm is formed thereon. 1
.mu.m, and the topmost resist 3 having a thickness of 0.
Apply at 2 μm.

In this embodiment, since the source electrode and the drain electrode are formed in self-alignment with the gate electrode, the EB exposure 10 is performed once from above the resist 3 as shown in FIG. The width of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 is larger than the width L1 of the lower electrode portion of the Y-shaped cross-section gate electrode 6 with respect to the resist 3 in the region where the Y-shaped cross-section gate electrode 6 is to be formed. Width L narrower than width L2
3'and exposure is performed with an exposure amount that the resist 3 and the resist 11 are exposed. Next, with respect to the resist 2, the width L1 of the lower electrode portion of the Y-shaped cross-section gate electrode 6 is high with a high exposure amount.
(See FIG. 22), and an exposure is performed by offsetting the area where the recess 12 is to be formed. Further, the resist 2 and the resist 1 are formed on the regions where the source electrode 8 and the drain electrode 9 (see FIG. 29) are to be formed in the subsequent steps.
Exposure is performed with an exposure amount that 1 is exposed. 23 to 32, the gate pad electrode 7 (see FIG. 6) is omitted.

As shown in FIG. 25, a developing solution for the resist 3, for example, xylene as an organic solvent, is used to form a width L3 'in a region where the gate electrode 6 having the Y-shaped cross section is to be formed only in the resist 3.
A blank pattern (for example, 0.35 μm) is formed, and at the same time, a blank pattern having a width corresponding to those is formed in the regions where the source electrode 8 and the drain electrode 9 are to be formed.
At this time, the resists 2 and 11 are not dissolved by xylene.

Next, as shown in FIG. 26, a resist 5 for optical exposure, for example, image reversal (image reversal).
Apply a resist of 1 μm. At this time, the mixing layer 4 is formed between the resist 3 and the resist 5. Next, the resist 5 in the regions where the source electrode 8 and the drain electrode 9 are to be formed is exposed by optical exposure.

As shown in FIG. 27, after the exposure, the image is inverted, and the resist 5 and the resist 2 in the blank pattern portion for the source electrode 8 and the drain electrode 9 are removed by organic alkali development to remove the source electrode 8 An opening is formed in the area where the drain electrode 9 is to be formed, and a blank pattern in which only the resist 11 remains is formed. Here, since the regions where the source electrode 8 and the drain electrode 9 are to be formed of the resist 2 have been exposed by the EB exposure 10 of FIG. 24, they are removed at the same time as the resist 5 by the above development to form a blank pattern. It is a thing.

As shown in FIG. 28, the resist 11 is organically developed, for example, with methyl isobutyl ketone to open the regions where the source electrode 8 and the drain electrode 9 are to be formed.

Next, after the metal for forming the source electrode 8 and the drain electrode 9 is vapor-deposited using the resist 5 as a mask, the resist 2, the resist 3 and the resist 11 are not dissolved but only the resist 5 is dissolved. The resist 5 is lifted off with an organic solvent such as acetone. Thereby, as shown in FIG. 29, the source electrode 8 and the drain electrode 9 are formed while leaving the resist 2, the resist 3, the mixing layer 4, and the resist 11.

Next, a resist 5A made of the same material as the resist 5 described above, that is, a material for optical exposure and soluble in the developing solution for the resist 2, for example, an image reversal resist, is used for the entire surface. To 1 μm. Then, the resist 5A is subjected to optical exposure with a width corresponding to the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6. Then, after exposure, reverse the image,
As shown in FIG. 30, the resist 2 and the resist 5A are removed by organic alkali development. Thereby, the width L2 of the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6, for example, 0.7
μm to resist 5A and Y-shaped cross-section gate electrode 6
A blank pattern is formed in the resist 2 with the width L1 of the lower electrode portion of, for example, 0.2 μm.

As shown in FIG. 31, only the resist 11 is
For example, by developing with methyl isobutyl ketone, a width L4 corresponding to the width of the recess 12, for example, 0.3
A punching pattern is formed with a thickness of μm, and this punching pattern is offset with respect to the punching pattern having the width L1 of the resist 2.

As shown in FIG. 32, after the active layer 1B (see FIG. 1) is etched to form the recess 12, the resist 5A is used as a mask to remove metal such as Pt / Au forming the gate electrode 6. , Vapor deposition with a layer thickness of about 6000Å. Next, when the resist 11, the resist 2, the resist 3, the mixing layer 4 and the resist 5A are removed by lift-off, the gate length Lg 0.2 μ as shown in FIG.
A gate electrode 6 having a Y-shaped cross section is formed.

As a result, the height from the semiconductor substrate 1 to the upper electrode portion 6c of the Y-shaped cross-section gate electrode 6 is set to the resist 2
The total thickness of the resist 3 and the resist 3 can be increased to about 0.4 μm.
The drain capacitance can be reduced, and the lower electrode portion of the Y-shaped cross-section gate electrode 6 is recessed by the method described above.
Since the offset can be easily applied within 2, the source resistance and the source / drain capacitance can be reduced when the lower electrode portion of the Y-shaped cross-section gate electrode 6 is brought closer to the source electrode 8 side in the recess 12. Further, the recess 12 in the present invention
The structure of the Y-shaped cross-section gate electrode 6 having an offset inside reduces the damage to the semiconductor substrate such as plasma processing in a later step because the upper electrode portion 6c is provided so as to cover the upper portion of the recess 12. be able to. In the method of manufacturing a semiconductor device having an electrode structure with a Y-shaped cross-section according to the present invention, the gate, source, and drain electrodes can be formed in a self-aligned manner, so that they can be easily formed and the yield can be improved.

[0058]

According to the semiconductor device of the present invention, it is provided with a semiconductor substrate, a source electrode and a drain electrode provided on the semiconductor substrate, and a gate electrode located between them.
Since the gate electrode has the reverse step type side cross-sectional shape, the height from the semiconductor substrate to the upper part of the gate electrode can be increased, which can reduce the gate-source capacitance and the gate-drain capacitance. Since it is a reverse step type, it is possible to obtain a gate electrode with a stable connection between the upper part of the electrode and the part supporting it while maintaining a fine gate length, and it is possible to improve the electrical reliability. Play.

Further, a semiconductor substrate and a gate electrode provided on the semiconductor substrate are provided. The gate electrode is fixed on the semiconductor substrate and has a support portion having a first width, and the support portion is provided on the support portion. An upper portion having a second width wider than the width of the support portion, and an intermediate portion provided between the support portion and the upper portion and having a width wider than the first width and narrower than the second width, Since the total height of the support portion and the intermediate portion is 0.4 μm, the height of the upper portion of the gate electrode from the semiconductor substrate can be made higher than that of the conventional T-shaped cross-section gate.
The gate-source capacitance and the gate-drain capacitance can be reduced, and high gain and high output can be achieved in a high frequency band.

Further, since the support portion is provided coaxially with the upper portion, it is stable and has high reliability.

Further, since the supporting portion is provided not on the same axis as the upper portion but on the other side, it is possible to reduce the source resistance when the gate electrode is brought closer to the source electrode side.
The source / drain capacitance can be reduced.

Further, in the method for manufacturing a semiconductor device according to the present invention, the support portion provided on the semiconductor substrate and having the first width, and the second support portion provided on the support portion and wider than the first width are provided. A gate having an inverted step type side cross-sectional shape including an upper portion having a width and an intermediate portion provided between the support portion and the upper portion and having a width wider than the first width and narrower than the second width. A method of manufacturing a semiconductor device including an electrode, comprising: a step of applying a first resist on the entire surface of a semiconductor substrate; and a second resist having a higher sensitivity than the first resist and a developing solution different from that of the first resist. The step of applying the resist on the first resist, and the step of exposing the area where the gate electrode of the second resist is to be formed with a width wider than the first width and narrower than the second width. , Through the second resist, the first in the exposed area Step of exposing the resist to the first width, and developing only the second resist to remove the second resist in the exposed portion, and the second resist on the first resist. A step of forming a removal pattern of the first resist, a step of applying a third resist that can be developed with a developing solution of the first resist on the second resist and on the first resist in the removal pattern, Exposing the resist in a second width, developing the third resist and the first resist, and removing the third resist and the first resist in the exposed portion, and the reverse step The step of forming the side cross-section punching pattern of the mold, the step of depositing the metal for the gate electrode in the side step cross-section punching pattern of the reverse step mold to form the gate electrode, and the step of unexposed part First, second and third resist Since it is provided with a step of removing, it is possible to easily manufacture a semiconductor device in which the height from the semiconductor substrate to the upper part of the gate electrode is higher than that of the conventional T-shaped cross-section gate, and it is possible to easily manufacture the semiconductor device. It is possible to achieve high gain and high output in the high frequency band, which can reduce the gate / drain capacitance.

Further, the support portion is provided on the semiconductor substrate and has a first width, and the upper portion is provided on the support portion and has a second width wider than the first width. Is a method of manufacturing a semiconductor device provided with a gate electrode having a side cross-sectional shape of an inverse step type, which is provided not in coaxial with the upper portion but on the entire surface of a semiconductor substrate. A step of applying a resist, a step of applying a second resist having a lower sensitivity than the first resist and a developer different from the first resist on the first resist,
A step of applying a third resist on the second resist, which has a higher sensitivity than the second resist and a developing solution different from that of the second resist, and which is wider than the first width with respect to the third resist. The step of exposing the area where the gate electrode is to be formed with a width narrower than the width, and the second resist with respect to the area where the gate electrode is to be formed with the first width through the third resist. Step of exposing by applying offset, and developing only the third resist to remove the third resist in the exposed portion, and forming a third resist blank pattern on the second resist A step of applying a fourth resist which can be developed with a developing solution of a second resist, on the third resist and on the second resist in the removal pattern,
Exposing the fourth resist with a second width,
The fourth resist, the second resist and the first resist are developed to remove the exposed fourth resist, the second resist and the first resist, and the reverse step type side sectional shape. Forming a punched pattern, a step of forming a gate electrode metal in the punching pattern of the side cross-sectional shape of the reverse step type to form a gate electrode, and the first and second portions not exposed. Since the step of removing the third and fourth resists is provided, it is possible to dispose the support portion not coaxially with the upper portion,
When the gate electrode is brought closer to the source electrode side, it is possible to easily manufacture a semiconductor device capable of reducing the source resistance and the source / drain capacitance. In the electrode structure of the Y-shaped cross-section gate having an offset in the recess, since the upper part of the gate electrode covers the upper part of the recess, it is possible to reduce damage to the semiconductor substrate such as plasma processing in a later step.

Further, the source electrode and the drain electrode provided on the semiconductor substrate, the support portion provided on the semiconductor substrate and having the first width, and the support portion provided on the support portion and wider than the first width. A method of manufacturing a semiconductor device comprising a gate electrode having a reverse step type side cross-sectional shape composed of an upper portion having a second width, wherein a first resist is applied to the entire surface of a semiconductor substrate. Step, a step of applying a second resist having a higher sensitivity than the first resist and a developing solution different from that of the first resist on the first resist, and a region for forming the gate electrode of the second resist And a step of performing exposure with a width that is wider than the first width and narrower than the second width, and a step of performing exposure with respect to the regions where the source and drain electrodes of the first resist and the second resist are to be formed. , Second Regis Only the second resist is developed to remove the second resist in the exposed portion, and a second resist punching pattern is formed on the first resist, and development can be performed with the first resist developer. A step of applying a third resist on the second resist and the first resist in the blank pattern, a step of exposing the regions where the source and drain electrodes of the third resist are to be formed, and A step of developing the third resist and the first resist, removing the first resist and the third resist in the exposed portion, and forming a blank pattern in the regions where the source electrode and the drain electrode are to be formed; A step of forming a source electrode and a drain electrode by vapor-depositing a metal for the source electrode and the drain electrode on a blank pattern of a region where the source electrode and the drain electrode are to be formed, and performing exposure. Removing the third resist the free portion, the fourth resist in the same material as the third resist, the source electrode, the drain electrode,
The step of applying on the second resist and the first resist, the step of exposing the fourth resist with a second width, and developing the fourth resist and the first resist to expose. The step of removing the first resist and the fourth resist in the performed portion and forming a punching pattern of the reverse step type side sectional shape, and a metal for a gate electrode in the punching pattern of the reverse step type side sectional shape Since a step of forming a gate electrode by vapor deposition and a step of removing the first, second, and fourth resists in the unexposed portion are provided, the gate electrode can be formed more than a conventional T-shaped cross-section gate. It is possible to easily manufacture a semiconductor device in which the height from the semiconductor substrate to the upper part of the gate electrode is increased, and it is possible to reduce the gate / source capacitance and the gate / drain capacitance, and achieve high gain and high output in the high frequency band. With , The gate electrode, the source electrode and the drain electrode can be easily formed because it can form a self-aligned, thereby improving the yield.

Further, the source electrode and the drain electrode provided on the semiconductor substrate, the support portion provided on the semiconductor substrate and having the first width, and the support portion provided on the support portion and wider than the first width. A method of manufacturing a semiconductor device comprising a gate electrode having a reverse step type side cross-sectional shape composed of an upper portion having a second width, wherein a first resist is applied to the entire surface of a semiconductor substrate. A step of applying a second resist having a lower sensitivity than the first resist and a developing solution different from that of the first resist on the first resist, and having a higher sensitivity than the second resist, and a second resist A step of applying a third resist having a different developing solution from that of the resist on the second resist, and an exposure amount that the third resist and the first resist are exposed to, and the width is wider than the first width and narrower than the second width. The width of the gate electrode Exposing a region to the second resist, exposing the second resist through the third resist with a first width to the region where the gate electrode is to be formed by offsetting, and exposing Exposing the second resist and the first resist to the regions where the source electrode and the drain electrode of the first resist and the second resist are to be formed with an exposure amount that is exposed to light, and developing only the third resist. The step of removing the third resist in the exposed portion and forming a third resist removal pattern on the second resist, and the fourth resist which can be developed with a developing solution for the second resist. On the third resist and on the second resist in the blanking pattern, exposing the regions where the source and drain electrodes of the fourth resist are to be formed, and exposing the fourth resist ,second The resist and the first resist are developed, the exposed fourth resist, the second resist and the first resist are removed, and a blank pattern is formed in the regions where the source electrode and the drain electrode are to be formed. And the step of forming a source electrode and a drain electrode by vapor-depositing the metal for the source electrode and the drain electrode on the blank pattern of the region where the source electrode and the drain electrode are to be formed, and The step of removing the fourth resist, the fifth resist of the same material as the fourth resist, the source electrode, the drain electrode,
The step of applying on the second resist and the third resist, the step of exposing the fifth resist with the second width, and the development of the fifth resist, the second resist and the first resist. Then, the step of removing the fifth resist, the second resist, and the first resist in the exposed portion to form the punched pattern of the reverse step type side cross-sectional shape, and the reverse step type side cross-sectional shape A step of vapor-depositing a metal for a gate electrode in the blank pattern to form a gate electrode, and a step of removing the first, second, third and fifth resists in the unexposed portion. Therefore, it is possible to easily manufacture a semiconductor device in which the height from the semiconductor substrate to the upper part of the gate electrode is higher than that of the conventional T-shaped cross-section gate, and it is possible to reduce the gate-source capacitance and the gate-drain capacitance. ,high frequency High gain at frequency, with a high output can be achieved, a gate electrode, a source electrode and a drain electrode can be easily formed because it can form a self-aligned,
Since the yield can be improved and the support part can be provided off-axis rather than coaxially, the source resistance can be reduced and the source / drain capacitance can be reduced when the gate electrode is moved closer to the source electrode side. It is possible to easily manufacture a semiconductor device capable of reducing the noise.

Since the first resist and the second resist are applied so that the total layer thickness of the first resist and the second resist is 0.4 μm, the conventional cross section is It is possible to easily manufacture a semiconductor device in which the height from the semiconductor substrate to the upper portion of the gate electrode is higher than that of the T-shaped gate.

Further, since the first resist and the second resist are made of materials which do not cause mixing with each other, the gate electrode can be manufactured without misalignment due to superposition.

Further, the first resist, the second resist and the third resist are applied so that the total layer thickness of the first resist, the second resist and the third resist is 0.4 μm. Therefore, since the first resist and the second resist are applied, a semiconductor device in which the height from the semiconductor substrate to the upper part of the gate electrode is higher than that of the conventional T-shaped cross-section gate is provided. It can be easily manufactured.

Since the first resist and the second resist are made of materials that do not mix with each other, and the second resist and the third resist are made of materials that do not mix with each other, The gate electrode can be manufactured without misalignment due to the alignment.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the three-layer resist according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the three-layer resist according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the three-layer resist according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the three-layer resist according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a method of manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 9 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 10 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 13 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 14 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the three-layer resist according to the second embodiment of the present invention.

FIG. 15 is a sectional view showing a method for manufacturing a semiconductor device having a Y-shaped cross-section gate electrode using a three-layer resist according to a second embodiment of the present invention.

FIG. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 17 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 18 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 19 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 21 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 22 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 27 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 28 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 29 is a cross-sectional view showing the method for manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 30 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 31 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 32 is a cross-sectional view showing the method of manufacturing the semiconductor device having the Y-shaped cross-section gate electrode using the four-layer resist according to the fourth embodiment of the present invention.

FIG. 33 is a cross-sectional view showing the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1, 20 semiconductor substrate, 2, 3, 5, 5A, 11 resist, 6 cross-section Y-shaped gate electrode, 7 gate pad electrode, 8 source electrode, 9 drain electrode.

Claims (12)

[Claims] 1. A semiconductor substrate, a source electrode and a drain electrode provided on the semiconductor substrate, and a gate electrode located between the source electrode and the drain electrode, wherein the gate electrode has a reverse step type side cross-sectional shape. A semiconductor device characterized in that 2. The gate electrode is provided on a semiconductor substrate and has a support portion having a first width, and an upper portion provided on the support portion and having a second width wider than the first width. ,
It is provided between the support part and the upper part, and is composed of an intermediate part having a width wider than the first width and narrower than the second width, and the support part and the intermediate part are combined. Height 0.4 μm
A semiconductor device, characterized in that: 3. The support section is provided coaxially with the upper section.
3. The semiconductor device according to claim 1. 4. The support portion is provided eccentrically with respect to the upper portion.
3. The semiconductor device according to claim 1. 5. A support portion provided on a semiconductor substrate and having a first width, and an upper portion provided on the support portion and having a second width wider than the first width, the support portion and the above. Manufacture of a semiconductor device provided with a gate electrode having an inverted step type side cross-sectional shape, which is provided between the upper part and an intermediate part having a width wider than the first width and narrower than the second width. A step of applying a first resist on the entire surface of the semiconductor substrate, and a second resist having a higher sensitivity than the first resist and a developing solution different from that of the first resist, A step of applying on the first resist, and a step of exposing a region of the second resist where the gate electrode is to be formed with a width wider than the first width and narrower than the second width. , Exposing the above through the second resist A step of exposing the first resist in the region formed with the first width, and developing only the second resist to form the second resist in the exposed portion. A step of removing and forming a second resist removal pattern on the first resist, and a third resist which can be developed with a developing solution of the first resist, on the second resist and A step of applying on the first resist in the removal pattern, a step of exposing the third resist with the second width, and developing the third resist and the first resist. The step of removing the third resist and the first resist in the exposed portion to form a punching pattern of the reverse step type side sectional shape, and the step of removing the reverse step type side sectional shape. Gate electrode in pattern A semiconductor device comprising: a step of vapor-depositing a metal to form the gate electrode; and a step of removing the first, second and third resists in the non-exposed portion. Production method. 6. A support portion provided on a semiconductor substrate and having a first width, an upper portion provided on the support portion and having a second width wider than the first width, and the support portion. The support portion is provided between the upper portion and the intermediate portion having a width wider than the first width and narrower than the second width, and the support portion is eccentrically provided with respect to the upper portion. A method of manufacturing a semiconductor device having a gate electrode having a reverse step type side cross-sectional shape, the method including applying a first resist to the entire surface of the semiconductor substrate, and lower sensitivity than the first resist. Then, a step of applying a second resist having a different developing solution from the first resist on the first resist, and a second resist having a higher sensitivity than the second resist and having a different developing solution from the second resist. Third resist on the second resist above A step of applying, and a step of exposing the third resist and the first resist to a region where the gate electrode is to be formed with a width wider than the first width and narrower than the second width, A step of exposing the second resist through the third resist with the first width by offsetting the area where the gate electrode is to be formed, and exposing the third resist; Developing only the second resist to remove the third resist in the exposed portion, and forming a third resist relief pattern on the second resist; and developing the second resist. A step of applying a fourth resist which can be developed with a liquid on the third resist and the second resist in the punching pattern, and exposing the fourth resist with the second width The step of performing The resist, the second resist and the first resist are developed to remove the exposed fourth resist, the second resist and the first resist, and the reverse step type And a step of forming a gate electrode metal in the reverse step type side cross-sectional shape punching pattern to form the gate electrode, and the exposure is not performed. And a step of removing the first, second, third, and fourth resists of a part. 7. A source electrode and a drain electrode provided on a semiconductor substrate, a support portion provided on the semiconductor substrate and having a first width,
An upper portion provided on the support portion and having a second width wider than the first width, and provided between the support portion and the upper portion, wider than the first width and larger than the second width. A method of manufacturing a semiconductor device, comprising a gate electrode having a reverse step type side cross-sectional shape composed of an intermediate portion having a narrow width, wherein a first resist is applied to the entire surface of the semiconductor substrate. A step of applying a second resist having a higher sensitivity than the first resist and a developing solution different from that of the first resist onto the first resist, and forming a gate electrode of the second resist. Exposing the area to be formed with a width wider than the first width and narrower than the second width, and forming the source electrode and the drain electrode of the first resist and the second resist Perform exposure on the area A step of developing only the second resist, removing the second resist in the exposed portion, and forming a second resist blank pattern on the first resist; A step of applying a third resist which can be developed with a developing solution of the first resist on the second resist and the first resist in the blank pattern, and the source of the third resist. A step of exposing the regions where the electrodes and the drain electrode are to be formed, and developing the third resist and the first resist to expose the exposed portions of the first resist and the third resist. A step of removing the resist to form a blank pattern in the regions where the source and drain electrodes are to be formed; The same as the above-mentioned third resist, the step of vapor-depositing the metal for the electrode and the drain electrode to form the above-mentioned source electrode and drain electrode, the step of removing the above-mentioned third resist in the unexposed portion. A step of applying a fourth resist of material on the source electrode, the drain electrode, the second resist and the first resist, and exposing the fourth resist with the second width. Steps to be carried out, developing the fourth resist and the first resist, removing the first resist and the fourth resist of the exposed portion, the side cross-sectional shape of the reverse step type A step of forming a punching pattern, a step of depositing a metal for a gate electrode in the punching pattern of the side cross-sectional shape of the reverse step type to form the gate electrode, and a portion which is not exposed. And a step of removing the above first, second and fourth resists. 8. A source electrode and a drain electrode provided on a semiconductor substrate, a support portion provided on the semiconductor substrate and having a first width, and a support portion provided on the support portion and having a width greater than the first width. Inverse step type having an upper portion having a wider second width and an intermediate portion provided between the supporting portion and the upper portion and having a width wider than the first width and narrower than the second width. A method of manufacturing a semiconductor device having a gate electrode having a side cross-sectional shape, the method comprising: applying a first resist to the entire surface of the semiconductor substrate; A step of applying a second resist having a different developing solution from the first resist on the first resist, and a third resist having a higher sensitivity than the second resist and having a different developing solution from the second resist On the second resist above And a step of exposing the area where the gate electrode is to be formed with a width wider than the first width and narrower than the second width with an exposure amount that the third resist and the first resist are exposed. A step of exposing the second resist through the third resist with the first width to an area where the gate electrode is to be formed by offsetting the exposure; And exposing the first resist and the second resist to the regions where the source electrode and the drain electrode are to be formed with an exposure amount that the resist and the first resist are exposed, and the third resist Developing only the second resist to remove the third resist in the exposed portion, and forming a third resist relief pattern on the second resist; and developing the second resist. Present with liquid A step of applying a fourth resist on the third resist and on the second resist in the blank pattern, and for the regions where the source and drain electrodes of the fourth resist are to be formed And exposing, and developing the fourth resist, the second resist and the first resist, the exposed portion of the fourth resist, the second resist and the second resist. A step of removing one resist to form a blank pattern in the regions where the source electrode and the drain electrode are to be formed; and a metal for the source electrode and the drain electrode in the blank pattern in the regions where the source electrode and the drain electrode are to be formed. Vapor-depositing to form the source electrode and the drain electrode, and removing the fourth resist in the unexposed portion, Applying a fifth resist of the same material as the fourth resist on the source electrode, the drain electrode, the second resist and the third resist, and the fifth resist with respect to the fifth resist. A step of performing exposure with two widths, developing the fifth resist, the second resist and the first resist, and exposing the exposed portion of the fifth resist, the second resist And a step of removing the first resist to form a reverse step type side cross-section punching pattern, and depositing a metal for a gate electrode in the reverse step type side cross-section punching pattern to form the gate. A method of manufacturing a semiconductor device, comprising: a step of forming an electrode; and a step of removing the first, second, third and fifth resists in a portion which is not exposed. 9. The first resist and the second resist are applied so that the total layer thickness of the first resist and the second resist is 0.4 μm. Item 8. A method of manufacturing a semiconductor device according to Item 5 or 7. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first resist and the second resist are made of materials that do not mix with each other. 11. The combined layer thickness of the first resist, the second resist and the third resist is 0.4 μm.
9. The method of manufacturing a semiconductor device according to claim 6, wherein the first resist, the second resist, and the third resist are applied so that the thickness becomes m. 12. The first resist and the second resist are made of materials that do not mix with each other, and the second resist and the third resist are made of materials that do not mix with each other. The method of manufacturing a semiconductor device according to claim 11, wherein