JPS6177370A - Pattern formation - Google Patents
Pattern formationInfo
- Publication number
- JPS6177370A JPS6177370A JP19880484A JP19880484A JPS6177370A JP S6177370 A JPS6177370 A JP S6177370A JP 19880484 A JP19880484 A JP 19880484A JP 19880484 A JP19880484 A JP 19880484A JP S6177370 A JPS6177370 A JP S6177370A
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- gate
- irradiation
- resist
- amount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007261 regionalization Effects 0.000 title claims 2
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000010894 electron beam technology Methods 0.000 claims abstract description 14
- 239000007769 metal material Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000035945 sensitivity Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 7
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はパターン形成方法、例えば高周波電界効果半導
体装置の低抵抗微細ゲートの形成において、レジストを
２層構造にし、電子ビーム露光による補助露光を加えて
広範囲寸法の断面Ｔ字型の′ゲートをリフトオフ法によ
る作る方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a pattern forming method, for example, in the formation of a low-resistance fine gate for a high frequency field effect semiconductor device, the resist is made into a two-layer structure and auxiliary exposure by electron beam exposure is performed. In addition, the present invention relates to a method of making gates having a T-shaped cross section with a wide range of dimensions by a lift-off method.
ガリウム砒素（ＧａＡｓ） 、高電子移動トランジスタ
（ＯＥＭＴ）等の高周波ＦＥＴにおいては、特性向上の
ため特にゲート電極が短いゲート長のものであり、かつ
、低抵抗のものであることが要求され、そのため番こ断
面Ｔ字型のゲート形成技術の研究がなされている。In high-frequency FETs such as gallium arsenide (GaAs) and high electron mobility transistors (OEMTs), gate electrodes are particularly required to have short gate lengths and low resistance in order to improve characteristics. Research is being carried out on techniques for forming gates with a T-shaped cross section.
第１図（ｂｌに本発明実施例が断面図で示されるが、図
示の実施例を参照すると、２はノンドープＧａＡｓ゛バ
ッファ層、３はｎ−ＧａＡｓ活性層、１０はゲートリセ
ス、１２はゲート、１３はソース電極、１４はドレイン
電極をそれぞれ示す。活性層３を電流は図に見て左右の
横方向に流れ、それを止める（電流を制限する）ゲート
１２の活性Ｎ３と接続している部分の電流の流れ方向の
長さが小であるほど良い特性が得られる。前記したゲー
ト長とはゲートの電流の流れる方向の長さをいうもので
ある。An embodiment of the present invention is shown in cross-sectional view in FIG. Reference numeral 13 indicates a source electrode, and reference numeral 14 indicates a drain electrode.A current flows horizontally in the left and right directions in the active layer 3, and this is stopped (limits the current) at a portion connected to the active N3 of the gate 12. The smaller the length of the gate in the direction of current flow, the better the characteristics can be obtained.The gate length mentioned above refers to the length of the gate in the direction of current flow.
前記した如くゲート長を小にするとゲートの抵抗は大に
なる。ゲート長を小にする一方でゲート抵抗を小にする
ためにゲートの断面積を大にする、という互いに相反す
る要求を満足するために開発されたものが図示のＴ字型
断面のゲートである。As described above, when the gate length is made small, the gate resistance becomes large. The T-shaped cross-sectional gate shown in the figure was developed to satisfy the contradictory requirements of increasing the cross-sectional area of the gate in order to reduce the gate length and reduce the gate resistance. .
かかるＴ字型断面のゲートを作る方法として、従来２Ｎ
レジスト、３層レジスト構造が用いられているが、ゲー
ト長０．１５μｍに対し、Ｔ字型ゲートの上部寸法は０
．６μｍ程度の寸法にしか形成されず、この上部寸法を
より大になし得るゲートの形成方法が求められている。As a method of making such a gate with a T-shaped cross section, the conventional 2N
A three-layer resist structure is used, but the gate length is 0.15 μm, and the upper dimension of the T-shaped gate is 0.
．． There is a need for a method for forming a gate that can be formed to a size of only about 6 μm and that can make the upper size larger.
他方、金属層を中間層として現像レベルを変化させてＴ
字型断面のゲートを形成する方法も提案されているが、
この方法ではプロセスの工程数が多くなるという問題が
ある。On the other hand, by using a metal layer as an intermediate layer and changing the development level, T
A method of forming a gate with a letter-shaped cross section has also been proposed;
This method has a problem in that the number of process steps increases.
本発明は上記問題点を解決し断面Ｔ字型のゲートを、半
導体装置の活性領域表接触する部分の長さくゲートの下
部寸法）は従来よりも小に、またゲートの上部寸法は従
来のものよりも大に形成する方法を提供するもので、そ
の手段は、基板上に断面Ｔ字型電極を形成する方法にし
て、前記基板上に順に下層レジスト膜と該下層レジスト
膜よりも感度の大なる上層レジスト膜を形成し、電子ビ
ームの照射量を変更することにより、上層レジスト膜と
下層レジスト膜に前記電極の上部寸法と下部寸法番こそ
れぞれ対応する開口を形成し、これら開口を通して電極
メタル材料を蒸着し、リフトオフ法により電極以外のメ
タル材料を除去することを特徴とするパターン形成方法
によって達成される。The present invention solves the above problems and provides a gate with a T-shaped cross section.The length of the part that contacts the active region surface of a semiconductor device (the lower dimension of the gate) is smaller than that of the conventional one, and the upper dimension of the gate is smaller than that of the conventional one. The present invention provides a method of forming a T-shaped cross-section electrode on a substrate, and sequentially forming a lower resist film and a T-shaped electrode having a higher sensitivity than the lower resist film on the substrate. By forming an upper resist film and changing the amount of electron beam irradiation, openings corresponding to the upper and lower dimensions of the electrode are formed in the upper resist film and the lower resist film, and the electrode metal is passed through these openings. This is achieved by a pattern forming method characterized by depositing a material and removing metal material other than the electrodes by a lift-off method.
上記方法においては、低抵抗微細ゲート長のＴ字型断面
のゲートを作るために、レジストを２Ｎ構造のものとし
、上層のレジストは高感度のものとし、下層のレジスト
は上層のレジストよりは低感度のものとし、電子ビーム
露光によるゲートパターン露光にＥＢの補助露光を加え
、上層レジストのパターンは大なる寸法に形成し、ゲー
ト形成金属の蒸着、リフトオフの工程によってＴ字型断
面ゲートの上部寸法を大にするものである。In the above method, in order to create a gate with a T-shaped cross section with a small gate length and low resistance, the resist has a 2N structure, the upper layer resist is of high sensitivity, and the lower layer resist is lower than the upper layer resist. By adding EB auxiliary exposure to the gate pattern exposure using electron beam exposure, the pattern of the upper resist layer is formed to a large size, and the upper size of the T-shaped cross-section gate is adjusted by vapor deposition of gate forming metal and lift-off process. It is something that increases the.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明の方法によって形成されるＴ字型断面のゲートは
第１図ｆａｔとそのＢ−Ｂ線に沿う断面図である同図ｆ
ｂｌに示され、その各部は前記に説明した如くである。A gate with a T-shaped cross section formed by the method of the present invention is shown in FIG.
bl, and its parts are as described above.
図示の例で、ゲートの下部寸法、すなわちゲートの活性
層３に接する部分の長さＬｂと上部寸法Ｌｕは、Ｌｂ＝
０．１〜０．５ ／ｊ ｍに対してＬｕを１．５〜２
．５μｍに形成可能であることが確認された。次に、か
かるゲートを形成する方法を第２図の断面図と線図を参
照して説明する。In the illustrated example, the lower dimension of the gate, that is, the length Lb of the portion of the gate in contact with the active layer 3 and the upper dimension Lu, are Lb=
0.1-0.5 /j Lu 1.5-2 for m
．． It was confirmed that it could be formed to a thickness of 5 μm. Next, a method for forming such a gate will be explained with reference to the cross-sectional view and line diagram of FIG.
第２図ｆａｔに示される如く、半絶縁性ＧａＡｓ基板１
」―に順にノンドープＧａＡｓバッファ層２、ｎ−Ｇａ
Ａｓ活性層３ （ｎ ＝ Ｉ ＸＩＯ”〜２ Ｘ １０
”／ ｃｍ３）をエピタキシャル成長し、更に順にレ
ジストＣＭＲ（ＣＭＲは特開昭５４−６６８２９号に開
示のレジスト）の膜厚０．１〜０．６μｍの下層レジス
ト膜４、レジストＥＢｌ？−９（ＥＢＲ−９は東し株式
会社製のレジストの商品名）の上層レジスト膜５ （膜
厚０．６〜２．０μｍ）を塗布形成する。As shown in FIG. 2, a semi-insulating GaAs substrate 1
” - non-doped GaAs buffer layer 2, n-Ga
As active layer 3 (n = IXIO"~2X10
"/cm3) is epitaxially grown, and then a lower resist film 4 of resist CMR (CMR is the resist disclosed in JP-A-54-66829) with a thickness of 0.1 to 0.6 μm, and resist EBL-9 (EBR) are grown in order. An upper resist film 5 (film thickness: 0.6 to 2.0 μm) (9 is the trade name of a resist manufactured by Toshi Co., Ltd.) is formed by coating.
次に、これらのレジスト膜に第２図ｆｂｌの線図に示さ
れる照射量の電子ビームを照射する。なお、この線図に
おいて、横軸は上層レジスト膜５上の位置、縦軸は照射
量、強度を示し、７で示される照射量Ｄａは上層レジス
ト膜５のみを露光する補助露光、６で示される照射量Ｄ
Ｏは下層レジスト膜を露光する露光の照射量をそれぞれ
表す。かかる露光は、電子ビームの露光条件を変えるこ
とによってなされ、例えばパターンデータに従って、Ｄ
ａ７の部分はある速度で走査して照射量を数μＣ／ＣＷ
１２〜数１０μＣ／Ｃｍ２ とし、Ｄｏ６の部分は前記
速度よりもより遅い速度で走査して照射量を０．５ｎＣ
／ ｃｍ２〜５ ｎＣ／ ｃｍ２にすることによってな
しうる。Next, these resist films are irradiated with an electron beam at a dose shown in the diagram of FIG. 2 fbl. In this diagram, the horizontal axis shows the position on the upper resist film 5, and the vertical axis shows the irradiation amount and intensity. irradiation amount D
O each represents the exposure dose for exposing the lower resist film. Such exposure is performed by changing the exposure conditions of the electron beam, for example, according to the pattern data, D
The part a7 is scanned at a certain speed and the irradiation amount is several μC/CW.
12 to several tens of μC/Cm2, and the Do6 part was scanned at a slower speed than the above speed to reduce the irradiation amount to 0.5 nC.
/ cm2 to 5 nC/cm2.
メチルイソブチルケトン（ＭＩＢＫ）とイソプロピルア
ルコール（ＩＰＡ）の混合液でレジスト膜を現像すると
第２図（Ｃ１に示されるパターンが得られる。When the resist film is developed with a mixed solution of methyl isobutyl ketone (MIBK) and isopropyl alcohol (IPA), a pattern shown in FIG. 2 (C1) is obtained.
同図に符号８で示す範囲はＤａ７で示した電子ビーム露
光によって得られたレジスト膜５の開口、符号９で示す
範囲はＤｏ６で示した電子ビーム露光によって得られた
レジスト膜４の開口である。なお、第２図（Ｃ１以下に
おいてＧａＡｓ基板１は省略しである。In the figure, the range indicated by reference numeral 8 is the opening of the resist film 5 obtained by the electron beam exposure indicated by Da7, and the range indicated by reference numeral 9 is the opening of the resist film 4 obtained by the electron beam exposure indicated by Do6. . Note that the GaAs substrate 1 is omitted from FIG. 2 (C1 and below).
次に、第２図ｆｄｌに示される如く、開口９のレジスト
膜をマスクにしてウェットエツチングでゲートリセス１
０を形成する。このゲートリセスは、活性層３を流れる
電流を遮断しうるに適する厚さの活性層を残すように形
成する。次いで、 Ａ７！、Ｔｉ。Next, as shown in FIG.
form 0. This gate recess is formed to leave the active layer with a thickness suitable for blocking the current flowing through the active layer 3. Next, A7! , Ti.
ｐｔまたはＡｕの如きゲートメタル材料１１を蒸着する
。A gate metal material 11, such as PT or Au, is deposited.
次に、リフトオフによってレジスト膜４．５を除去しレ
ジスト膜５の上のゲートメタル材料１１を除去すると、
第２図ｆａ）に示されるゲート１２が得られる。Next, when the resist film 4.5 is removed by lift-off and the gate metal material 11 on the resist film 5 is removed,
A gate 12 as shown in FIG. 2 fa) is obtained.
最後にソース電極１３、ドレイン電極１４を通常の技術
で形成して第１図に示されるＧａＡｓ ＭＥＳ ＦＥＴ
を完成する。Finally, a source electrode 13 and a drain electrode 14 are formed using conventional techniques to form the GaAs MES FET shown in FIG.
complete.
Ｔ字型断面ゲート１２において、前記の如（上部寸法を
Ｌｕ、下部寸法（ゲート長）をＬｂとし、第２図ｆｂ）
に示される低照射量部分の一方の長さく照射幅）をｌａ
とし、更に前述の如く６で示すゲート弄光の照射量をＤ
ｏ、７で示す補助露光の照射量をＤａとしたとき、本発
明者の実施した実験の結果を第３図の線図に示す。なお
、第３図において、横軸には照射量をｎＣ７ｃｍで示し
、縦軸にはＬｂ＋ Ｌｕをμｍで示し、実線曲線はゲー
ト１２の上部寸法、点線曲線はゲート１２の下部寸法を
表示する。In the T-shaped cross-sectional gate 12, as described above (the upper dimension is Lu and the lower dimension (gate length) is Lb, Fig. 2 fb).
The length and irradiation width of one of the low irradiation portions shown in
Furthermore, as mentioned above, the irradiation amount of the gate light shown by 6 is D.
The results of the experiment carried out by the present inventor are shown in the diagram of FIG. 3, where Da is the irradiation amount of the auxiliary exposure shown by o, 7. In FIG. 3, the horizontal axis shows the irradiation dose in nC7cm, the vertical axis shows Lb+Lu in μm, the solid line curve shows the upper dimension of the gate 12, and the dotted line curve shows the lower dimension of the gate 12.
曲線ＡはＡ！ａ ＝１．０ ｐｔｎ ％ Ｄａ＝１５．
ｃ＋ｃ ７０ｍ２、曲線ＢはＲａ ＝０．５１１ｍ 、
、 Ｄａ＝１５μＣ７０ｍ２、曲線Ｃは１ａ−０、Ｄａ
＝ Ｏのときを、また曲線りはｌ ａ −１’、Ｏμｍ
、 Ｄａ＝１５μＣ７０ｍ２、曲線Ｅはｊ！ａ ＝０
．５ μｍ、Ｄａ＝、１５＃’Ｃ７０ｍ２、曲線Ｆは１
１ａ ＝Ｏ１Ｄａ＝０のときの結果を表す。従来、上部
寸法は０．６μｍ、下部寸法は０．１５μｍが限度であ
ったものが、同図の示す如く、上部寸法は１．５〜２．
５μｍに、また下部寸法は０．１〜０．５μｍの範囲に
形成可能であり、例えばＬｂを０．１μｍにしてＬｕを
１μｍ以上にしうろことが確認された。このことは、従
来に比べてゲート長を短かくし、ゲート抵抗をゲート長
が１μｍ台のときの低い値になしうろこと、例えばゲー
ト抵抗を２５倍程度に下げうろことを示すものである。Curve A is A! a = 1.0 ptn % Da = 15.
c+c 70m2, curve B is Ra = 0.511m,
, Da=15μC70m2, curve C is 1a-0, Da
= O, and the curve is l a -1', Oμm
, Da=15μC70m2, curve E is j! a = 0
．． 5 μm, Da=, 15#'C70m2, curve F is 1
The results are shown when 1a=O1Da=0. Conventionally, the upper dimension was limited to 0.6 μm and the lower dimension to 0.15 μm, but as shown in the figure, the upper dimension was limited to 1.5 to 2.5 μm.
It was confirmed that it is possible to form the lower part with a diameter of 5 μm and a lower dimension in the range of 0.1 to 0.5 μm, for example, Lb can be set to 0.1 μm and Lu can be set to 1 μm or more. This indicates that it is possible to shorten the gate length and reduce the gate resistance to a value as low as when the gate length is on the order of 1 μm, for example, to reduce the gate resistance by about 25 times.
以上説明したように本発明によれば、レジスト膜を２層
構造にし、上層レジスト膜を下層レジスト膜よりも感度
の大なるものとし、パターンデータに従い電子ビーム照
射の照射量を適宜変更することにより、上層レジスト膜
にはゲートの上部寸法に対応する大なる寸法の開口を、
また下層レジスミ−膜にはゲート長（ゲートの下部寸法
）に対応する小なる寸法の開口を形成し、これら開口を
通してゲートメタル材料を蒸着し、不要部分はリフトオ
フにより取り去ることにより、従来例より小なるゲート
長で、従来例より大なる上部寸法（このことはゲート抵
抗の減少につながる）のＴ字型断面ゲートが形成される
ので、特性に優れたＧａＡｓＭＥＳ ＦＥＴなどの製造
に有効である１、As explained above, according to the present invention, the resist film has a two-layer structure, the upper resist film has higher sensitivity than the lower resist film, and the dose of electron beam irradiation is appropriately changed according to the pattern data. , an opening with large dimensions corresponding to the upper dimension of the gate is formed in the upper resist film.
In addition, by forming an opening with a small size corresponding to the gate length (lower dimension of the gate) in the lower resistive film, depositing the gate metal material through these openings, and removing unnecessary parts by lift-off, the structure is made smaller than the conventional example. With a gate length of
第１図（ａｌと（ｂｌは本発明方法によって形成される
ＧａＡｓ ＭＦ、Ｓ ＦＥＴの平面図と断面図、第２図
＋ａｌ 、 ＋８） 。
（ｄｉ 、 （８１は本発明の方法を実施する工程にお
ける半導体装置要部の断面図、第２図（ｂｌは第２図（
ｅ）のパターンを得る電子ビームの照射量を示す線図、
第３図は本発明の方法における電子ビームの照射量とゲ
〒トの上部寸法および下部寸法との関係を示す線図であ
る。
図中、１は半絶縁性ＧａＡｓ基板、２はノンドープＧａ
Ａｓバッファ層、３はｎ−ＧａＡｓ活性層、４は下層レ
ジスト膜、５は上層レジスト膜、６はゲートパターン電
子ビーム露光を示す線、７は電子ビーム補助露光を示す
線、８は上層レジスト膜の開口、９は下層レジスト膜の
開口、１０はゲートリセス、１１はゲートメタル材料、
１２はゲート、１３はソース電極、１４はドレイン電極
、をそれぞれ示す。
第１図
１″）
第２図
第２図
第３図Figure 1 (al and (bl) are a plan view and cross-sectional view of GaAs MF, S FET formed by the method of the present invention, Figure 2 +al, +8). (di, (81 is a step of carrying out the method of the present invention) A cross-sectional view of the main part of a semiconductor device in FIG. 2 (bl is in FIG. 2 (
A diagram showing the irradiation amount of the electron beam to obtain the pattern e),
FIG. 3 is a diagram showing the relationship between the electron beam irradiation amount and the upper and lower dimensions of the gate in the method of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped Ga
As buffer layer, 3 is n-GaAs active layer, 4 is lower resist film, 5 is upper resist film, 6 is a line indicating gate pattern electron beam exposure, 7 is a line indicating electron beam auxiliary exposure, 8 is upper resist film 9 is an opening in the lower resist film, 10 is a gate recess, 11 is a gate metal material,
12 represents a gate, 13 represents a source electrode, and 14 represents a drain electrode. Figure 1 1'') Figure 2 Figure 2 Figure 3
Claims (1)
基板上に順に下層レジスト膜と該下層レジスト膜よりも
感度の大なる上層レジスト膜を形成し、電子ビームの照
射量を変更することにより、上層レジスト膜と下層レジ
スト膜に前記電極の上部寸法と下部寸法にそれぞれ対応
する開口を形成し、これら開口を通して電極メタル材料
を蒸着し、リフトオフ法により電極以外のメタル材料を
除去することを特徴とするパターン形成方法。A method of forming a cross-sectional T-shaped electrode on a substrate, forming a lower resist film and an upper resist film having higher sensitivity than the lower resist film in order on the substrate, and changing the amount of electron beam irradiation. By forming openings corresponding to the upper and lower dimensions of the electrode in the upper resist film and the lower resist film, respectively, depositing the electrode metal material through these openings, and removing the metal material other than the electrode by a lift-off method. Characteristic pattern formation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198804A JPH0630361B2 (en) | 1984-09-21 | 1984-09-21 | Pattern formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198804A JPH0630361B2 (en) | 1984-09-21 | 1984-09-21 | Pattern formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6177370A true JPS6177370A (en) | 1986-04-19 |
| JPH0630361B2 JPH0630361B2 (en) | 1994-04-20 |
Family
ID=16397187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59198804A Expired - Lifetime JPH0630361B2 (en) | 1984-09-21 | 1984-09-21 | Pattern formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0630361B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02299245A (en) * | 1989-05-15 | 1990-12-11 | Rohm Co Ltd | Manufacture of field-effect transistor |
| JPH03185739A (en) * | 1989-12-01 | 1991-08-13 | Hughes Aircraft Co | Self-aligning t gate hemt |
| JPH03283434A (en) * | 1990-03-29 | 1991-12-13 | Sharp Corp | Formation of electrode |
| US5391899A (en) * | 1991-10-29 | 1995-02-21 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor device with a particular gate structure |
| JPH07335671A (en) * | 1994-06-13 | 1995-12-22 | Nec Corp | Manufacture of t-type gate electrode |
| JPH08186128A (en) * | 1994-12-19 | 1996-07-16 | Korea Electron Telecommun | Gate formation of field-effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105326A (en) * | 1979-02-07 | 1980-08-12 | Matsushita Electronics Corp | Manufacturing method of electrode of semiconductor device |
| JPS5623783A (en) * | 1979-08-01 | 1981-03-06 | Matsushita Electronics Corp | Formation of electrode for semiconductor device |
| JPS57183037A (en) * | 1981-05-06 | 1982-11-11 | Nec Corp | Formation of pattern |
-
1984
- 1984-09-21 JP JP59198804A patent/JPH0630361B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105326A (en) * | 1979-02-07 | 1980-08-12 | Matsushita Electronics Corp | Manufacturing method of electrode of semiconductor device |
| JPS5623783A (en) * | 1979-08-01 | 1981-03-06 | Matsushita Electronics Corp | Formation of electrode for semiconductor device |
| JPS57183037A (en) * | 1981-05-06 | 1982-11-11 | Nec Corp | Formation of pattern |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02299245A (en) * | 1989-05-15 | 1990-12-11 | Rohm Co Ltd | Manufacture of field-effect transistor |
| JPH03185739A (en) * | 1989-12-01 | 1991-08-13 | Hughes Aircraft Co | Self-aligning t gate hemt |
| JPH03283434A (en) * | 1990-03-29 | 1991-12-13 | Sharp Corp | Formation of electrode |
| US5391899A (en) * | 1991-10-29 | 1995-02-21 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor device with a particular gate structure |
| JPH07335671A (en) * | 1994-06-13 | 1995-12-22 | Nec Corp | Manufacture of t-type gate electrode |
| JPH08186128A (en) * | 1994-12-19 | 1996-07-16 | Korea Electron Telecommun | Gate formation of field-effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0630361B2 (en) | 1994-04-20 |
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