JPH0630361B2 - Pattern formation method - Google Patents
Pattern formation methodInfo
- Publication number
- JPH0630361B2 JPH0630361B2 JP59198804A JP19880484A JPH0630361B2 JP H0630361 B2 JPH0630361 B2 JP H0630361B2 JP 59198804 A JP59198804 A JP 59198804A JP 19880484 A JP19880484 A JP 19880484A JP H0630361 B2 JPH0630361 B2 JP H0630361B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- resist film
- resist
- electron beam
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 23
- 230000007261 regionalization Effects 0.000 title 1
- 238000010894 electron beam technology Methods 0.000 claims description 15
- 239000007769 metal material Substances 0.000 claims description 8
- 230000035945 sensitivity Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- UIHCLUNTQKBZGK-UHFFFAOYSA-N Methyl isobutyl ketone Natural products CCC(C)C(C)=O UIHCLUNTQKBZGK-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はパターン形成方法、例えば高周波電界効果半導
体装置の低抵抗微細ゲートの形成において、レジストを
２層構造にし、電子ビーム露光による補助露光を加えて
広範囲寸法の断面Ｔ字型のゲートをリフトオフ法による
作る方法に関する。The present invention relates to a pattern forming method, for example, in the formation of a low resistance fine gate of a high frequency field effect semiconductor device, the resist is made into a two-layer structure and auxiliary exposure by electron beam exposure is performed. In addition, the present invention relates to a method of forming a T-shaped gate having a wide range of dimensions by a lift-off method.
ガリウム砒素(GaAs)、高電子移動トランジスタ(HEMT)等
の高周波FETにおいては、特性向上のため特にゲート電
極が短いゲート長のものであり、かつ、低抵抗のもので
あることが要求され、そのために断面Ｔ字型のゲート形
成技術の研究がなされている。In high-frequency FETs such as gallium arsenide (GaAs) and high electron mobility transistors (HEMT), the gate electrode is required to have a short gate length and low resistance in order to improve the characteristics. Research on gate formation technology with a T-shaped cross section has been conducted.
第１図(b)に本発明実施例が断面図で示されるが、図示
の実施例を参照すると、２はノンドープGaAsバッファ
層、３はn-GaAs活性層、10はゲートリセス、12はゲー
ト、13はソース電極、14はドレイン電極をそれぞれ示
す。活性層３を電流は図に見て左右の横方向に流れ、そ
れを止める（電流を制限する）ゲート12の活性層３と接
続している部分の電流の流れ方向の長さが小であるほど
良い特性が得られる。前記したゲート長とはゲートの電
流の流れる方向の長さをいうものである。FIG. 1 (b) is a sectional view showing an embodiment of the present invention. Referring to the illustrated embodiment, 2 is a non-doped GaAs buffer layer, 3 is an n-GaAs active layer, 10 is a gate recess, 12 is a gate, Reference numeral 13 is a source electrode, and 14 is a drain electrode. A current flows through the active layer 3 in the left and right lateral directions as viewed in the figure, and stops it (limits the current). The length of the portion of the gate 12 connected to the active layer 3 in the current flow direction is small. Good characteristics are obtained. The above-mentioned gate length refers to the length of the gate in the direction of current flow.
前記した如くゲート長を小にするとゲートの抵抗は大に
なる。ゲート長を小にする一方でゲート抵抗を小にする
ためにゲートの断面積を大にする、という互いに相反す
る要求を満足するために開発されたものが図示のＴ字型
断面のゲートである。As described above, when the gate length is reduced, the gate resistance increases. The gate having a T-shaped cross section shown in FIG. 1 has been developed to meet the contradictory requirements of increasing the cross-sectional area of the gate in order to reduce the gate resistance while reducing the gate length. .
かかるＴ字型断面のゲートを作る方法として、従来２層
レジスト、３層レジスト構造が用いられているが、ゲー
ト長0.15μｍに対し、Ｔ字型ゲートの上部寸法は0.6μ
ｍ程度の寸法にしか形成されず、この上部寸法をより大
になし得るゲートの形成方法が求められている。Conventionally, a two-layer resist and a three-layer resist structure have been used as a method of forming a gate having such a T-shaped cross section, but the upper dimension of the T-shaped gate is 0.6 μ for a gate length of 0.15 μm.
There is a demand for a method of forming a gate which can be formed only to a size of about m and can make the upper size larger.
他方、金属層を中間層として現像レベルを変化させてＴ
字型断面のゲートを形成する方法も提案されているが、
この方法ではプロセスの工程数が多くなるという問題が
ある。On the other hand, by using the metal layer as an intermediate layer and changing the development level, T
Although a method of forming a gate having a V-shaped cross section has been proposed,
This method has a problem that the number of process steps increases.
そしてこの問題点は、基板上に断面Ｔ字型電極を形成す
る方法にして、前記基板上に順に下層レジスト膜と該下
層レジスト膜よりも感度の大なる上層レジスト膜を形成
し、上層レジスト膜のみ露光し、下層レジスト膜を露光
しない照射量による電子ビーム露光と、下層レジスト膜
を露光する電子ビーム露光を実行することにより、上層
レジスト膜と下層レジスト膜に前記電極の上部寸法と下
部寸法にそれぞれ対応する開口を形成し、これら開口を
通して電極メタル材料を蒸着し、リフトオフ法により電
極以外のメタル材料を除去することを特徴とするパター
ン形成方法に関するもの提供することによって解決され
る。This problem is that a method of forming a T-shaped electrode in cross section on a substrate is used to form a lower layer resist film and an upper layer resist film having a greater sensitivity than the lower layer resist film on the substrate in order. By performing electron beam exposure with a dose that only exposes the lower resist film and does not expose the lower resist film, and electron beam exposure that exposes the lower resist film, the upper and lower dimensions of the electrode are adjusted to the upper and lower resist films. The problem is solved by providing a pattern forming method characterized by forming corresponding openings, depositing an electrode metal material through these openings, and removing the metal material other than the electrodes by a lift-off method.
上記方法においては、低抵抗微細ゲート長のＴ字型断面
のゲートを作るために、レジストを２層構造のものと
し、上層のレジストは高感度のものとし、下層のレジス
トは上層のレジストよりは低感度のものとし、電子ビー
ム露光によるゲートパターン露光にEBの補助露光を加
え、上層レジストのパターンは大なる寸法に形成し、ゲ
ート形成金属の蒸着、リフトオフの工程によってＴ字型
断面ゲートの上部寸法を大にするものである。In the above method, in order to form a gate having a T-shaped cross section with a low resistance fine gate length, the resist has a two-layer structure, the upper layer resist has high sensitivity, and the lower layer resist has a higher sensitivity than the upper layer resist. Low sensitivity, electron beam exposure gate pattern exposure with EB auxiliary exposure, upper resist pattern is formed to a large size, and gate formation metal vapor deposition and lift-off process is performed on top of T-shaped cross-section gate. The size is increased.
以下、図面を参照して本発明の実施例を詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
本発明の方法によって形成されるＴ字型断面のゲートは
第１図(a)とそのＢ−Ｂ線に沿う断面図である同図(b)に
示され、その各部は前記に説明した如くである。図示の
例で、ゲートの下部寸法、すなわちゲートの活性層３に
接する部分の長さLbと上部寸法Luは、Lb＝0.1〜0.5μｍ
に対してLuを1.5〜2.5μｍに形成可能であることが確認
された。次に、かかるゲートを形成する方法を第２図の
断面図と線図を参照して説明する。A gate having a T-shaped cross section formed by the method of the present invention is shown in FIG. 1 (a) and its sectional view taken along line BB (b), and each part thereof is as described above. Is. In the illustrated example, the lower dimension of the gate, that is, the length Lb of the portion of the gate in contact with the active layer 3 and the upper dimension Lu is Lb = 0.1 to 0.5 μm.
On the other hand, it was confirmed that Lu can be formed to have a thickness of 1.5 to 2.5 μm. Next, a method for forming such a gate will be described with reference to the sectional view and the diagram of FIG.
第２図(a)に示される如く、半絶縁性GaAs基板１上に順
にノンドープGaAsバッファ層２、n-GaAs活性層３（ｎ＝
１×１０17〜２×１０18／cm3）をエピタキシャル成長
し、更に順にレジストCMR（CMRは特開昭54-66829号に開
示のレジスト）の膜厚0.1〜0.6μｍの下層レジスト膜
４、レジストEBR-9（EBR-9は東レ株式会社製のレジスト
の商品名）の上層レジスト膜５（膜厚0.6〜2.0μｍ）を
塗布形成する。As shown in FIG. 2 (a), a non-doped GaAs buffer layer 2 and an n-GaAs active layer 3 (n =
1 × 10 17 to 2 × 10 18 / cm 3 ) is epitaxially grown, and a resist CMR (CMR is a resist disclosed in JP-A-54-66829) having a film thickness of 0.1 to 0.6 μm, a lower resist film 4 and a resist. An upper layer resist film 5 (film thickness 0.6 to 2.0 μm) of EBR-9 (EBR-9 is a trade name of a resist manufactured by Toray Industries, Inc.) is formed by coating.
次に、これらのレジスト膜に第２図(b)の線図に示され
る照射量の電子ビームを照射する。なお、この線図にお
いて、横軸は上層レジスト膜５上の位置、縦軸は照射
量、強度を示し、７で示される照射量Daは上層レジスト
膜５のみを露光する補助露光、６で示される照射量Doは
下層レジスト膜を露光する露光の照射量をそれぞれ表
す。かかる露光は、電子ビームの露光条件を変えること
によってなされ、例えばパターンデータに従って、Da７
の部分はある速度で走査して照射量を数μＣ／cm2〜数1
0μＣ／cm2とし、Do６の部分は前記速度よりもより遅い
速度で走査して照射量を0.5nC／cm2〜５nC／cm2にする
ことによってなしうる。Next, these resist films are irradiated with the electron beam having the dose shown in the diagram of FIG. 2 (b). In this diagram, the horizontal axis represents the position on the upper layer resist film 5, the vertical axis represents the dose and intensity, and the dose Da indicated by 7 is auxiliary exposure for exposing only the upper layer resist film 5, and 6 The dose Do given is the dose of exposure for exposing the lower resist film. Such exposure is performed by changing the exposure conditions of the electron beam, and for example, according to the pattern data, Da7
Is scanned at a certain speed and the irradiation dose is several μC / cm 2 to several 1
And 0μC / cm 2, portions of the Do6 may without by the irradiation amount is scanned at a slower rate than the rate of 0.5nC / cm 2 ~5nC / cm 2 .
メチルイソブチルケトン(MIBK)とイソプロピルアルコー
ル(IPA)の混合液でレジスト膜を現像すると第２図(c)に
示されるパターンが得られる。同図に符号８で示す範囲
はDa７で示した電子ビーム露光によって得られたレジス
ト膜５の開口、符号９で示す範囲はDo６で示した電子ビ
ーム露光によって得られたレジスト膜４の開口である。
なお、第２図(c)以下においてGaAs基板１は省略してあ
る。When the resist film is developed with a mixed solution of methyl isobutyl ketone (MIBK) and isopropyl alcohol (IPA), the pattern shown in FIG. 2 (c) is obtained. In the figure, the range indicated by reference numeral 8 is the opening of the resist film 5 obtained by the electron beam exposure shown by Da7, and the range shown by the reference numeral 9 is the opening of the resist film 4 obtained by the electron beam exposure shown by Do6. .
The GaAs substrate 1 is omitted in FIG. 2 (c) and subsequent figures.
次に、第２図(d)に示される如く、開口９のレジスト膜
をマスクにしてウエットエッチングでゲートリセス10を
形成する。このゲートリセスは、活性層３を流れる電流
を遮断しうるに適する厚さの活性層を残すように形成す
る。次いで、Ａ，Ti，PtまたはAuの如きゲートメタル
材料11を蒸着する。Next, as shown in FIG. 2D, a gate recess 10 is formed by wet etching using the resist film in the opening 9 as a mask. This gate recess is formed so as to leave an active layer having a thickness suitable for blocking the current flowing through the active layer 3. A gate metal material 11 such as A, Ti, Pt or Au is then deposited.
次に、リフトオフによってレジスト膜４，５を除去しレ
ジスト膜５の上のゲートメタル材料11を除去すると、第
２図(e)に示されるゲート12が得られる。Next, the resist films 4 and 5 are removed by lift-off and the gate metal material 11 on the resist film 5 is removed to obtain the gate 12 shown in FIG. 2 (e).
最後にソース電極13、ドレイン電極14を通常の技術で形
成して第１図に示されるGaAs MES FETを完成する。Finally, the source electrode 13 and the drain electrode 14 are formed by a usual technique to complete the GaAs MES FET shown in FIG.
Ｔ字型断面ゲート12において、前記の如く上部寸法をL
u、下部寸法（ゲート長）をLbとし、第２図(b)に示され
る低照射量部分の一方の長さ（照射幅）をａとし、更
に前述の如く６で示すゲート露光の照射量をDo、７で示
す補助露光の照射量をDaとしたとき、本発明者の実施し
た実験の結果を第３図の線図に示す。なお、第３図にお
いて、横軸には照射量をnC／cmで示し、縦軸にはLb，Lu
をμｍで示し、実線曲線はゲート12の上部寸法、点線曲
線はゲート12の下部寸法を表示する。In the T-shaped cross-section gate 12, the upper dimension is L as described above.
u, the lower dimension (gate length) is Lb, one length (irradiation width) of the low irradiation amount portion shown in FIG. 2 (b) is a, and the irradiation amount of the gate exposure shown in 6 as described above. The results of the experiment conducted by the present inventor are shown in the diagram of FIG. In FIG. 3, the horizontal axis represents the irradiation dose in nC / cm, and the vertical axis represents Lb and Lu.
In μm, the solid curve represents the upper dimension of the gate 12, and the dotted curve represents the lower dimension of the gate 12.
曲線Ａはａ＝1.0μｍ、Da＝15μＣ／cm2、曲線Ｂは
ａ＝0.5μｍ、Da＝15μＣ／cm2、曲線Ｃはａ＝０、Da
＝０のときを、また曲線Ｄはａ＝1.0μｍ、Da＝15μ
Ｃ／cm2、曲線Ｅはａ＝0.5μｍ、Da＝15μＣ／cm2、
曲線Ｆはａ＝０、Da＝０のときの結果を表す。従来、
上部寸法は0.6μｍ、下部寸法は0.15μｍが限度であっ
たものが、同図の示す如く、上部寸法は1.5〜2.5μｍ
に、また下部寸法は0.1〜0.5μｍの範囲に形成可能であ
り、例えばLbを0.1μｍにしてLuを１μｍ以上にしうる
ことが確認された。このことは、従来に比べてゲート長
を短かくし、ゲート抵抗をゲート長が１μｍ台のときの
低い値になしうること、例えばゲート抵抗を25倍程度に
下げうることを示すものである。Curve A has a = 1.0 μm, Da = 15 μC / cm 2 , curve B has a = 0.5 μm, Da = 15 μC / cm 2 , curve C has a = 0, Da.
= 0, and curve D has a = 1.0 μm and Da = 15 μm.
C / cm 2 , curve E has a = 0.5 μm, Da = 15 μC / cm 2 ,
Curve F represents the result when a = 0 and Da = 0. Conventionally,
The upper dimension was limited to 0.6 μm and the lower dimension was limited to 0.15 μm, but as shown in the figure, the upper dimension is 1.5 to 2.5 μm.
It was also confirmed that the lower dimension can be formed in the range of 0.1 to 0.5 μm, for example, Lb can be 0.1 μm and Lu can be 1 μm or more. This means that the gate length can be shortened as compared with the conventional one, and the gate resistance can be set to a low value when the gate length is on the order of 1 μm, for example, the gate resistance can be reduced to about 25 times.
以上説明したように本発明によれば、レジスト膜を２層
構造にし、上層レジスト膜を下層レジスト膜よりも感度
の大なるものとし、パターンデータに従い電子ビーム照
射の照射量を適宜変更することにより、上層レジスト膜
にはゲートの上部寸法に対応する大なる寸法の開口を、
また下層レジスト膜にはゲート長（ゲートの下部寸法）
に対応する小なる寸法の開口を形成し、これら開口を通
してゲートメタル材料を蒸着し、不要部分はリフトオフ
により取り去ることにより、従来例より小なるゲート長
で、従来例より大なる上部寸法（このことはゲート抵抗
の減少につながる）のＴ字型断面ゲートが形成されるの
で、特性に優れたGaAs MES FETなどの製造に有効であ
る。As described above, according to the present invention, the resist film has a two-layer structure, the upper resist film has higher sensitivity than the lower resist film, and the irradiation amount of electron beam irradiation is appropriately changed according to the pattern data. , The upper resist film has a large size opening corresponding to the upper size of the gate,
In addition, the lower resist film has a gate length (dimension below the gate)
By forming openings of small size corresponding to the above, vapor-depositing the gate metal material through these openings, and removing unnecessary parts by lift-off, the gate length is smaller than the conventional example and the upper size larger than the conventional example. Is effective for manufacturing GaAs MES FETs having excellent characteristics.
第１図(a)と(b)は本発明方法によって形成されるGaAs M
ES FETの平面図と断面図、第２図(a)，(c)，(d)，(e)は
本発明の方法を実施する工程における半導体装置要部の
断面図、第２図(b)は第２図(c)のパターンを得る電子ビ
ームの照射量を示す線図、第３図は本発明の方法におけ
る電子ビームの照射量とゲートの上部寸法および下部寸
法との関係を示す線図である。 図中、１は半絶縁性GaAs基板、２はノンドープGaAsバッ
ファ層、３はn-GaAs活性層、４は下層レジスト層、５は
上層レジスト層、６はゲートパターン電子ビーム露光を
示す線、７は電子ビーム補助露光を示す線、８は上層レ
ジスト膜の開口、９は下層レジスト膜の開口、10はゲー
トリセス、11はゲートメタル材料、12はゲート、13はソ
ース電極、14はドレイン電極、をそれぞれ示す。1 (a) and 1 (b) show GaAs M formed by the method of the present invention.
A plan view and a cross-sectional view of the ES FET, FIGS. 2 (a), (c), (d), and (e) are cross-sectional views of the main part of the semiconductor device in the steps of carrying out the method of the present invention, and FIG. ) Is a diagram showing the dose of the electron beam for obtaining the pattern of FIG. 2 (c), and FIG. 3 is a line showing the relation between the dose of the electron beam and the upper and lower dimensions of the gate in the method of the present invention. It is a figure. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs buffer layer, 3 is an n-GaAs active layer, 4 is a lower resist layer, 5 is an upper resist layer, 6 is a line showing a gate pattern electron beam exposure, 7 Is a line indicating electron beam auxiliary exposure, 8 is an opening in the upper resist film, 9 is an opening in the lower resist film, 10 is a gate recess, 11 is a gate metal material, 12 is a gate, 13 is a source electrode, 14 is a drain electrode. Shown respectively.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/812 (72)発明者 石割 秀敏 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 山本 純生 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 昭55−105326（ＪＰ，Ａ) 特開 昭57−183037（ＪＰ，Ａ) 特開 昭56−23783（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical indication location H01L 29/812 (72) Inventor Hidetoshi Ishiwari 1015 Uedoda, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Sumio Yamamoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP-A-55-105326 (JP, A) JP-A-57-183037 (JP, A) JP 56-23783 (JP, A)
Claims (1)
して、 前記基板上に順に下層レジスト膜と該下層レジスト膜よ
りも感度の大なる上層レジスト膜を形成し、上層レジス
ト膜のみ露光し、下層レジスト膜を露光しない照射量に
よる電子ビーム露光と、下層レジスト膜露光する電子ビ
ーム露光を実行することにより、上層レジスト膜と下層
レジスト膜に前記電極の上部寸法と下部寸法にそれぞれ
対応する開口を形成し、これら開口を通して電極メタル
材料を蒸着し、リフトオフ法により電極以外のメタル材
料を除去することを特徴とするパターン形成方法。1. A method of forming a T-shaped electrode in cross section on a substrate, wherein a lower layer resist film and an upper layer resist film having a higher sensitivity than the lower layer resist film are sequentially formed on the substrate, and only the upper layer resist film is formed. Corresponds to the upper and lower dimensions of the electrode for the upper resist film and the lower resist film by performing electron beam exposure with an exposure amount that exposes and does not expose the lower resist film, and electron beam exposure that exposes the lower resist film. A pattern forming method is characterized in that the openings are formed, the electrode metal material is vapor-deposited through the openings, and the metal material other than the electrodes is removed by a lift-off method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198804A JPH0630361B2 (en) | 1984-09-21 | 1984-09-21 | Pattern formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198804A JPH0630361B2 (en) | 1984-09-21 | 1984-09-21 | Pattern formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6177370A JPS6177370A (en) | 1986-04-19 |
| JPH0630361B2 true JPH0630361B2 (en) | 1994-04-20 |
Family
ID=16397187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59198804A Expired - Lifetime JPH0630361B2 (en) | 1984-09-21 | 1984-09-21 | Pattern formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0630361B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2550412B2 (en) * | 1989-05-15 | 1996-11-06 | ローム株式会社 | Method for manufacturing field effect transistor |
| US5053348A (en) * | 1989-12-01 | 1991-10-01 | Hughes Aircraft Company | Fabrication of self-aligned, t-gate hemt |
| JP2736154B2 (en) * | 1990-03-29 | 1998-04-02 | シャープ株式会社 | Electrode fabrication method |
| JP2735718B2 (en) * | 1991-10-29 | 1998-04-02 | 三菱電機株式会社 | Compound semiconductor device and method of manufacturing the same |
| JP2626558B2 (en) * | 1994-06-13 | 1997-07-02 | 日本電気株式会社 | Manufacturing method of T-type gate electrode |
| JP2746539B2 (en) * | 1994-12-19 | 1998-05-06 | 韓國電子通信研究院 | Method for forming gate of field effect transistor and method for forming region for forming gate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55105326A (en) * | 1979-02-07 | 1980-08-12 | Matsushita Electronics Corp | Manufacturing method of electrode of semiconductor device |
| JPS5623783A (en) * | 1979-08-01 | 1981-03-06 | Matsushita Electronics Corp | Formation of electrode for semiconductor device |
| JPS57183037A (en) * | 1981-05-06 | 1982-11-11 | Nec Corp | Formation of pattern |
-
1984
- 1984-09-21 JP JP59198804A patent/JPH0630361B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6177370A (en) | 1986-04-19 |
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