JPS6267654A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To transfer data which are outputted by the 1st storage device at the same time to the 2nd storage device synchronously at any time by providing a temporary storage device whose storage time or number of storage stages is determined according to respective transfer modes between the 1st and the 2nd storage devices. CONSTITUTION:When the clock period of a transfer mode is, for example, 50ns, the output data of the 1st storage device 102 are inputted to the 1st buffer 203 in the temporary storage device 104 a specific time later, set in the buffer 201 with the 2nd clock, and then inputted to a selecting circuit 203. Then, a signal which is delayed by a specific time under the control of the flag signal of a flag setting circuit 105 is stored in the 2nd storage device 203 through the 2nd buffer 202 after being delayed by three clocks in this case. The output data of the 1st storage device 10 are also sent to and set in a device 103 after being delayed by three clocks. Consequently, the output signal of the devices 101 and 102 are stored in the device 103 synchronously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a plurality of first storage means in which related data are stored, and a second storage means for storing the outputs of these first storage means. The present invention relates to a data transfer circuit that simultaneously outputs related data stored in the first storage means and transfers it to the second storage means.

[Conventional technology]

Conventionally, this type of data transfer circuit has a first storage means 1 in which related data is stored, for example, as shown in FIG.
01 and 102, and a second storage means in which the outputs of the first storage means 101 and 102 are stored via signal lines 11 and 12, respectively.

Now, suppose that the signal line 11 requires a transfer time of 90 ns, and the signal line requires a transfer time of 70 ns, and if this data transfer circuit is operated in the transfer mode 1 with a clock cycle of 50 ns, for example. , first storage means 101, 10
The two output data of No. 2 are stored in the second storage means 103 in one clock, and are stored simultaneously with a delay of two clocks. However, when operating in the second transfer mode with a clock cycle of 80 ns, the output data of the first storage means 101 is stored in the second storage means 103 every clock as in the first transfer mode. However, it is stored with a delay of 2 clocks. On the other hand, the output data of the first storage means 102 is stored in the second storage means 103 with the clock [unlike in the first transfer mode].

[Problem that the invention attempts to solve]

In the conventional data transfer circuit described above, in the first transfer mode, the output data of the seventh storage means +01 and the output data of the first storage means 102 are input to the second storage means 103 in synchronization. However, the second transfer mode has the drawback that synchronization cannot be achieved.

[Means for Solving the Problems] The data transfer circuit of the present invention includes a transfer mode instruction means in which information indicating one of a plurality of transfer modes with different clock synchronization is set, and a first storage means. and the second storage means by canceling out the difference in the transfer time of the signal line between the first storage means and the second storage means.
In order to synchronize the output of the storage means with the second storage means, the output of the first storage means is connected to the signal line of the first storage means and the second storage means with a transfer time of 1. of,
The present invention is characterized by comprising temporary storage means for temporarily storing the stored data for a predetermined time according to the transfer mode indicated by the information set in the transfer mode instruction means and outputting the temporarily stored data to the second storage means.

Therefore, all data output from the first storage means is always synchronously transferred to the second storage means, regardless of the transfer mode.
input into the storage means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the data transfer circuit of the present invention (in the case where there are two first storage means), and FIG.
Block diagram of temporary storage means 104 in the figure, M3 diagram, Sumire 4
The figure is a time chart of signals of each section in the first and second transfer modes, respectively, in this embodiment.

The output of the storage means 101 of the father-in-law 1 and the input of the second storage means +03 are connected by a signal line 12, and the output of the first storage means 102 is inputted to the temporary storage means +04 via the signal line 12. After the temporary storage means 104 holds the output of the first storage means 102 for a period determined by the transfer mode specifying the flag signal 14 of the flag setting means 105,
It is output to the second storage means 103.

Now, assume that the time required for data transfer on signal lines I+, +2, and 13 is 120 ns, 40 ns, and 30 ns, respectively, and that the clock cycle of the first transfer mode is 50 ns and the clock cycle of the second transfer mode is 100 ns.

The temporary storage means 104, as shown in FIG. buffer 20)
The output of the selection means 203 and the input of the second buffer 202 are connected by signal lines 21 and 22, respectively. When the flag signal 14 indicates the first transfer mode, the selection means 203 selects and outputs the output of the first buffer 201 and selects the flag signal 1.
4 or the second transfer mode, signal line 12
Select and output.

Now, assume that the times required for data transfer on the signal lines 21 and 22 are Ions and 1 Ons, respectively.

Next, the operation of this embodiment will be explained with reference to the time charts of FIGS. 3 and 4.

In the case of (+) Ml transfer mode (FIG. 3), the first storage means +01 outputs data signals Ao and At every clock as shown in FIG. 3(A).

△7+Aj+... is output, and the first storage means 102
As shown in Figure CB), the data signals Bo, Bl, 87, B:4, . . . are generated every clock.
is output. The output data of the storage means 102 of the cup 1 is 4
After 0 ns, as shown in the same figure (C), the first buffer 2
01, and as shown in FIG. 2D, it is set in the first buffer 201 at the second cross, and is input to the selection means 203 after Ions. The output of the selection means 203 is input to the second buffer 202 after lof'ls from the input of the data selection means 203, as shown in FIG. The data is visually set in the second buffer 202 and output to the second storage means 103. The output of the second buffer 202 is shown in FIG.
As shown, the signal is input to the second storage means 103 with a delay of 30 ns, and is set in the second storage means 103 at the fourth clock. That is, it is stored in the second storage means 103 with a delay of three clocks. On the other hand, as shown in the same figure (H),
The output data of the first storage means 101 is input to the second storage means 103 with a delay of 120 ns, and is also stored in the second storage means 103 with a delay of 3 clocks. That is, the output data of the first storage means 101 and the first storage means 10
The second output data is stored in the second storage means 103 in synchronization with a delay of three clocks.

(2) In the case of the second transfer mode (Fig. 4) In this case, the clock period is 100ns, and the first storage means +01
data signals Ao, A+, .

817... is output. The output of the first storage means 102 is output to the selection means 20 after 40 ns as shown in FIG.
3 and is selectively output by the selection means 203.

The output of the selection means 203 is 50n as shown in FIG.
It is input to the second buffer 202 with a delay of
As shown in FIG. 3, the data is set in the second buffer 202 at the second clock and input to the second storage means 103. The output of the second buffer 202 is 30 as shown in FIG.
It is input to the second storage means 103 with a delay of ns, and is stored in the third storage means 103 at the third clock. That is,
The data is stored in the second storage means 103 with a delay of two clocks.

On the other hand, as shown in FIG. 3H, the output data of the first storage means 101 is input to the second storage means 103 with a delay of 120 ns, and is stored in the second storage means 103 at the third time. That is, the output data of the storage means 101 of the cup 1 and the output data of the first storage means 102 are both stored in the second storage means 103 in synchronization with a delay of two clocks.

Note that (D) in the figure is data stored in the first buffer 201, but it is not selected by the selection means 203 and becomes invalid.

In this embodiment, there are two first storage means, but three
The present invention can be similarly applied to the case of more than one.

(Effects of the Invention) As explained above, the present invention provides temporary storage means with a fixed storage time or number of storage stages depending on each transfer mode between the first storage means and the second storage means. Another advantage is that the simultaneously outputted data of the first storage means can always be synchronously input to the second storage means in the tank number transfer mode.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the data transfer circuit of the present invention, FIG. 2 is a block diagram of the temporary storage means 104 in FIG. 1, and FIG. FIG. 4 is a time chart showing signals of each part in the transfer mode, FIG. 4 is a time chart showing signals of each part in the second transfer mode of the embodiment of FIG. 1, and FIG. 5 is a block diagram showing a conventional example of a data transfer circuit. be. +1.12.13.21.22. ...Signal line, 14
...Flag signal, 101, 102...First storage means, 103...
2nd storage means, 104... Temporary storage means, 105... Flag setting means, 20+... First buffer, 202... Second buffer, 203... Selection means.

Claims (1)

[Scope of Claims] Comprising a plurality of first storage means in which related data is stored, and a second storage means for storing outputs of these first storage means, the data is stored in the first storage means. The data transfer circuit simultaneously outputs related data and transfers them to the second storage means, the data transfer circuit comprising: a transfer mode instruction means in which information indicating one of a plurality of transfer modes having different clock periods is set; By canceling the difference in signal line transfer time between each of the storage means and the second storage means, the output of the first storage means is transferred to the second storage means.
In order to synchronize the input to the storage means, the output of the first storage means is set to the transfer mode instruction means on the signal line of the first storage means and the second storage means, which have a short transfer time. 1. A data transfer circuit comprising temporary storage means for temporarily storing the stored information for a predetermined time according to a transfer mode indicated by the information, and outputting the temporarily stored information to the second storage means.