JPS626703Y2 - - Google Patents
Info
- Publication number
- JPS626703Y2 JPS626703Y2 JP1604779U JP1604779U JPS626703Y2 JP S626703 Y2 JPS626703 Y2 JP S626703Y2 JP 1604779 U JP1604779 U JP 1604779U JP 1604779 U JP1604779 U JP 1604779U JP S626703 Y2 JPS626703 Y2 JP S626703Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistors
- unit
- resistance
- accuracy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置に関するものであり、特に
不純物拡散技術と写真蝕刻技術を用いた集積回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an integrated circuit using impurity diffusion technology and photoetching technology.
近年、集積回路は製造技術の長足の進歩と回路
設計技術の発達により、さまざまな応用分野へと
浸透し続けている。集積回路において、不純物拡
散技術と写真蝕刻技術を利用して同一基板上に構
成される能動素子(例えばトランジスタ,ダイオ
ード等)や受動素子(例えば抵抗,コンデンサ
等)の性能と限界および製造誤差分布等の理解が
深まるにつれ、これらの素子を用いた回路設計技
術も発達し続けている。このような動向は、従来
集積回路の応用分野として考えられなかつた分野
へと集積回路が利用され始めていることからもう
かがえる。 In recent years, integrated circuits have continued to penetrate into various application fields due to rapid advances in manufacturing technology and developments in circuit design technology. In integrated circuits, the performance, limits, and manufacturing error distribution of active elements (e.g., transistors, diodes, etc.) and passive elements (e.g., resistors, capacitors, etc.) that are constructed on the same substrate using impurity diffusion technology and photolithography technology. As understanding of these elements deepens, circuit design techniques using these devices continue to develop. This trend can be seen in the fact that integrated circuits are beginning to be used in fields that were previously unthinkable as applications for integrated circuits.
一般に、不純物拡散技術と写真蝕刻技術を使用
した抵抗については、よく知られているように抵
抗の絶対精度は製造技術の変動により変化し十数
パーセントにも及ぶことが考えられる。このため
回路設計において抵抗の絶対精度が十数パーセン
トの変動に対しても、必要とされる機能を満足す
るように考慮することが必要とされる。 In general, as for resistors using impurity diffusion technology and photoetching technology, the absolute accuracy of the resistor varies due to variations in manufacturing technology, and is thought to vary by as much as ten or more percent, as is well known. Therefore, in circuit design, it is necessary to take into account even if the absolute accuracy of the resistance varies by more than ten percent, so that the required functions are satisfied.
しかしながら、集積回路素子として使用される
抵抗は同一基板上に互に近接して製造されるた
め、抵抗間の比精度を数パーセント以下にするこ
とは比較的容易に可能である。更に、抵抗間の比
精度を改善する方法としては
(1) 抵抗の抵抗幅を広くする。 However, since the resistors used as integrated circuit elements are manufactured close to each other on the same substrate, it is relatively easy to reduce the relative accuracy between the resistors to a few percent or less. Furthermore, methods to improve the relative accuracy between resistors include (1) widening the resistance width of the resistors;
(2) 抵抗と配線導体との接続抵抗を小さくする。(2) Reduce the connection resistance between the resistor and the wiring conductor.
等の対策が一般に考えられる。Measures such as these are generally considered.
第1の対策は、製造工程における写真蝕刻技術
に関係する誤差により生ずる抵抗の抵抗値変動は
抵抗間の比精度を劣化させる原因となる。この対
策として、抵抗の抵抗幅を広くすることにより、
抵抗端面で生ずる写真蝕刻技術に起因する誤差の
抵抗値への影響を少なくする方法である。 The first measure is that fluctuations in the resistance values of the resistors caused by errors related to photolithographic techniques in the manufacturing process cause a deterioration in the relative precision between the resistors. As a countermeasure to this, by widening the resistance range of the resistor,
This is a method for reducing the influence of errors caused by photolithography on the resistor end face on the resistance value.
第2の対策は、抵抗と配線導体との接続抵抗の
抵抗値変動が抵抗間の比精度に影響を与えない値
まで小さくする方法である。 The second measure is to reduce the resistance value fluctuation of the connection resistance between the resistance and the wiring conductor to a value that does not affect the relative accuracy between the resistances.
前記対策は、回路設計において必要とする抵抗
間の比精度を明確にし、集積回路化するに際し、
最適な対策を計るのが一般的手法である。 The above measures clarify the relative accuracy between resistors required in circuit design, and when integrated circuits,
The general method is to determine the optimal countermeasure.
抵抗を用いる特殊な用途、例えば抵抗回路網を
用いて高精度電圧分割回路を構成するとか、抵抗
ラダー回路網を用いて複数個の高精度定電流回路
を構成する等においては、特に抵抗間の比精度に
対し厳しく要求されることがある。 In special applications using resistors, such as constructing a high-precision voltage divider circuit using a resistor network or constructing multiple high-precision constant current circuits using a resistor ladder network, the Strict requirements may be placed on ratio accuracy.
抵抗間の比精度を厳しく要求される抵抗回路網
の集積回路化した例を第1図に示す。第1図は不
純物拡散技術と写真蝕刻技術を用いて抵抗ラダー
回路網を構成した一例である。第1図において、
単位抵抗器1を9個と、単位抵抗器1間の相互接
続をなす配線導体2、および凝似抵抗3を2個用
いて抵抗ラダー回路を構成した例であり、この等
価回路図を第2図に示す。 An example of an integrated circuit of a resistor network, which requires strict ratio accuracy between resistors, is shown in Figure 1. Figure 1 shows an example of a resistor ladder network constructed using impurity diffusion technology and photolithography technology. In Figure 1,
This is an example of a resistor ladder circuit formed using nine unit resistors 1, wiring conductors 2 for interconnecting the unit resistors 1, and two pseudo resistors 3, and the equivalent circuit diagram is shown in FIG.
第1図の集積回路は、抵抗と配線導体間の接続
抵抗に起因する誤差を防ぐため、取り出し方法は
全て同一方法を使用している点や、凝似抵抗3を
挿入して、写真蝕刻技術および不純物拡散技術に
かかわる抵抗間の比精度の劣化を防いでいる一例
である。 The integrated circuit shown in Figure 1 uses the same method for extraction to prevent errors caused by the connection resistance between the resistor and the wiring conductor, and the photo-etching technique This is an example of preventing deterioration in the relative accuracy between resistors involved in impurity diffusion technology.
第2図の等価回路図を実現すべく集積回路化し
た第1図の例では、複数の単位抵抗1で抵抗ラダ
ー回路網を構成しているため、比精度の優れた抵
抗ラダー回路網が実現できる。 In the example shown in Fig. 1, which is an integrated circuit to realize the equivalent circuit diagram shown in Fig. 2, the resistance ladder network is composed of a plurality of unit resistors 1, so a resistance ladder network with excellent ratio accuracy is realized. can.
次に、単位抵抗の抵抗値が異なる2種類の抵抗
ラダー回路網を集積回路化することを考える。こ
のとき、2種類の抵抗ラダー回路網を近接して集
積化するのは良く用いられる手法である。これは
集積回路化するに際し、能動素子および受動素子
間の分離を不純物拡散技術を用いて行うことが必
要であり、素子分離された領域は大きくするほど
集積度が向上するためである。 Next, consider integrating two types of resistor ladder networks with different resistance values of unit resistors. At this time, it is a commonly used technique to integrate two types of resistor ladder networks in close proximity. This is because when creating an integrated circuit, it is necessary to isolate active elements and passive elements using impurity diffusion technology, and the larger the area where the elements are isolated, the higher the degree of integration.
第3図に、2種類の単位抵抗器31および32
を用いた、2種類の抵抗ラダー回路網の一例を示
す(ここでは抵抗の相互配線パターンは略す
る)。凝似抵抗33および34は単位抵抗31お
よび32のそれぞれ間の比精度を保つため1個ず
つ入れてある。なお、第3図において、図面を簡
略にするため抵抗器間の相互接続用配線導体は記
入していないが、第1図の如き配線導体を使用す
るのが一般的である。 In FIG. 3, two types of unit resistors 31 and 32 are shown.
An example of two types of resistor ladder circuit networks using the following is shown (the interconnection patterns of the resistors are omitted here). One piece of the condensed resistors 33 and 34 are provided to maintain the ratio accuracy between the unit resistors 31 and 32, respectively. In FIG. 3, wiring conductors for interconnection between resistors are not shown in order to simplify the drawing, but wiring conductors as shown in FIG. 1 are generally used.
第3図における凝似抵抗33および34を用い
て、それぞれの抵抗ラダー回路網を構成する単位
抵抗器間のそれぞれの比精度を改善した一例であ
るが、このように、凝似抵抗器を2個も使用する
のは集積回路化に際し集積度の劣化をまねき、好
ましくないことは明らかである。 This is an example of improving the ratio accuracy between the unit resistors constituting each resistance ladder network using the condensed resistors 33 and 34 in FIG. It is clear that the use of individual circuits is not preferable because it leads to deterioration of the degree of integration when integrated circuits are fabricated.
本考案は上記欠点を改善し、1個の凝似抵抗を
用いるだけで、それぞれの単位抵抗器間の比精度
を保てる集積回路を提供するものであり、本考案
を用いれば1個の凝似抵抗器を用いるだけで互の
比精度を保つた集積回路が実現できる。 The present invention improves the above-mentioned drawbacks and provides an integrated circuit that can maintain ratio accuracy between each unit resistor by using only one condensed resistor. An integrated circuit that maintains relative accuracy can be realized simply by using resistors.
以下に図面を用いて本考案の実施例を説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第4図は本考案の実施例の説明図である。第4
図は、第1の単位抵抗器41と第2の単位抵抗器
42および凝似抵抗器43により構成した2種類
の抵抗ラダー回路網の説明図である。なお、図を
簡略にするため配線導体を省略してあるのは第3
図と同じである。 FIG. 4 is an explanatory diagram of an embodiment of the present invention. Fourth
The figure is an explanatory diagram of two types of resistance ladder circuit networks constituted by a first unit resistor 41, a second unit resistor 42, and a condensed resistor 43. Note that the wiring conductors are omitted in order to simplify the diagram.
Same as the figure.
本考案の特徴は凝似抵抗器43にあるので、凝
似抵抗器43につき説明する。 Since the feature of the present invention lies in the condensed resistor 43, the condensed resistor 43 will be explained.
凝似抵抗器43は単位抵抗器41および42の
中点で切断し、単位抵抗器41の右半分と、単位
抵抗器42の左半分を接続してなる凝似抵抗器で
あり、単位抵抗器41間の比精度を保つため、単
位抵抗器41側では単位抵抗器41と同一形状と
なり、単位抵抗器42側では単位抵抗器42と同
一形状となつている。このため凝似抵抗器を2個
使用することなく、単位抵抗器41および42の
比精度を保ちながら集積度の向上を計れるのでき
わめて有効である。 The condensing resistor 43 is a condensing resistor which is cut at the midpoint of the unit resistors 41 and 42 and connecting the right half of the unit resistor 41 and the left half of the unit resistor 42. In order to maintain the ratio accuracy between the resistors 41 and 41, the unit resistor 41 side has the same shape as the unit resistor 41, and the unit resistor 42 side has the same shape as the unit resistor 42. Therefore, it is extremely effective because it is possible to improve the degree of integration while maintaining the relative accuracy of the unit resistors 41 and 42 without using two fibrillated resistors.
第1図は従来の集積回路の説明図、第2図は第
1図の等価回路図、第3図は従来の集積回路の説
明図、第4図は本考案の実施例の説明図。
1……抵抗器、2……配線導体、3……凝似抵
抗器、31,32,41,42……単位抵抗器、
33,34,43……凝似抵抗器。
FIG. 1 is an explanatory diagram of a conventional integrated circuit, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIG. 3 is an explanatory diagram of a conventional integrated circuit, and FIG. 4 is an explanatory diagram of an embodiment of the present invention. 1...Resistor, 2...Wiring conductor, 3...Fragmented resistor, 31, 32, 41, 42...Unit resistor,
33, 34, 43... Condensation resistor.
Claims (1)
し、前記第3の抵抗は右に近接する第1の抵抗の
左半分と同一形状とし、左に近接する第2の抵抗
の右半分と同一形状としたことを特徴とする半導
体装置。 A third resistor is provided between the first resistor and the second resistor, the third resistor has the same shape as the left half of the first resistor adjacent to the right, and the second resistor is adjacent to the left. A semiconductor device characterized by having the same shape as the right half of.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1604779U JPS626703Y2 (en) | 1979-02-09 | 1979-02-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1604779U JPS626703Y2 (en) | 1979-02-09 | 1979-02-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55117862U JPS55117862U (en) | 1980-08-20 |
JPS626703Y2 true JPS626703Y2 (en) | 1987-02-16 |
Family
ID=28838847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1604779U Expired JPS626703Y2 (en) | 1979-02-09 | 1979-02-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS626703Y2 (en) |
-
1979
- 1979-02-09 JP JP1604779U patent/JPS626703Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS55117862U (en) | 1980-08-20 |
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