JPS626649B2 - - Google Patents
Info
- Publication number
- JPS626649B2 JPS626649B2 JP55003365A JP336580A JPS626649B2 JP S626649 B2 JPS626649 B2 JP S626649B2 JP 55003365 A JP55003365 A JP 55003365A JP 336580 A JP336580 A JP 336580A JP S626649 B2 JPS626649 B2 JP S626649B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode wiring
- ion
- ion implantation
- implanted
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005468 ion implantation Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 238000000635 electron micrograph Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ion Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係わり、特に
レーザー光を照射して熱処理する工程を含む半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a step of irradiating with laser light and performing heat treatment.
イオン注入法などで半導体に不純物を添加した
後、そのイオン注入中に半導体中に形成された格
子不整を回復させ、結晶格子を整えるために熱処
理が必要であることは良く知られている。従来の
この熱処理には通常の高温の炉が用いられてい
た。然るにこのような炉の中での熱処理では最初
に添加した不純物の電気的な活性化率を必ずしも
100％には到達しないことが知られている。一
方、最近、例えばエイ・ギヤツト等による1978年
発行のアプライド・フイズイツクス・レターズ誌
第32巻の276頁からの論文〔A.Gat、J.F.
Gibbons、T.J.Magee、J.Peng、V.R.Deline、P.
Williams and C.A.Evans、Jr.：“Physical and
Electrical Properties of Laser−Annealed Ion
Implanted Silicon”、Applied Phys.Lett.32、
276（1978）〕でも明らかな通り、単結晶半導体に
不純物をイオン注入し、その半導体上をレーザー
光で照射するとイオン注入損傷層の結晶性が回復
し、しかもその不純物の電気的活性化率も高い事
が報告されている。そのためレーザー熱処理法が
最近検討されるようになつた。しかしこのレーザ
ー熱処理を施すと、半導体表面が荒れ、従つてそ
の後の電極形成時のフオトレジスト工程にてフオ
トレジスト膜にピンホールが形成されやすいとい
う欠点があつた。しかもこの欠点を除去するため
にレジスト膜厚を厚くすると、微細なパターンを
形成し難いという新たな欠点も生じていた。 It is well known that after impurities are added to a semiconductor by ion implantation or the like, heat treatment is necessary to restore the lattice misalignment formed in the semiconductor during the ion implantation and to adjust the crystal lattice. Conventionally, this heat treatment has used an ordinary high temperature furnace. However, in heat treatment in such a furnace, the electrical activation rate of the impurities initially added is not necessarily controlled.
It is known that it will never reach 100%. On the other hand, recently, for example, a paper by A. Gat et al. from page 276 of Volume 32 of Applied Physics Letters published in 1978 [A. Gat, JF
Gibbons, T.J.Magee, J.Peng, VRDeline, P.
Williams and CAEvans, Jr.: “Physical and
Electrical Properties of Laser−Annealed Ion
"Implanted Silicon", Applied Phys. Lett. 32 ,
276 (1978)], when impurity ions are implanted into a single-crystal semiconductor and the semiconductor is irradiated with laser light, the crystallinity of the ion-implanted damaged layer is restored, and the electrical activation rate of the impurity also increases. It has been reported that high For this reason, laser heat treatment methods have recently been studied. However, when this laser heat treatment is applied, the semiconductor surface becomes rough, and therefore pinholes are likely to be formed in the photoresist film in the subsequent photoresist process for electrode formation. Moreover, when the thickness of the resist film is increased in order to eliminate this drawback, a new drawback arises in that it is difficult to form fine patterns.
本発明の目的はレーザー熱処理による不純物の
電気的活性化率が高いという長所を生かしつつ、
かつ電極配線金属を容易に取り付ける技術を提供
することにある。 The purpose of the present invention is to take advantage of the high electrical activation rate of impurities by laser heat treatment, and to
Another object of the present invention is to provide a technique for easily attaching electrode wiring metal.
本発明は、選択的にイオン注入法で不純物を添
加し、該イオン注入領域の少なくとも一部を覆つ
て電極配線金属を付着せしめた後、レーザー光照
射による熱処理を施すことを特徴とする半導体装
置の製造方法である。 The present invention is a semiconductor device characterized in that impurities are selectively added by ion implantation, electrode wiring metal is deposited to cover at least a portion of the ion implanted region, and then heat treatment is performed by laser beam irradiation. This is a manufacturing method.
本発明の原理は適切な電極配線材料を付着せし
め、パターンを形成した後でレーザー光照射によ
る熱処理を行うことにより、結晶性の回復と共に
良好なオーミツク接触抵抗を有する電極配線を持
つ半導体装置が製造できるという発見に基づく。 The principle of the present invention is to deposit an appropriate electrode wiring material, form a pattern, and then perform heat treatment using laser light irradiation to recover crystallinity and produce a semiconductor device with electrode wiring that has good ohmic contact resistance. Based on the discovery that it can be done.
次に本発明の実施例を図面を参照して説明す
る。 Next, embodiments of the present invention will be described with reference to the drawings.
先ず第１図Ａに示したように、例えば４Ω・cm
のｐ型シリコンウエハ１１上に通常の方法で１μ
ｍの二酸化硅素膜１２を形成し、選択的に不純物
を添加する場所の該二酸化硅素膜１２を通常のフ
オトエツチング法で除去して孔１３を形成する。
次いでやはり通常のイオン注入装置を用い、例え
ば31P+イオンを100keVで1015／cm2ほど注入する。
この時残されている二酸化硅素膜１２はイオン注
入のマスクとなり、第１図Ｂのようにイオン注入
領域１４が形成される。この状態ではイオン注入
領域１４はイオン注入時の照射損傷のため格子不
整を生じ、高抵抗であり、電気的には注入された
不純物は不活性である。その後このウエハ上に例
えば、多結晶シリコン１５を約1000Å付着させ、
次いでモリブデン１６を約3000Å付着させて、通
常のフオトエツチング法で不要な部分のモリブデ
ンとその下の多結晶シリコンを除去し、第１図Ｃ
に示すような電極配線パターンを形成する。その
後、例えば波長4880Åのアルゴンイオンレーザー
光を10Wの強度にし、80mmのレンズで絞り、走査
速度３cm／秒走査線幅20μｍにして照射した。こ
の処理を行うと、第１図Ｄに示したように、第１
図Ｃのモリブデン１６と多結晶シリコン１５とが
反応し非化学量論的組成ではあるがモリブデンシ
リサイド１７になる。しかもイオン注入領域１４
の不純物Ｐは電気的に活性となりｎ形領域１８を
形成する。このようにして不純物を添加した領域
に電極を取り付けつつ、かつその不純物の電気的
活性化率をレーザー熱処理により高めることが可
能となる。 First, as shown in Figure 1A, for example, 4Ω・cm
1 μm on a p-type silicon wafer 11 using the usual method.
A silicon dioxide film 12 of m is formed, and holes 13 are formed by removing the silicon dioxide film 12 at locations where impurities are to be selectively added by a conventional photoetching method.
Next, for example, 31 P + ions are implanted at 100 keV and about 10 15 /cm 2 using a conventional ion implantation device.
The silicon dioxide film 12 left at this time serves as a mask for ion implantation, and an ion implantation region 14 is formed as shown in FIG. 1B. In this state, the ion implantation region 14 has a lattice misalignment due to radiation damage during ion implantation, has a high resistance, and the implanted impurity is electrically inactive. After that, for example, about 1000 Å of polycrystalline silicon 15 is deposited on this wafer.
Next, approximately 3000 Å of molybdenum 16 was deposited, and unnecessary portions of molybdenum and the polycrystalline silicon underneath were removed using a normal photoetching method, as shown in Figure 1C.
Form an electrode wiring pattern as shown in . Thereafter, for example, argon ion laser light with a wavelength of 4880 Å was made to have an intensity of 10 W, was focused with an 80 mm lens, and was irradiated with a scanning speed of 3 cm/sec and a scanning line width of 20 μm. When this process is performed, the first
Molybdenum 16 and polycrystalline silicon 15 in Figure C react to form molybdenum silicide 17, although it has a non-stoichiometric composition. Moreover, the ion implantation region 14
The impurity P becomes electrically active and forms an n-type region 18. In this way, it is possible to attach an electrode to a region to which an impurity is added and to increase the electrical activation rate of the impurity by laser heat treatment.
第２図は本発明の効果を示すために、電極材料
を付着せしめる前にレーザー光を照射した時の試
料の断面を模式図的に示したものである。イオン
注入領域はｎ形領域１８′に変つているが、その
表面２１が非常に荒れているため、その上に電極
材料２２を付着せしめてもその凹凸により次に続
くフオトレジスト工程でレジストにピンホールが
生じ易く、電極配線パターン形成時に電極材料に
ピンホール２３が生じたり断線部２４が生じてし
まう。本発明では第１図Ｃの段階ではイオン注入
領域１４の表面はせいぜい格子不整が生じている
のみで、第１図Ｃのように、直接レーザー熱処理
をした場合の第２図に比較して極めて平坦なの
で、このような問題は生じず、かつフオトレジス
ト膜も薄くて済むので微細加工に適する。第３図
Ａ，Ｂは従来技術を示す２つのサンプルのそれぞ
れの電子顕微鏡写真である。すなわちイオン注入
領域（写真の凹部の底面）にレーザ照射した後
に、シリコン膜とこの上のアルミニウム膜からな
る電極配線を形成し場合である。同写真から明ら
かのようにイオン注入領域の表面（写真の凹部の
底面）は平坦となつておらず大きく凹凸している
ことがわかる。尚、同サンプル作成を容易とする
ために電極配線金属はその表面よりエツチングと
し、残つた配線部分（主としてシリコン膜）が白
色で示されている。又、写真の凹部の側面はシリ
コン酸化膜である。 In order to demonstrate the effects of the present invention, FIG. 2 schematically shows a cross section of a sample irradiated with laser light before the electrode material is attached. The ion implantation region has changed to an n-type region 18', but its surface 21 is very rough, so even if electrode material 22 is deposited thereon, the unevenness will cause pins to be attached to the resist in the subsequent photoresist process. Holes are likely to occur, and pinholes 23 or disconnections 24 may occur in the electrode material during electrode wiring pattern formation. In the present invention, at the stage shown in FIG. 1C, the surface of the ion-implanted region 14 has at most lattice misalignment, and as shown in FIG. Since it is flat, such problems do not occur, and the photoresist film can be thin, making it suitable for microfabrication. Figures 3A and 3B are electron micrographs of two samples illustrating the prior art. That is, after irradiating the ion implantation region (the bottom surface of the recess in the photograph) with a laser, an electrode wiring made of a silicon film and an aluminum film on top of the silicon film is formed. As is clear from the photo, the surface of the ion-implanted region (the bottom surface of the recess in the photo) is not flat but has large irregularities. In order to facilitate the preparation of the same sample, the electrode wiring metal was etched from its surface, and the remaining wiring portion (mainly silicon film) is shown in white. Also, the side surface of the recess in the photo is a silicon oxide film.
一方、第４図Ａ，Ｂは第１図に示す実施例の２
つのサンプルのそれぞれの電子顕微鏡写真であ
る。すなわちイオン注入領域（写真の凹部の底
面）にレーザを照射しないで第１図Ｃのように電
極配線金属を設け、しかる後にレーザ照射をした
場合である。同写真から明らかのようにイオン注
入領域の表面（写真の凹部の底面）は平坦となつ
ていることがわかる。尚、同サンプルを作成する
際に電極配線金属であるモリブデンシリサイドを
除去した。しかしこのモリブデンシリサイドはシ
リコン基板表面（イオン注入領域表面）と反応を
おこしているので全部は除去せず薄く残余させ
た。写真において凹部の底面も含めて表面全体が
白色となつているのが薄く残余したモリブデンシ
リサイドである。尚、凹部の側面はシリコン酸化
膜である。 On the other hand, FIGS. 4A and 4B show the second embodiment shown in FIG.
These are electron micrographs of each of the two samples. That is, this is a case where the ion implantation region (the bottom surface of the recess in the photograph) is not irradiated with a laser, but an electrode wiring metal is provided as shown in FIG. 1C, and then the laser irradiation is performed. As is clear from the photo, the surface of the ion-implanted region (the bottom surface of the recess in the photo) is flat. In addition, when creating the same sample, molybdenum silicide, which is the electrode wiring metal, was removed. However, since this molybdenum silicide reacts with the surface of the silicon substrate (the surface of the ion implanted region), not all of it was removed, but a thin layer remained. In the photo, the entire surface, including the bottom of the recess, is white because of the thin remaining molybdenum silicide. Note that the side surfaces of the recessed portions are silicon oxide films.
尚、本実施例では半導体としてシリコン、電極
材料としてモリブデンと多結晶シリコンとの組合
せで説明したがこれは他の半導体、他の配線材料
でもよい。又、本発明では二酸化硅素膜１２に孔
１３を作つて下のシリコン１１を露出してイオン
注入を施したが、これは二酸化硅素膜１２を通し
てイオン注入してもよく、又、絶縁膜も単に二酸
化硅素に限定されるものでもない。 In this embodiment, silicon is used as a semiconductor, and molybdenum and polycrystalline silicon are used as electrode materials in combination, but other semiconductors and other wiring materials may be used. Further, in the present invention, the holes 13 are made in the silicon dioxide film 12 to expose the underlying silicon 11 for ion implantation, but ions may be implanted through the silicon dioxide film 12, or the insulating film may also be simply implanted. Nor is it limited to silicon dioxide.
第１図ＡからＤ迄の図は本発明の典型的な実施
例の工程を順次示す断面図であり、第２図は本発
明の実施例の効果を示すための従来の方法により
作製した試料の断面図であり、第３図は電子顕微
鏡写真によつて示された従来技術の構造をあらわ
す図であり、第４図は電子顕微鏡写真によつて示
された本発明の実施例の構造を示す図である。
尚図に於て、１１…ｐ型シリコン、１２…二酸
化硅素膜、１３…選択的に形成された孔、１４…
イオン注入領域、１５…多結晶シリコン、１６…
モリブデン、１７…非化学量論的組成のモリブデ
ンシリサイド電極配線、１８，１８′…ｎ型領
域、２１…ｎ型領域の表面、２２…電極配線、２
３…ピンホール、２４…断線部分である。
Figures 1A to 1D are cross-sectional views sequentially showing the steps of a typical embodiment of the present invention, and Figure 2 is a sample prepared by a conventional method to demonstrate the effects of the embodiment of the present invention. FIG. 3 is a diagram showing the structure of the prior art shown by an electron micrograph, and FIG. 4 is a diagram showing the structure of the embodiment of the present invention shown by an electron micrograph. FIG. In the figure, 11... p-type silicon, 12... silicon dioxide film, 13... selectively formed holes, 14...
Ion implantation region, 15...polycrystalline silicon, 16...
Molybdenum, 17... Molybdenum silicide electrode wiring with non-stoichiometric composition, 18, 18'... n-type region, 21... Surface of n-type region, 22... electrode wiring, 2
3... Pinhole, 24... Disconnected portion.
Claims (1)
を形成する工程と、前記開孔を通して前記半導体
基板にイオン注入法で選択的に不純物を添加して
イオン注入領域を形成する工程と、前記開孔内に
おいて前記イオン注入領域に付着せる電極配線金
属を形成する工程と、しかる後に前記電極配線金
属上からレーザ光照射による熱処理を施し、該電
極配線金属下の前記イオン注入された不純物を電
気的に活性化する工程とを有することを特徴とす
る半導体装置の製造方法。1. A step of forming an insulating film having an opening on one principal surface of a semiconductor substrate, and a step of selectively adding impurities to the semiconductor substrate through the opening by an ion implantation method to form an ion implantation region. A step of forming an electrode wiring metal to be attached to the ion-implanted region within the opening, and then heat treatment by laser beam irradiation from above the electrode wiring metal to eliminate the ion-implanted impurities under the electrode wiring metal. 1. A method for manufacturing a semiconductor device, comprising the step of electrically activating the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP336580A JPS56100427A (en) | 1980-01-16 | 1980-01-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP336580A JPS56100427A (en) | 1980-01-16 | 1980-01-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56100427A JPS56100427A (en) | 1981-08-12 |
| JPS626649B2 true JPS626649B2 (en) | 1987-02-12 |
Family
ID=11555312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP336580A Granted JPS56100427A (en) | 1980-01-16 | 1980-01-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56100427A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH042361Y2 (en) * | 1987-02-28 | 1992-01-27 | ||
| JPH042360Y2 (en) * | 1987-02-28 | 1992-01-27 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6384024A (en) * | 1986-09-26 | 1988-04-14 | Seiko Epson Corp | Manufacture of semiconductor device |
| JP5187771B2 (en) * | 2009-12-11 | 2013-04-24 | 株式会社日本製鋼所 | Semiconductor substrate manufacturing method and laser annealing apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51130184A (en) * | 1975-05-06 | 1976-11-12 | Matsushita Electric Ind Co Ltd | Semiconductor ic resistance element process |
| JPS5691460A (en) * | 1979-12-25 | 1981-07-24 | Seiko Epson Corp | Manufacturing of dispersion layer resistor |
-
1980
- 1980-01-16 JP JP336580A patent/JPS56100427A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51130184A (en) * | 1975-05-06 | 1976-11-12 | Matsushita Electric Ind Co Ltd | Semiconductor ic resistance element process |
| JPS5691460A (en) * | 1979-12-25 | 1981-07-24 | Seiko Epson Corp | Manufacturing of dispersion layer resistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH042361Y2 (en) * | 1987-02-28 | 1992-01-27 | ||
| JPH042360Y2 (en) * | 1987-02-28 | 1992-01-27 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56100427A (en) | 1981-08-12 |
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