JPS6265518A - Through-current preventing circuit - Google Patents

Abstract

PURPOSE:To prevent the through-current at a push-pull switching output circuit by using a switch means so as to lead a base carrier of an output transistor (TR) to be turned off to a grounding point and using a delayed input signal to apply on/off control to the output TR. CONSTITUTION:Switches 22, 23 to discharge the base carrier are provided between the base of output TRs 17, 19 and a grounding point respectively and delay means 20, 21 to retard an input signal Sin are provided. The switches 22, 23 are subject to on/off control selectively by the input signal Sin so as to discharge the base carrier of a TR in the on-state thereby quickening the off-operation and output TRs 17, 19 are subject to switching control by using the input signal Sin delayed by the delay means 20, 21. Thus, the period when the TRs 17, 19 are turned on simultaneously is avoided.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit formed using a piezoelectric transistor, and the present invention relates to a semiconductor integrated circuit formed using a piezoelectric transistor. Related to current prevention circuit.

[Technical background of the invention and its problems]

Conventionally, the Zossiedel switching output circuit has e.g.
It is configured as shown in the figure. In FIG. 3, an amplifier 12 is connected to an input terminal 11 to which an input signal Sin is supplied.
The input end of is connected. At the output end of this amplifier 12,
The input terminals of amplifiers 13 and 14 are connected to each other, and the output terminal of the amplifier 13 is connected to the base of a PNP Lanzoster 15. The emitter of this transistor 15 is connected to the positive terminal of the DC power supply 16 and the NPN transistor 11.
The collectors of the transistors are connected to each other, and the base of transistor 1f0 is connected to the collector. The above transistor 17
to the emitter of.

The output terminal 18 and the collector of the NPN) runnostar 19 are connected. At the base of the transistor 19,
The output end of the amplifier 14 is connected, and the emitter is connected to a ground point. Then, an output signal S is output from the output terminal 18. It is now possible to obtain ut.

In the above configuration, the input signal 8 is connected to the input terminal 11.
1n is supplied, this signal S1n is sent to the amplifier 12.1.
3 and 12.14:h,) is supplied to the bases of transistors 15 and 19. Now, if the input signal Sin is at a high ("H") level, the transistor 19 is on, the transistors 15 and 17 are off, and the output signal S is generated. ut becomes low ("L") level. On the other hand, if the input signal S1n is at the ``L'' level, the transistors 15 and 11 are on, the transistor 19 is off, and the output signal S.ut is 1.
It becomes H” level.

By the way, when switching from the on state of the transistor 17 to the on state of the transistor 19, or from the on state of the transistor 19 to the on state of the transistor 17, the carriers in the pace of the transistor that was in the on state until then are caused by a characteristic peculiar to semiconductors. Due to causes such as stray capacitance, it does not disappear immediately, but decreases with a predetermined time constant.

Further, the time required for a transistor to change from an off state to an on state is much shorter than the time required for a transistor to change from an on state to an off state. Therefore, as shown in FIG. 4, the pace currents of the transistors 17 and 19 are simultaneously at the "H" level period (to * t+, !! + ts,...)
exists, and both transistors 17 and 19 are in the on state during this period. At this time, a through current flows from the positive electrode of the DC power supply 16 to the ground point via the transistors 17 and 19. This through current is large, and not only does the current consumption of the circuit increase, but the voltage of the power line connected to the DC power supply 16 fluctuates, worsening the leggy ratio, and having an adverse effect on the peripheral circuits. Lotus.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a through-current prevention circuit that can prevent an increase in current consumption and adverse effects on peripheral circuits by preventing through-current in a Zoschesol switching output circuit.

[Summary of the invention]

That is, in this invention, in order to achieve the above object, the output transistor 11.1 in FIG.
A switch for releasing pace carriers is provided between the pace and grounding points of 9, and a manual signal Sln is provided.
A delay means for delaying is provided, and first, the switch is selectively on/off controlled by the input signal Sin to release the pace carriers of the transistor which was in the on state to hasten the off operation, and then the delay means The input signal 81n delayed by the output transistor 17.
Switching of transistors 17 and 19 is controlled so that transistors 17 and 19 are not turned on at the same time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 3 are given the same reference numerals, and detailed explanation thereof will be omitted. That is,
An inverter 20.degree. 21 serving as a delay means is provided between the amplifiers 12 and 13.degree. 14, and the input signal 81n is delayed and supplied to the pace of the transistors 15.19.

Between the bases of the output transistors 17 and 19 and the ground point, the collectors and starters of transistors 22 and 23, which serve as switching means for releasing pace carriers (NPN), are connected, respectively. The output terminal of the amplifier 12 is connected to the base of the transistor 22, and the output terminal of an inverter 24 whose input terminal is connected to the output terminal of the amplifier 7#12 is connected to the base of the transistor 23. Become.

Next, the operation of the above-described configuration will be explained with reference to the tie-on gate shown in FIG.

At time to, the input signal Sim changes from the ``H'' level to the ``L#'' level.
When the level changes, the output of the amplifier 12 turns the transistor 22 off, the output of the amplifier 12 is inverted by the inverter 24, and a good signal turns the transistor 23 on. As a result, the carriers accumulated in the output transistor 19 are led to the ground point, and this transistor 19 is turned off at high speed. Next, at time t1 delayed by the delay time Δt of the inverter 20.21, the "L" level of the input signal Sln changes to the "L" level of the transistor 15.21.
The signal is transmitted to the pace of J9, transistors 15 and 17 are turned on, and transistor 19 is turned off. Therefore,
Output signal S. utFi becomes ``H'' level.When the input signal 131n becomes ``H'' level at time 1, the amplifier 12
The output of the transistor 22 turns on and the transistor 23 turns off. When the transistor 22 is turned on, the pace carriers of the transistor 190 are guided to the ground point, and the transistor 17 is quickly turned off. At time t3, which is delayed by Δt from time 1°, the transistor 15°17
is off, transistor 19 is on, and the output signal S is output. ut becomes "L" level.

At the next time t4, the input signal 81n goes to ``L'' level, the register 23 turns on, and the output transistor 19 is turned off at high speed. Thereafter, the above-described operations are sequentially repeated.

According to such a configuration, the output transistors 17.19
Since the output transistors 17 and 19 simultaneously turn off and then one of the transistors turns on in response to the input signal 81n, there is no period during which the output transistors 17 and 19 turn on at the same time.

Therefore, since through current can be prevented, an increase in current consumption can be prevented, and an adverse effect on peripheral circuits can also be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, by preventing the through current in the Zossy pull switching output circuit, it is possible to obtain a through current prevention circuit that can prevent an increase in current consumption and adverse effects on peripheral circuits.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a through current prevention circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a diagram for explaining a conventional circuit. FIG. 4, which is a diagram showing the Schudel switching output circuit, is a timing chart for explaining the operation of the circuit shown in FIG. 3. 17.19... Output transistor, 22.23...
Transistor (switching means) for pace carrier release
%20.21...Informator (delay means), Sin
...Input signal, 5out...Output signal.

Claims (1)

[Claims] The push-pull switching output circuit is provided between a base of an output transistor and a ground point, and includes a switch means for discharging base carriers of the output transistor, and a delay means for delaying an input signal to the push-pull switching output circuit, By selectively controlling on/off the switch means based on the input signal to lead the base carrier of the output transistor to be turned off to a ground point, and then controlling the output transistor on/off using the delayed input signal. , a through-current prevention circuit characterized by preventing output transistors from turning on at the same time.