JPS6265468A - Display device - Google Patents
Display deviceInfo
- Publication number
- JPS6265468A JPS6265468A JP60204409A JP20440985A JPS6265468A JP S6265468 A JPS6265468 A JP S6265468A JP 60204409 A JP60204409 A JP 60204409A JP 20440985 A JP20440985 A JP 20440985A JP S6265468 A JPS6265468 A JP S6265468A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- line
- gate
- film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052782 aluminium Inorganic materials 0.000 claims abstract 2
- 229910052737 gold Inorganic materials 0.000 claims abstract 2
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract 2
- 229910052697 platinum Inorganic materials 0.000 claims abstract 2
- 239000010408 film Substances 0.000 abstract description 7
- 239000011521 glass Substances 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000002048 anodisation reaction Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の嘱する技術分野〕
本発明はＩｆｆ本ずつの互いに直交するアドレスライン
とデーターラインで構成される表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display device comprising If address lines and data lines that are orthogonal to each other.
近年、多結晶ま九は非晶質半導体薄膜を用いたトランジ
スタアレイを集積形成して液晶駆動回路基板とした液晶
表示装置が注目されている。特に上記半導体薄膜が低温
で形成できることから、ガラス基板を用りることができ
、従って低コスト化が可能であり、ｔｆ：、従来の露光
技術、エツチング技術等のパターン形成法をそのまま適
用して大面積化を容易に図ることができるなどの利点が
注目されている。In recent years, attention has been paid to liquid crystal display devices in which transistor arrays using polycrystalline semiconductor thin films are integrated and a liquid crystal drive circuit board is used. In particular, since the semiconductor thin film mentioned above can be formed at a low temperature, a glass substrate can be used, and therefore costs can be reduced. Advantages such as the ability to easily increase the area are attracting attention.
一般に液晶表示ｖ＆（ｌｔ：ｔ、液晶駆動回路基板に、
液晶駆動用のトランジスタアレイとＸ、Ｙデータライン
がマトリクス状に配置されており、大面積化に伴って表
示セル数が増加し、これに比例して電極数も増加し、ま
た電極長さも増大する。電極ラインが長くなるに比例し
てライン抵抗が高くなり、回路駆動上動作速度があげら
れない等の問題がある。又電極パターン形成時にゴミや
マスクの傷などによシミ極短路や断線が発生する問題が
ある。Generally, liquid crystal display v&(lt:t), liquid crystal drive circuit board,
The transistor array for driving the liquid crystal and the X and Y data lines are arranged in a matrix, and as the area becomes larger, the number of display cells increases, and the number of electrodes increases proportionally, as well as the length of the electrodes. do. The line resistance increases in proportion to the length of the electrode line, and there are problems such as an inability to increase the operating speed of the circuit. In addition, there is a problem in that dirt, scratches on the mask, etc. cause stains, extremely short circuits, and disconnections during electrode pattern formation.
本発明は電極ラインの低抵抗化と電極ラインの断線防止
をはかり１表示品位の向上し比表示装置を提供すること
を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a ratio display device with improved display quality by reducing the resistance of electrode lines and preventing disconnection of the electrode lines.
本発明は、ゲート電極ライン抵抗の低抵抗化と１億ライ
ン断線防止をはかり、第１７１１電極を局部陽極酸化（
ＴＦＴ部とアドレス線との交点）Ｌ、ＮＴＩ膜を用い、
第２層電極に人１ 、Ｍｏ 、Ａｕ 、Ｐｉのいずれか
の金属を組合せる事により電極ラインの低抵抗化するゲ
ート電極二層構造を用いた表示装置を得ることＶＣある
。The present invention aims to reduce the gate electrode line resistance and prevent disconnection of 100 million lines, and the 1711th electrode is locally anodized (
(intersection between TFT section and address line) L, using NTI film,
It is possible to obtain a display device using a two-layer gate electrode structure in which the resistance of the electrode line is reduced by combining any one of metals, Mo, Au, and Pi for the second layer electrode.
本発明によればゲート電極二層構造を用いる事によって
回路駆動動作速度を下げる事なく、又電極ライン断線防
止し、表示品位の高い表示装置を製造する事が出来る。According to the present invention, by using the gate electrode two-layer structure, it is possible to manufacture a display device with high display quality without lowering the circuit drive operation speed and preventing electrode line disconnection.
以下本発明の実施例を第１図及び第２図を参照して説明
する。第１図は本発明の平面図であり。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the present invention.
第２図はｘ −ｘ’での断面図である。FIG. 2 is a cross-sectional view taken along x-x'.
第１図、第２図を製造工程にしたがって説明する。まず
ガラス基板（１）の上に全面Ｔａスパッタ−２５００Ｘ
蒸着し、ホトエツチングを行いゲート電極（２）を作成
する。次にホトレジストを塗布し、ＴＦＴ部とデータラ
イ／と交差する位置のレジストを露光、現像により取シ
除き、陽極酸化（３）、（３’）を行う。さらに全面に
５ｉ０２ｆ［（４）を３０００λ堆積する。1 and 2 will be explained according to the manufacturing process. First, the entire surface of the glass substrate (1) was sputtered with Ta at 2500X.
A gate electrode (2) is formed by vapor deposition and photoetching. Next, a photoresist is applied, and the resist at the intersection of the TFT section and the data line/line is removed by exposure and development, and anodization (3) and (3') are performed. Furthermore, 3000λ of 5i02f[(4) is deposited on the entire surface.
次に画素部電極（６）をＩＴφで作成する。さらにグロ
ー放電によりアモルファスＢｉｇ （５） ３０００
Ａｊ４に積しパターニングを行う。次にコンタクトホー
ルを作成後ＡＩ蒸着をＩａｍ行い、ホトエツチングによ
シンース（７’） 、ドレイン（７）電極を作成、同時
にゲート上の第２層電極（８）を作成し簿膜トランジス
タと画素部を製造する。Next, the pixel part electrode (6) is made of ITφ. Furthermore, amorphous Big (5) 3000
Aj4 is stacked and patterned. Next, after creating a contact hole, AI evaporation was performed, and the thin layer (7') and drain (7) electrodes were created by photoetching, and at the same time, the second layer electrode (8) on the gate was created, forming the film transistor and pixel area. Manufacture.
ここでゲート電極のライン抵抗を測定してみた。Here, I measured the line resistance of the gate electrode.
従来法のゲート電極（Ｔａ＋陽極酸化）ラインでは厚さ
２５００人、巾３Ｑμｍ、長さ２５０ｍｍの１本の抵抗
は８５にΩ〜７０にΩと高く、これ以上ラインが長くな
ると回路駆動動作速度が下がり表示品位を低下する要因
となる。しかし本発明法で作成した二１−ゲート電極の
ライン抵抗は、Ｔａ厚２５００１＋入ｊ厚ＩＪｍ、巾３
０μｍ、長さ２５０ｍで１７〜２０にΩと低く動作速度
上なんの問題もなかった。又ゲート電極のオープンチェ
ックを行ってみると、従来法で作成したものは、４８０
本中オープンのライン３０本〜５０本と多く、又本発明
法で作成したものはオープンライン０本と良い結果を得
た。In the conventional gate electrode (Ta+anodized) line, the resistance of a single line with a thickness of 2,500 mm, width of 3 Q μm, and length of 250 mm is as high as 85Ω to 70Ω, and if the line becomes longer than this, the circuit drive operation speed will decrease. This causes a drop in display quality. However, the line resistance of the 21-gate electrode created by the method of the present invention is Ta thickness 25001 + input j thickness IJm, width 3
0 μm and a length of 250 m, it was as low as 17 to 20 Ω, and there was no problem in operating speed. Also, when I performed an open check on the gate electrode, it was found that the gate electrode made using the conventional method was 480
There were as many as 30 to 50 open lines in the book, and good results were obtained with no open lines in those prepared by the method of the present invention.
従来法の断線の原因は、ゴミ、レジストのはがれ、マス
クのキズあるいは５ｉ０２膜のピノホール等が考えられ
る。本発明のゲート電極二層構造では、一層電極がオー
プンしていても二１１Ｅ極を作成する為、同一場所での
オープンがないかぎりゲート電極はオープンとなラナイ
。The causes of disconnection in the conventional method are considered to be dust, peeling of the resist, scratches on the mask, or pinholes in the 5i02 film. In the gate electrode two-layer structure of the present invention, even if one layer electrode is open, two 11E electrodes are created, so the gate electrode remains open unless there is an open at the same location.
大面積化に伴って表示セル数が増加し、それに比例して
電極数も増加し、又電極長さも増加する。As the area becomes larger, the number of display cells increases, and the number of electrodes also increases in proportion to this, and the length of the electrodes also increases.
しかし、電極パターン形成時のライン断線の増加、ライ
ン抵抗の問題等は本発明電極構造を用いる事によって解
決できる。However, problems such as increased line breakage and line resistance during electrode pattern formation can be solved by using the electrode structure of the present invention.
以上のように本発明電極構造を用することにより、ゲー
トラインの低抵抗化、ゲー）！極の断線防止となシ表示
品位を著しく向上する。又大面積表示装置に最適である
。As described above, by using the electrode structure of the present invention, the resistance of the gate line can be reduced. It prevents disconnection of the poles and significantly improves display quality. It is also ideal for large area display devices.
第１図は本発明実施例を示す平面図、！２図は第１図で
示すｘ−ｘ’断面図、第３図は従来図を示したものであ
る（本発明のｘ −ｘ’にあ九る部分）。
１・・・ガラス基板
２・・・ゲート電極（Ｔａ ）
３ 、３’ ・・・局部陽極酸化（Ｔａ２０５）４ ・
＝ 絶縁ｍ （Ｓ ｉ０２ ）
５・・・アモルファス８ｉ
６・・・表示電極（ＩＴφ）
７・・・ドレイン電極（人ｌ）FIG. 1 is a plan view showing an embodiment of the present invention. FIG. 2 is a sectional view taken along the line xx' shown in FIG. 1, and FIG. 3 is a conventional view (the portion taken along the line x-x' of the present invention). 1... Glass substrate 2... Gate electrode (Ta) 3, 3'... Local anodic oxidation (Ta205) 4.
= Insulation m (S i02 ) 5... Amorphous 8i 6... Display electrode (ITφ) 7... Drain electrode (person l)
Claims (3)
ータラインで構成される表示装置において、アドレスラ
インのゲート電極が多層構造であることを特徴とする表
示装置。(1) A display device consisting of a plurality of address lines and data lines that are perpendicular to each other, wherein the gate electrode of the address line has a multilayer structure.
されたＴａ層であることを特徴とする特許請求の範囲第
１項記載の表示装置。(2) The display device according to claim 1, wherein at least one layer of the multilayer electrode is a locally anodized Ta layer.
、Ａｕ、Ｐｔのいずれか一つからなる層とを組合せたも
のであることを特徴とする特許請求の範囲第１項記載の
表示装置。(3) The multilayer electrode has at least a Ta layer, Al, and Mo.
2. The display device according to claim 1, wherein the display device is a combination of layers made of any one of , Au, and Pt.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60204409A JPS6265468A (en) | 1985-09-18 | 1985-09-18 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60204409A JPS6265468A (en) | 1985-09-18 | 1985-09-18 | Display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6265468A true JPS6265468A (en) | 1987-03-24 |
Family
ID=16490065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60204409A Pending JPS6265468A (en) | 1985-09-18 | 1985-09-18 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6265468A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01227128A (en) * | 1988-03-07 | 1989-09-11 | Mitsubishi Electric Corp | Liquid crystal display device |
| JPH0210330A (en) * | 1988-06-29 | 1990-01-16 | Hitachi Ltd | Active matrix substrate and production thereof and liquid crystal display element formed by using the same substrate |
| US5889573A (en) * | 1989-08-14 | 1999-03-30 | Hitachi, Ltd. | Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipment |
-
1985
- 1985-09-18 JP JP60204409A patent/JPS6265468A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01227128A (en) * | 1988-03-07 | 1989-09-11 | Mitsubishi Electric Corp | Liquid crystal display device |
| JPH0210330A (en) * | 1988-06-29 | 1990-01-16 | Hitachi Ltd | Active matrix substrate and production thereof and liquid crystal display element formed by using the same substrate |
| US5889573A (en) * | 1989-08-14 | 1999-03-30 | Hitachi, Ltd. | Thin film transistor substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal display equipment |
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