KR940006918Y1 - Display panel - Google Patents

Abstract

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Description

[Designation name]

Display panel

[Brief Description of Drawings]

1 is a planar layout view of a display panel according to an exemplary embodiment of the present invention.

2 is a cross-sectional view of the TFT portion and the storage capacitor portion of FIG.

3 is a plan view of a pixel of a display panel according to the related art.

[Detailed Description of Utility Model]

Industrial use field

This invention relates to a display panel, and more particularly, to a liquid crystal display panel and an electrode wiring material of a thin film transistor used as an active element of an SRAM, and a liquid crystal display panel using the wiring material.

Prior art and problem

An active matrix liquid crystal display device employing a thin film transistor using amorphous silicon or polycrystalline silicon as a switching element has attracted much attention.

In particular, amorphous silicon has good compatibility with a large-area transparent glass substrate and does not have any particular difficulties in large screen response, reproducibility, low temperature deposition, film quality, and the like. When formed, a cheap display panel having high quality and high definition of a large screen can be realized.

In the conventional liquid crystal display panel, a structure as shown in FIG. 3 is used.

3 is a pixel plan view of a conventional display panel, in which a gate bus line 13 and a data line 12 are arranged in a matrix form on a transparent glass substrate 10, and thin film transistors are disposed at each intersection. The thin film transistor includes a gate electrode 15 connected to the gate bus line 13, a source electrode 12a connected to the data line 12, and a drain electrode 12b connected to the liquid crystal cell via the pixel electrode 18. Doing.

The gate electrode 15 may be integrally formed on the gate bus line 13 and the source electrode 12a may be integrally formed on the data line. Reference numeral 19 denotes a portion where the pixel electrode 18 and the gate bus line 13 overlap, that is, a storage capacitor, which is also formed integrally with the gate bus line 13.

In the conventional display panel having such a structure, after forming pads using chromium (Cr) on the transparent glass substrate 10, the gate electrode 15, the gate bus line 13, and the storage capacitor 19 are made of Al. Or by patterning a metal mainly composed of Al. Anodization is then performed, and SiN _X is formed thereon to form a gate insulating film of Al ₂ O ₃ / SiN _X.

Then, an ohmic layer is sequentially formed of an amorphous silicon (a-Si) film 17 into which impurities are not implanted, and n ₊ type amorphous silicon (n ₊ a-Si) and chromium (Cr).

Next, a transparent electrode 18 for each pixel is formed by an ITO (Indum thin oxide) film, and finally the data line 12, the source electrode 12a, and the drain electrode 12b are formed in the resultant structure of the process. In order to form continuously) Al films are laminated and patterned. In this case, the source electrode 12a is integrally formed with the data line 12, and the drain electrode 12b is formed to be spaced apart from the source electrode 12a to be connected to the pixel electrode 18.

In the conventional display panel, however, Al, which is a material for forming the gate electrode 15 and the storage capacitor 19, is difficult to taper because of its characteristics. The thinning of the metal part occurs. Because of this, there is a case of burn-out during electrical operation, and the device characteristics become unstable. Here, the taper etching means that the edges are tapered in order to prevent process damage that may occur on the gate electrode 15 and the storage capacitor 19.

In addition, Al does not appear well in a wide and constant line like the gate bus line 13, but when Al has a specific shape such as the gate electrode 15 and the storage capacitor 19, Al is heat treated, for example, a hard bake Bake, hihhock, pin hole and surface roughness appear due to temperature increase effect due to deposition. This is a major factor in disturbing the operation of the panel because the gate electrode 15 and the storage capacitor 19 control the electrical operation characteristics.

Purpose of devising

The purpose of this design is to make full use of the low line resistance, which is an advantage of aluminum electrode wiring material, to prevent the difficulty of taper etching, which is a disadvantage of aluminum, to prevent hillocks and pinholes due to heat treatment, and to avoid surface roughness. The present invention provides an improved display panel.

Constitution

The present invention for achieving the above object is an insulating substrate, a plurality of gate bus lines and data lines intersected with each other on the insulating substrate, and formed on the lower layer of the gate bus line and electrically connected to the gate bus line. A plurality of thin film transistors each having a gate electrode portion and a source electrode connected to a data line, and a plurality of pixel electrodes connected to drain electrodes of the thin film transistors are provided.

In the above configuration, tantalum is used as the gate electrode material or the storage capacitor electrode material of the thin film transistor, and aluminum is used as the electrode material of the address line and the data line.

Action

According to this design of the above configuration, tantalum (Ta) is used as the gate electrode material or the storage capacitor material of the thin film transistor, and the material of the gate bus line and the data line is made of aluminum so that the shape etching, that is, the tape etching is easily performed. The improved curvature can prevent a short circuit between the gate and drain electrodes and a short circuit between the accumulation electrode and the pixel electrode.

In addition, the operation characteristics of the panel are improved by eliminating the hillock, pinhole generation problem and surface roughness, which are inevitable in the related art, in which the gate electrode is integrally formed with the gate bus line.

In addition, due to the properties of tantalum, a good anodic oxide film can be formed, which is advantageous for forming a multilayer gate insulating film.

EXAMPLE

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a planar layout view showing a part of a display panel according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the TFT portion and the storage capacitor portion of FIG.

Gate bus arranged in a matrix form on the line (13 ₁ -13 ₂₎ and data lines (12 ₁ -12 _3), a transparent glass substrate 10, there is a thin film transistor is disposed in each cross point of these, a thin film transistor the liquid crystal by the gate bus line (13 ₁ -13 ₂₎ the gate electrode (14 ₁ -14 ₇₎ and the data line source electrode (12a) and a pixel electrode 18 connected to the (12 ₁ -12 ₃₎ connected to the intermediate A drain electrode 12b connected to the cell is provided.

The manufacturing method of the liquid crystal display panel which has such a structure is demonstrated.

First, a Ta film is laminated on the transparent glass substrate 10 by a sputtering method, and the resulting structure is patterned by a photolithography process to form the gate electrode 15 and the storage capacitor 19. ₁ -14 ₇ ). In this process, the edges of the gate electrode portions 14 ₁ are tapered to prevent process damage that may occur on the gate electrode 15 and the storage capacitor 19. In this regard, since Ta is a material having a favorable property for taper etching, it can be performed quickly using a resistor and CF ₄ + O ₂ .

It said gate electrode (14 ₁₎ includes a gate bus line to be formed in the part 15 and the follow-up process in which the portion 19, the actual gate electrode is the accumulation capacitor is overlapped with the actual pixel electrode 19 (13 ₁ -13 _The part which overlaps with ₂ ) is integrally formed.

Therefore, the accumulation capacitor 19 portion should be formed wide enough with the pixel electrode 18, and the gate electrode 15 portion should be formed small enough so as not to affect the device characteristics. However, there is no gate electrode portion to be limited to the (14 ₁ -14 ₇₎ has a constant shape which is a problem in the design of the pattern only for optimization.

These are the gate electrode (14 ₁ -14 ₇₎ and electrically connected (short) so that the gate electrode (14 ₁ -14 ₇₎ in a laminated aluminum (Al) sputtering film and patterning the gate bus line ( 13 ₁ -13 ₂ ).

The actual gate electrode 15 according to this embodiment has a thickness of 250 nm and a length of 40 μm. This is equal to the thickness of the address line 13 ₁ .

Subsequently, the process in a two-layer structure of the gate bus line (13 ₁ -13 ₂₎ and the gate electrode (14 ₁ -14 ₇₎ at the same time by the anode oxidation to form a nitride film _{Ta 2 O 5 / Si 3 N} 4 On the finished structure, the gate insulating films 22 and 24 are formed and an impurity-implanted amorphous silicon (a-Si) film 17, n ₊ type amorphous silicon (n ₊ a-Si) 26, and chromium ( The ohmic layer 28 is sequentially formed from Cr).

Next, the transparent electrode 18 is formed by the ITO film, the final step in the data line (12 ₁ -12 ₃₎ and a source electrode (12a) and a drain electrode (12b) on the resultant structure of the process for each pixel In order to form the film continuously, the Al film is laminated and patterned. At this time, the source electrode (12a) is formed integrally with the mutator lines (12 ₁ -123), a drain electrode (12a) is formed to be spaced apart from the source electrode (12a) to be connected to the pixel electrode 18.

Effect of design

As such, according to the present invention, since Ta is used as a material for the gate electrode and the storage capacitor, which has low specific resistance and excellent processability and stability, the step coverage is improved as the taper etching is possible, and the yield is improved by the stabilization of the subsequent process.

Claims (4)

An insulated substrate, a plurality of gate bus lines and data lines intersected with each other on the insulated substrate, and a source formed in a lower layer of the gate bus line and connected to a gate electrode portion and a data line electrically connected to the gate bus line; A display panel comprising a plurality of thin film transistors provided with electrodes and a plurality of pixel electrodes connected to drain electrodes of the thin film transistors. The display panel of claim 1, wherein the gate electrode part is formed of an accumulation capacitor which is an area overlapping the pixel electrode, a gate electrode, and a portion electrically overlapping the gate bus line. The display panel of claim 1, wherein the gate electrode is formed of tantalum (Ta). The display panel of claim 1, wherein the gate bus line is formed of aluminum (Al).