JPS6265343A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of undistributed wirings and to improve a design operation efficiency by a method wherein the space between the unit cells of each unit cell row or the space between the unit cells of every prescribed number unit cells and the areas of the wiring areas are increased as the unit cell rows and the wiring areas are near the central part of a chip. CONSTITUTION:A device 1 is constituted in such a way that the number of the unit cells 4 of each unit cell block 4a and 4b is increased according as the blocks approach the central part of the device 1, whereby the wiring density at the central part can be reduced. Moreover, the device is constituted in such a way that the area of each wiring region 5a and 5b is increased according as the regions approach the central part of the device 1, whereby the number of the wirings which are connected to the logic circuit can be increased according as the wiring areas approach the central part, the wiring density at the central part can be reduced, in particular, the wiring density of the wirings which are formed extendedly in the line direction can be reduced. Furthermore, the device is constituted in such a way that the areas of wiring regions 5A-5C are increased according as the regions approach the central part of the device 1, whereby the number of the wirings which are connected to the logic circuit can be increased according as the wiring regions approach the central part, the wiring density at the central part can be reduced, in particular, the wiring density of the wirings which are formed extendedly in the column direction can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device that employs a master slice method.

[Background Art] Semiconductor integrated circuit devices are known that employ a mask slicing method that allows designing of a wide variety of products in small quantities in a short time. In this semiconductor integrated circuit device, unit cells made according to a basic design are regularly arranged in a matrix. A logic circuit is constructed by wiring within and between unit cells. The semiconductor integrated circuit device configured in this manner has the feature that various logic circuits can be configured by simply changing the wiring pattern in the wiring forming process without changing the arrangement form of the unit cells. Further, by regularly arranging the unit cells, it is possible to easily perform so-called automatic design in which a computer automatically designs the layout of the logic circuit and the wiring inside and outside the logic circuit.

However, the results of considerations in such technology.

The present inventor discovered that the following problems occur. Since this type of semiconductor integrated circuit device is designed to effectively use unit cells, logic circuits are arranged so as to be uniformly distributed over the entire chip. The wires connected to this logic circuit are thought to extend in all directions, and the number of wires passing through the center of the chip increases, so the wire density at the center of the chip becomes significantly higher than at the periphery of the chip. For this reason.

In automatic design, there are many unwired areas in which wiring cannot be provided, and the designer has to manually design the wiring. That is, in a semiconductor integrated circuit device that employs the master slice method, the efficiency of design work becomes extremely poor.

Note that a semiconductor integrated circuit device employing the master slice method is described in, for example, Japanese Patent Laid-Open No. 57-211248.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the efficiency of design work in a semiconductor integrated circuit device that employs a master slice method.

Another object of the present invention is to provide a technique that can reduce the wiring density in the central part of a chip and reduce the number of unwired lines through automatic design.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device that employs the master slicing method, the area between unit cells in a unit cell row or between unit cells for each predetermined number of unit cell rows and the area of the wiring region is configured to be larger as it approaches the center of the chip.

This increases the number of wires that can be placed in the center of the chip and reduces the wiring density in the center of the chip.

The number of unwired wires can be reduced by automatic design.

As a result, artificial wiring design can be reduced, and work efficiency can be improved.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device that employs a master slicing method using a CMO 5 as a unit cell.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment] FIG. 1 is a schematic configuration diagram showing a semiconductor integrated circuit device employing a master slice method as an embodiment of the present invention.

In FIG. 1, l is a semiconductor integrated circuit device that employs a master slice method. Reference numeral 2 denotes an external terminal (bonding butt) provided at the periphery of the semiconductor integrated circuit device 1, and 3 an output buffer circuit provided at the periphery of the semiconductor integrated circuit device 1.

A plurality of unit cells 4 are regularly provided in the center of the semiconductor integrated circuit bag [1. Basic cell 4 is NAND
, AND, F, F, etc. are configured.

The basic cell 4, as shown in the enlarged plan view of the main part before the wiring forming process in FIG. Cell 4 has three p-channel MIs
SFETQp and three n-channel M I S F E
It is composed of TQn. 3 MISFETs
Qp or Qn is constituted by a series circuit that shares one source region or drain region.

MISFETQp is configured on an n-type semiconductor substrate IA made of single crystal silicon. MISFETQn is configured in a P-type well region IB.

As shown in FIG. 1, a plurality of unit cells 4 are arranged in one column to form a unit cell block 4 a r 4 b. This unit cell block 4a + 4b is
A plurality of unit cell columns 4A are arranged in the column direction with wiring regions 5a and 5b provided between them. This unit cell column 4A has wiring areas 5A, 5B, and 5C.
A plurality of them are arranged in the row direction with

The number of unit cells 4 in the unit cell blocks 4a, 4b is configured to become thicker as it approaches the center of the semiconductor integrated circuit device (chip) 1 compared to its periphery. By configuring it like this.

Since the number of logic circuits constituted by the unit cell 4 and the number of wires connected thereto can be decreased as the distance from the central portion approaches, the wiring density in the central portion can be reduced.

The areas of the wiring regions 5a and 5b are configured to increase as they approach the center of the semiconductor integrated circuit device 1. With this configuration, the number of wires connected to the logic circuit can be increased closer to the center, so that the wire density in the center can be reduced. In particular, the wiring density of wiring formed extending in the row direction can be reduced.1 For example, in a semiconductor integrated circuit device 1 using two layers of aluminum wiring, the wiring density of the wiring extending in the row direction can be reduced. The wiring density of aluminum wiring can be reduced.

The areas of the wiring regions 5A, 5B, and 5C are configured to increase as they approach the center of the semiconductor integrated circuit device 1. With this configuration, the number of wires connected to the logic circuit can be increased closer to the center, so that the wire density in the center can be reduced. In particular, it is possible to reduce the wiring density of wiring formed extending in one column direction.For example, in a semiconductor integrated circuit bag Wtl using two layers of aluminum wiring, one
Layered aluminum wiring (also installed inside unit cell 4)
wiring density can be reduced.

In addition, in the present invention, instead of configuring the unit cell column 4A with unit cell blocks 4a and 4b with wiring regions 5a and 5b interposed therebetween, a unit cell column is formed by arranging a plurality of unit cells 4 in the row direction at predetermined intervals. In this case, the area between unit cells 4 is equal to that of a semiconductor integrated circuit device! ! The structure is configured so that the closer to the center of 1, the larger the size becomes. The space between these unit cells 4 can be used as a wiring area.

In addition, the present invention provides an inverter circuit, a two-man power or a four-man power NAND gate circuit in place of the unit cell 4 that can constitute a three-man power NAND gate circuit.
It may be composed of unit cells that can constitute a human-powered NAND gate circuit.

Further, in the present invention, the unit cell may be configured with a single channel ME S FET instead of the 0MO3 unit cell 4.

Further, the present invention provides wiring areas 5a, 5b or wiring area 5A.
, 5B, 5G for embedded semiconductor elements (for example, MISF
ET, bipolar transistor) may be provided.

Further, in the present invention, a semiconductor element capable of forming a memory function (ROM, RAM) may be provided in a predetermined portion of the semiconductor integrated circuit device 11.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(1) In a semiconductor integrated circuit device that adopts the master slicing method, by configuring the area between unit cells in a unit cell row or between unit cells in each predetermined number of unit cell rows to be larger as the area approaches the center of the chip, Since the number of lines extending in the row direction that can be provided at the center of the chip can be increased, the wiring density at the center of the chip can be reduced.

(2) In a semiconductor integrated circuit device that adopts the master slicing method, by configuring the area of the wiring area between unit cell columns to be larger as it approaches the center of the chip, wiring extending in the column direction can be provided at the center of the chip. Since the number can be increased, the wiring density at the center of the chip can be reduced.

(3) With (1) and (2) above, it is possible to reduce the number of unwired lines through automatic design, which reduces the need for artificial wiring design placement and improves work efficiency in designing semiconductor integrated circuit devices. be able to.

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device employing a master slice method according to an embodiment of the present invention, and FIG. 2 is an enlarged plan view of the main part of FIG. In the figure, 1...Semiconductor integrated circuit bag! (chip), 4...
・Unit cell, Qp, Qn-MISFET, 4a, 4b・
...Unit cell block, 4A...Unit cell row, 5a. 5b, 5A, 5B, 5C... wiring areas. Figure 1

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which unit cells composed of a plurality of semiconductor elements are arranged regularly and various functions can be obtained by changing the unit cells and wiring patterns between the unit cells. A circuit device, wherein a plurality of the unit cells are arranged in a column direction to form a unit cell column, and a plurality of the unit cell columns are arranged in a row direction with a wiring area interposed therebetween, and the unit of the unit cell column is 1. A semiconductor integrated circuit device, wherein the area between cells or the area between unit cells in each predetermined number of unit cell rows and the area of the wiring region increase as the area approaches the center of the chip. 2. The semiconductor integrated circuit device according to claim 1, wherein the space between the unit cells in the unit cell row is used as a wiring area. 3. A predetermined number of unit cells in the unit cell row constitute a unit cell block, and the number of unit cells in the unit cell block decreases as it approaches the center of the chip. The semiconductor integrated circuit device according to item 1. 4. The semiconductor integrated circuit device according to claim 1, wherein a semiconductor element is provided between unit cells of the unit cell row or in a wiring area.