JPS6262594A - Mounting method for electronic part with lead - Google Patents
Mounting method for electronic part with leadInfo
- Publication number
- JPS6262594A JPS6262594A JP20157585A JP20157585A JPS6262594A JP S6262594 A JPS6262594 A JP S6262594A JP 20157585 A JP20157585 A JP 20157585A JP 20157585 A JP20157585 A JP 20157585A JP S6262594 A JPS6262594 A JP S6262594A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lead
- recesses
- electronic component
- soldering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔発明の技術分野〕 この発明はリード付き電子部品の実装方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for mounting leaded electronic components.
〔発明の技術的背景およびその問題点〕半導体工業の発
展は目覚しく、高性能半導体素子の開発によりその応用
製品も多方面に亘っている。各応用製品において、印刷
配線板に独自の回路配線を回路設計している。このよう
に、半導体を使用する応用製品分野においても、自社独
自の回路を設計し、ファクトリオートメーション(FA
)を採用して大量生産に対応している。このようなFA
システムにおいて接着材で電子部品を取着する全自動マ
ウンタやICのポンディングパッドと印刷回路基板のボ
ンディングパッ、ド間を配線する全自動ボンダなどは高
度に発達した。しかし1組付は型のはんだ付は技術の全
自動化においては、大幅を印刷回路基板の予備はんだ付
けされたパターン上に位置決めして移送後、上記多数配
列されたす−ド上から棒状ヒータチップ(はんだごて)
により、加熱押圧すると、多数のはんだ付は作業におい
ては、印刷配線基板の予備はんだ付はパターンからずれ
てはんだ付けされるものが見られる。[Technical background of the invention and its problems] The development of the semiconductor industry is remarkable, and the development of high-performance semiconductor elements has led to a wide range of applied products. For each applied product, we design unique circuit wiring on printed wiring boards. In this way, even in the field of applied products that use semiconductors, we design our own circuits and implement factory automation (FA).
) to support mass production. This kind of FA
Fully automatic mounters for attaching electronic components using adhesives in systems, fully automatic bonders for wiring between IC bonding pads and printed circuit boards, and bonding pads for ICs have become highly developed. However, in fully automated soldering technology, one set of soldering molds must be positioned on the pre-soldered pattern of the printed circuit board and transferred, and then the bar-shaped heater chips are placed on the multiple arrayed boards. (soldering iron)
Due to this, when heating and pressing, during a large number of soldering operations, preliminary soldering of printed wiring boards may be soldered out of alignment with the pattern.
この「ずれJてはんだ付けされたものは、 ICのリ
ードと印刷配線基板の予備はんだの幅とがほぼ同一であ
り、間隔も1リ一ド分程度であるため。This is because the width of the IC lead and the pre-solder on the printed wiring board are almost the same, and the distance between them is about one lead.
絶縁不良となってしまう。This will result in poor insulation.
この歩留りは、生産性を向上させるためにはんだ付は速
度を高速化すればする程、悪くなる。この歩留りは部品
数が多い大きな印刷配線板であればある程、歩留りの向
上は大きな問題である。The yield rate worsens as the soldering speed increases in order to improve productivity. The larger the printed wiring board with a larger number of parts, the greater the problem of improving the yield.
この改善手段として印刷配線基板の予備はんだ部に凹部
を形成することが考えられるが、印刷配線パターンの高
密度化やフラットパッケージ形ICのリード数が増加す
るにつれて凹部の形成が実際上困難になるなどの改善が
要望されていた。One idea to improve this problem is to form recesses in the pre-soldered parts of printed wiring boards, but as the density of printed wiring patterns increases and the number of leads in flat package ICs increases, it becomes difficult to form recesses in practice. Improvements were requested.
この発明は上記点に対処してなされたもので。 This invention was made in response to the above points.
高密度な印刷配線パターンでも所望する配線部へ溶融工
程における位置ずれを減少させ1歩留りを向上させるリ
ード付き電子部品の実装方法を提供するものである。The present invention provides a method for mounting electronic components with leads, which reduces misalignment during the melting process and improves the yield of desired wiring parts even with a high-density printed wiring pattern.
すなわち、電子部品のリードを印刷配線板の配線部に実
装するに際し、上記各配線部に予めフォトエツチングに
より凹部を形成する工程と、上記凹部に上記電子部品の
リードを係合させて実装する工程を設けたリード付き電
子部品の実装方法を得るものである。That is, when mounting the electronic component leads on the wiring portions of the printed wiring board, there are two steps: forming recesses in each of the wiring portions in advance by photoetching, and mounting the electronic component leads by engaging them in the recesses. The present invention provides a method for mounting an electronic component with leads.
次lこ本発明方法を印刷配線板への電子部品のはんだ付
けに適用した実施例を図面を参照して説明する。Next, an embodiment in which the method of the present invention is applied to soldering electronic components to a printed wiring board will be described with reference to the drawings.
絶縁性基板例えばガラスエポキシ樹脂製基板(1)の表
面に回路基板製造技術で選択的に配線(2)が形成され
、この配線(2)のはんだ付は個所のみ露出する如くは
んだレジスト(3)が形成され、印刷配線板(4)が形
成されている。さらに配線板(4)の、はんだ付は個所
上にクリームはんだを塗布し、この塗布した状態で高温
槽(図示せず)内に所定期間露らす。この工程によりは
んだ付は個所のみにクリームはんだ71)らなる予備は
んだ(5)が形成される。第1図(A)に第1図(B)
、 (C)に示めずフラットパッケージ型ICt6)の
予備はんだ付はバター/(力を示めす。第1図(B)は
正面図、第1図(C)は側面図である。このフラットパ
ッケージ型IC(6)の構造は当業者において局知のも
ので、モールド体(8)の側壁例えば2辺から多数のリ
ード(9)が設けられ、これらリード(9)は第1図(
C)に示めずように途中から屈折し先端部αυがモール
ド体(8)の底面と同一平面を形成するように構成され
たものである。このような構造のフラットパッケージ3
iIC(6)を印刷配線板(4)に、はんだ付けするの
であるが、この時、この発明の実施例では次のように行
う。即ち、形成された予備はんだ部(5)の一部例えば
IC(8)のリード(9)におけるはんだ付は部01)
が係合する印刷配線板の部分に凹部例えば予備はんだ(
5)を適宜な景部分的に除去した領域α2即ち凹部を形
成する。この状態を第1図(C)(ロ)に示めす。この
領域αりはIC(81の実装に際し、リード(9)のは
んだ付は部αυが対接される面積以上に領域(14を形
成することが望ましい。Wires (2) are selectively formed on the surface of an insulating substrate, such as a glass epoxy resin substrate (1), using circuit board manufacturing technology, and solder resist (3) is used to solder these wires (2) so that only the parts are exposed. is formed, and a printed wiring board (4) is formed. Further, cream solder is applied to the soldering parts of the wiring board (4), and the applied state is exposed in a high temperature bath (not shown) for a predetermined period of time. Through this process, preliminary solder (5) consisting of cream solder 71) is formed only at the soldering points. Figure 1 (A) and Figure 1 (B)
, The pre-soldering of the flat package type ICt6) not shown in (C) shows the butter/(force. Figure 1 (B) is a front view, and Figure 1 (C) is a side view. The structure of the packaged IC (6) is well known to those skilled in the art, and a large number of leads (9) are provided from the side wall of the molded body (8), for example, from two sides, and these leads (9) are arranged as shown in FIG.
As shown in C), it is bent in the middle so that the tip αυ forms the same plane as the bottom surface of the mold body (8). Flat package with this structure 3
The iIC (6) is soldered to the printed wiring board (4), and this is done as follows in the embodiment of the present invention. That is, a part of the formed preliminary solder part (5), for example, the soldering of the lead (9) of the IC (8) is part 01).
Place a recess in the part of the printed wiring board that will be engaged by the pre-solder (for example
5) is partially removed to form a region α2, that is, a concave portion. This state is shown in FIG. 1(C)(B). When mounting the IC (81), it is desirable that the area (14) for soldering the leads (9) be larger than the area where the portions αυ are in contact with each other.
この領域(Lカの形成は印刷配線板における総ての予備
はんだ部(5)のはんだ付は部αυの係合する領域a力
のみを選択的にフォトエツチングする。これは予めパタ
ーンユングにより容易に形成できる。表面にフォトレジ
ストを被着し、このフォトレジストをパターンユングす
ることによりできる。即ち一板印刷配線板について同時
に形成され、微細加工が容易に形成できる。上記パター
ンユングは夫々のリードの形状大きさに応じた凹部の形
成も選択的に容易lこできる。このようにして予備はん
だ(5)の除去された領域(12に7ラツトパツケージ
型IC(8)のはんだ付けに際し、フラックスを塗布し
た後リード(9)のはんだ付は部Iが係合載置される。To form this region (L), solder all the preliminary solder parts (5) on the printed wiring board by selectively photo-etching only the area a where part αυ engages.This can be done easily by patterning in advance. It can be formed by depositing a photoresist on the surface and patterning this photoresist.In other words, it can be formed simultaneously on a single printed wiring board, and microfabrication can be easily formed. It is also possible to selectively and easily form recesses according to the shape and size of After applying the soldering lead (9), part I is engaged and placed.
この工程は、 IC(8)を位置決め後、予め記憶され
たプログラムにより、予め教示された位tltlcロボ
ットにより自動搬送され、載置される。この状態で、−
辺のリード(9)群を跨ぐ如き先端棒状の予備加熱され
たヒータチップ(はんだごて)(図示せず)を押圧する
。この押圧と同時に加熱電流を増大して。In this process, after positioning the IC (8), it is automatically transported and placed by a tltlc robot at a position taught in advance according to a pre-stored program. In this state, −
A preheated heater tip (soldering iron) (not shown) with a rod-shaped tip that straddles the group of leads (9) on the side is pressed. At the same time as this pressing, increase the heating current.
予備はんだ(5)を溶融させて、 IC(6)のリード
(9)をはんだ付けする。このように凹部圓に係合させ
てはんな付けするので凹部aりの側壁により位置決めさ
れ予備はんだ(5)の溶融時に生ずる横方向位置ずれを
改善できる。特に、この実施例では、はんだ付は部αυ
の係合する部分の予備はんだ(5)が完全に除去され、
平坦な配線(2)上に載置されるので1位置ずれに対し
て大幅に改善できる効果がある。Melt the preliminary solder (5) and solder the leads (9) of the IC (6). Since the soldering is performed by engaging the concave portion in this manner, the solder is positioned by the side wall of the concave portion a, and the lateral displacement that occurs when the preliminary solder (5) is melted can be improved. In particular, in this embodiment, the soldering is done at αυ
The preliminary solder (5) on the engaging part is completely removed,
Since it is placed on the flat wiring (2), it has the effect of greatly improving one positional deviation.
以上説明したように予備はんだ部にフォトエツチングに
より凹部を形成し、この凹部にICのリードを係合させ
てはんだ付けするので位置ずれを軽減できる。予備はん
だは印刷配線板(4)に電子部品をはんだ付けする際、
印刷配線板(4)のはんだ付は部分に予めはんだを形成
しておく方法がとられるが、この予め形成されるはんだ
を言う。このはんだは1表面が平滑な円弧状になってお
り、凹部の形成は効果がある。As explained above, a recess is formed in the preliminary solder portion by photo-etching, and the IC leads are engaged with the recess and soldered, so that positional displacement can be reduced. Pre-solder is used when soldering electronic components to the printed wiring board (4).
When soldering the printed wiring board (4), a method is used in which solder is formed on the parts in advance, and this refers to the solder that is formed in advance. One surface of this solder has a smooth arc shape, and the formation of recesses is effective.
以上説明したように本発明によれば、フォトエツチング
により凹部を形成し、この凹部に電子部品のリードを係
合させて実装するので、実装例えばはんだ溶融工程にお
ける位置ずれを減少させ。As described above, according to the present invention, a recess is formed by photo-etching, and the lead of an electronic component is engaged with the recess for mounting, thereby reducing misalignment during mounting, for example, in the solder melting process.
位置ずれによる歩留り低下の改善に効果がある。This is effective in improving yield reduction due to positional misalignment.
特にピンチ間が例えば0.65131と小さい間隔のも
のでも凹部の形成が可能である。In particular, it is possible to form recesses even when the distance between the pinches is as small as, for example, 0.65131.
上記実施例では電子部品としてフラットパッケージ形I
Cについて説明したが、電子部品リードのはんだ付けで
あれば何れでもよく1例えば砥抗。In the above embodiment, a flat package type I is used as an electronic component.
Although we have explained about C, any method may be used as long as it is used for soldering electronic component leads.For example, an abrasive.
トランジスタコンデンサなど何れでもよい。Any transistor capacitor or the like may be used.
上記実施例ではフラットパッケージ形ICの断面角形状
リードの例について説明したが、電解コンデンサのよう
に断面円形状リードでも、リードの断面形状は何れでも
同様な効果がある。断面円形状のリードの場合、凹部を
曲面状に形成すると。In the above embodiment, an example of a lead having a rectangular cross section in a flat package type IC has been described, but the same effect can be obtained regardless of the cross-sectional shape of the lead, even if the lead has a circular cross-section as in an electrolytic capacitor. In the case of a lead with a circular cross section, the recess is formed in a curved shape.
位置決めがさらによい。Even better positioning.
第1図(A)(BXCXD)(E)は本発明方法の実施
例説明図である。
1・・・基 板 →・・・印刷配線板5・・・
予(iitiはんだ 7・・・はんだ付はパターン
9・・・リ − ド 11・・・はんだ付は部1
2・・・四 部
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
(A)(B)(C)
(E)
第1図FIG. 1 (A) (BXCXD) (E) is an explanatory diagram of an embodiment of the method of the present invention. 1... Board →... Printed wiring board 5...
Pre-soldering 7...Soldering is pattern 9...Lead 11...Soldering is part 1
2...Fourth Division Agent Patent Attorney Nori Ken Chika Yudo Kikuo Takehana (A) (B) (C) (E) Figure 1
Claims (2)
るに際し、上記各配線部に予めフォトエッチングにより
凹部を形成する工程と、上記凹部に上記電子部品のリー
ドを係合させて実装する工程とを具備してなることを特
徴とするリード付き電子部品の実装方法。(1) When mounting the electronic component leads on the wiring portions of the printed wiring board, there is a step of forming recesses in each of the wiring portions in advance by photo-etching, and mounting the electronic component leads by engaging them in the recesses. A method for mounting a leaded electronic component, comprising the steps of:
品のリードを実装する手段は、上記凹部をはんだメッキ
する工程と、はんだメッキされた凹部にフラックスを塗
布する工程と、フラックスが、塗布された凹部に電子部
品のリードを係合させる工程と、凹部に係合されたリー
ド上方からヒータチップにより加圧加熱する工程とを具
備してなることを特徴とする特許請求の範囲第1項記載
のリード付き電子部品の実装方法。(2) The means for mounting electronic component leads in the recesses formed by photo-etching consists of a step of solder plating the recesses, a step of applying flux to the solder-plated recesses, and a step of applying flux to the recesses to which the solder has been applied. The lead according to claim 1, comprising the steps of: engaging a lead of an electronic component with the recess; and applying pressure and heat with a heater chip from above the lead engaged with the recess. How to mount electronic components with
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20157585A JPS6262594A (en) | 1985-09-13 | 1985-09-13 | Mounting method for electronic part with lead |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20157585A JPS6262594A (en) | 1985-09-13 | 1985-09-13 | Mounting method for electronic part with lead |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6262594A true JPS6262594A (en) | 1987-03-19 |
Family
ID=16443331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20157585A Pending JPS6262594A (en) | 1985-09-13 | 1985-09-13 | Mounting method for electronic part with lead |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6262594A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1139465C (en) * | 2002-12-13 | 2004-02-25 | 温松柏 | Electric device with double functions of stapler bookbinding device and hole-punching device |
-
1985
- 1985-09-13 JP JP20157585A patent/JPS6262594A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1139465C (en) * | 2002-12-13 | 2004-02-25 | 温松柏 | Electric device with double functions of stapler bookbinding device and hole-punching device |
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