JPS6261172B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When the power is turned on or when the power supply voltage is abnormal, the power supply voltage is reset internally during the period until the power supply voltage reaches a predetermined value and the operation of the entire semiconductor integrated circuit is stabilized. This semiconductor integrated circuit has a built-in reset circuit to prevent the generation of external signals, and can cancel the reset signal by inputting a predetermined signal from the outside to one of the existing input terminals. This is what we provide.

FIG. 1 is a diagram showing the configuration of a conventional reset circuit that is integrated into a semiconductor integrated circuit and can reset various integrated functional circuit blocks when the power is turned on or when the power supply voltage is abnormal. It is. In such a reset circuit, the power supply voltage detection section B and its detection output are applied between the power supply terminal A and the reset signal generation terminal D, and the circuit operates until the power supply voltage falls within the operating voltage range of the semiconductor integrated circuit when the power is turned on. Alternatively, a configuration is adopted in which a reset signal generating section C is arranged to generate a reset signal before the power supply voltage reaches a range where even a part of the functional circuit, such as a functional circuit, malfunctions when the power supply voltage is abnormal. This system was designed to forcibly reset the circuit using a signal generated by the circuit to prevent malfunction of the circuit, and also to prevent abnormal signals from being output to the outside, thereby improving the reliability of the system.

Incidentally, the power supply voltage value to which the reset is applied is usually set to a value somewhat lower than the lower limit value of the power supply voltage in the product standard. On the other hand, the operating range of products in which semiconductor integrated circuits are used is set to be sufficiently wider than the range of product standards from the perspective of product guarantee, and the lower limit of the operating power supply voltage is the power supply voltage at which the semiconductor integrated circuit needs to be reset. must be below the value. For this reason, testing is required to confirm that the product's operating range is even lower than the voltage required for reset, but in semiconductor integrated circuits with conventional reset circuits, There was an inconvenience that the reset occurred before the test was reached, making it impossible to perform the test.

The present invention provides a semiconductor integrated circuit that can eliminate such inconveniences, and a feature of the present invention is a reset circuit that generates a signal for operating a reset circuit built into the semiconductor integrated circuit. It has a signal generating circuit and a functional circuit that stops the operation of the reset circuit based on the output of this circuit, that is, a reset release functional circuit, and
The existing terminals can be used in common without adding additional terminals for inputting control signals from the outside, which is required due to the built-in reset release function circuit.

The configuration and operation of the main parts of the semiconductor integrated circuit of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a reset signal generation section and a reset release function circuit section built into the semiconductor integrated circuit of the present invention. The output terminal Bout is connected to the reset signal generator C.
The output terminal Cout is connected to the first input terminal _Ein1 of the reset release control section E. In addition, the terminal F to which the reset release signal is input from the outside is the input terminal of the input signal detection section G.
Gin, its output terminal Gout is connected to the input terminal Hin of the reset release signal generation section H, and this output terminal Hout is further connected to the second input terminal Hin ₂ of the reset release control section E. The output terminal Eout is connected to a reset signal generation terminal D connected to a reset circuit (not shown) included inside the integrated circuit.

Next, the operation of each part will be explained. First, a conventional power supply terminal A is a terminal for supplying power for operating the entire semiconductor integrated circuit, and is also connected to a power supply voltage detection section B as shown. Power supply voltage detection section B is connected to power supply terminal A.
It is detected whether the voltage applied to the semiconductor integrated circuit is sufficient to operate the semiconductor integrated circuit in a stable state. Reset signal generating section C receives a signal from power supply voltage detecting section B and generates a reset signal until the power supply voltage reaches a predetermined value. Under normal operating conditions, the reset release signal input terminal F is one of the input terminals or output terminals of the semiconductor integrated circuit.
However, while inputting a control signal for the purpose of canceling the reset, this terminal becomes the reset release signal input terminal. Input signal detection section G
is for detecting that the input signal applied to the reset release signal input terminal F is a reset release signal. Reset release signal generator H
receives the signal from the input signal detection section G and generates a reset release signal. Reset release control section E
receives the signals from the reset signal generation section C and the reset release signal generation section H, and if the reset release signal is not output, it outputs the signal output from the reset signal generation section C as is, while if the reset release signal is not output. If so, it acts to prevent generation of the reset signal to the reset signal generation terminal D during this period.

Incidentally, a particularly important part of the circuit block configured as described above is the input signal detection section G.
As mentioned above, the reset release signal input terminal F is normally used as an input terminal or an output terminal, and if the reset release signal is not generated under normal usage conditions, the reset release signal input terminal F will not be generated in the event of a power supply voltage abnormality, etc. , it becomes impossible to apply an accurate reset to the internal circuit.

When performing a reset release operation in the semiconductor integrated circuit of the present invention, there is a method of applying a voltage higher than usual as an input to the reset release signal input terminal F and detecting it using a voltage dividing circuit in the input signal detection section G. By applying a signal that would never occur in normal use, such as applying a periodic signal that cannot be considered as an input or output and detecting it using a gate circuit, the reset release signal generator can be reset normally. It is necessary to operate H.
Of course, for this purpose, the reset release signal input terminal F
It is necessary to decide the configuration of the input signal detection section G depending on which existing terminal is selected. Representative examples will be explained below.

The first embodiment is an example in which the input signal detection section G is configured using a voltage dividing circuit, and the specific circuit configuration is shown in FIG. As shown in the figure, MOS resistors M ₁ to _{M 5} made up of MOS transistors are connected in series between the reset release signal input terminal F and the ground point, and the series connection point X of MOS resistors M ₄ and M ₅ is connected in series. The input signal detection section G uses a voltage dividing circuit configured to obtain a divided voltage output.
, a reset release signal generating section H is composed of an amplifier, and a reset release control section E is constructed.
It consists of a two-input type NOR gate. In this circuit configuration, reset release signal input terminal F
The terminal used as a semiconductor integrated circuit may be either an input terminal or an output terminal. When a normal level input signal is applied or a normal output signal is output, the voltage divider circuit that constitutes the input signal detection section G regardless of whether the signal is high level or low level. Since this signal is voltage-divided, the voltage-divided level does not reach a level at which the reset release signal generating section H can be operated.

On the other hand, in order to generate a reset release signal,
When a signal with a higher level than the normal signal level is applied to the reset release signal input terminal F,
The voltage is divided in the input signal detection section G, and the signal level generated at the X point is higher than that at normal times.

Therefore, if the voltage division ratio of the voltage divider circuit is selected in consideration of the level of the input signal so that the reset release signal generation section H operates at this signal level, the reset release signal generation section H will work and reset. The release control section E performs an operation of not outputting the reset signal to the terminal D.

The second embodiment is an example in which a gate circuit is used as the input signal detection section G, and a specific circuit configuration is shown in FIG. The input signal detection section G includes a cascade connection of D flip-flops FF ₁ to FF ₃ as shown in the figure;
It is composed of NAND gates N to which the outputs of the D flip-flops FF ₁ to _{FF 3} are input, and the reset release signal generating section H is composed of an inverter.

In the case of this circuit configuration, it is appropriate to use as the reset release signal input terminal F an output terminal whose nature of the output signal is well known. Note that the illustrated gate circuit operates at a certain fixed period,
The configuration is based on the assumption that the terminal outputs a high level for two pulses of the internal clock. In a normal output state, the output of the input signal detection section G made up of a gate circuit does not go to a high level, so the reset release signal generation section H does not operate. No signal is generated.

On the other hand, in order to generate a reset release signal, an input that fixes the reset release signal input terminal F at a high level for a time equal to or longer than three pulses of the internal clock is applied. By applying such an input signal, the level of each output Q of FF ₁ to _{FF 3} becomes "1" level when three pulses of the internal clock arrive, and therefore the output of the NAND gate N, that is, the level of the output Q of the input signal detection section G The output becomes "O" level. Therefore, the output level of the inverter forming the reset release signal generation section H becomes "1" level, and the output of the reset release control section E, that is, the logic level of the terminal D is set to "O", and the operation of the reset circuit is started. The operating state to be stopped is established.

In this way, when a gate circuit is used as the input signal detection section G, the input signal detection section G suitable for the intended semiconductor integrated circuit can be constructed by combining the gates.

As described above, in the semiconductor integrated circuit of the present invention,
It is possible to cancel the reset without adding a new input terminal for inputting the signal for canceling the reset, and it is possible to cancel the reset without adding a new input terminal for inputting the signal for canceling the reset. Accurate measurement becomes possible. Note that, as a matter of course, it is also possible to measure the operating range including the power supply voltage detection section and the reset signal generation section. Therefore, for semiconductor integrated circuits, it is possible to inspect and guarantee that the reset circuit operates correctly at low power supply voltages, and it is now possible to reliably guarantee the quality of semiconductor integrated circuits at the time of shipment. It can have a great effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a reset circuit control unit built into a conventional semiconductor integrated circuit, and Fig. 2 is a block diagram of a reset circuit control unit built into a semiconductor integrated circuit according to an embodiment of the present invention that enables reset cancellation. The block diagrams of the circuit control section, FIGS. 3 and 4, are circuit diagrams showing specific examples of the reset canceling section in the integrated circuit of the present invention. A...Power supply voltage terminal, B...Power supply voltage detection section,
C...Reset signal generation unit, D...Input terminal to the integrated circuit internal reset circuit, E...Reset release control unit, F...Reset release signal input terminal, G...
Input signal detection section, H...Reset release signal generation section, _M1 to _M5 ...MOS resistors, _FF1 to _FF3 ...Flip-flop, N...NAND gate.

Claims (1)

[Claims] 1 A power supply voltage detection section, a reset signal generation section that generates a reset signal in response to the output of the power supply voltage detection section, a reset circuit section that performs a reset operation using the output of the reset signal generation section, coupled to an input terminal or an output terminal. A control signal detection unit that responds only to a control signal having a different form from a normal input signal or output signal and generates an output only when the control signal is applied, and the output of the control signal detection unit are input, and the reset 1. A semiconductor integrated circuit comprising a built-in reset release signal generator that outputs a signal for canceling circuit operation.