JPS6260193A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain multi-functions of writing operation by inhibiting the writing action of an input/output circuit for each bit in response to a column address strobe signal, etc. CONSTITUTION:Writing and reading actions are carried out for every four bits, etc. by memory arrays M-ARY1, M-ARY2, etc. via input/output circuits 100-103. Timing signals phi12 and phi13 are not produced from a timing generating circuit TG when the signals, the inverse of CAS2, and the inverse of CAS3, et. are kept at H among those column address strobe signals, the inverse of CASs 0-3 corresponding to the bits of an external signal. Thus the input/output circuits 102 and 103 are inactive and the writing actions are inhibited selectively for each bit. As a result, a multi-function writing operation is attained. Here the write-enable signal can substitute the column address strobe signal for selective inhibition of the writing actions.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in semiconductor storage devices such as dynamic RAM (random access memory) that performs writing/Vt extraction in units of multiple bits.

[Background technology]

For example, in dynamic RAM, in addition to methods that access in units of 1 bit, methods that access in units of multiple bits such as 4 bits or 8 bits have been proposed (for example, (See "Hitachi IC Memory Data Book" published in September 2016).

In such a dynamic RAM that is accessed in units of multiple bits, all bits in units of multiple bits are simultaneously written in one write cycle. Therefore, even when rewriting only a specific bit out of a plurality of bits that have already been stored, it is necessary to form a write signal for all the bits in the unit of the plurality of bits. For this reason, it is necessary to read out the stored information once before rewriting it, which slows down the processing speed of the stored information.The need to change a specific bit among multiple bits is reduced, for example, by When using a dynamic RAM and assigning red, blue, green, and luminance signals to each as a pixel signal for displaying a color figure on a CRT (cathode ray tube), when using it as a so-called video RAM, the above 4. Image processing often involves changing only a specific color or luminance signal of a bit signal.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device with multifunctional write operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the operation of an input/output circuit that writes/reads information in units of multiple bits is performed in units of bits using the column address strobe signal or write enable signal supplied in response to the above-mentioned write/read signals of multiple bits. selectively prohibited.

〔Example〕

FIG. 1 shows a block diagram of a dynamic RAM according to the present invention. The circuit elements constituting each circuit block in the figure are formed on a semiconductor substrate such as, but not limited to, single-crystal silicon using a known semiconductor integrated circuit manufacturing technique.

In this embodiment, the memory array is arranged in two parts, M-ARYl and M-ARY2, although this is not particularly limited. Each memory array M ARY 1
, M-A RY 2 is not particularly limited, but may be a two-intersection method (folded bit line or disin line method).
Consisted of. In each memory array, the column system (data line) signal line consists of a pair of complementary data lines arranged in parallel, two pairs of complementary data lines are considered as one set, and in the figure, the column system (data line) signal line is arranged horizontally. It will be extended as follows.

Row address selection #! A (word line, dummy word line) is connected to each memory array M-ARY1. M-ARY2
It is extended vertically at the end. Sense amplifiers SAI and SA2, during write/read operations,
selectively put into an operating state by a timing signal φpa;
The minute read voltage from the memory cell coupled to one data line by the word line selection operation is read as complementary data by referring to the reference voltage from the dummy cell coupled to the other data line by the dummy word line selection operation. Amplify the line to high/low level.

The row address buffer R-ADB responds to the supplied address signal AX supplied in synchronization with the row address strobe signal RAS, and outputs an internal complementary address signal ax,
ax and the next row address decoder R-DCR1
, R-DCR2.

The row address decoders R-DCRI and R-DCR2 are
The memory array M is decoded by decoding the complementary address signals ax and ax and synchronizing with the word line selection timing signal φX.
A selection operation is performed for one word line of -ARY l and M-ARY2 and a dummy word line.

The column address decoder C-ADH is not particularly limited to 41! Column address strobe (δ CAS
In response to the address signal AY supplied in synchronization with the AND signal of O-CAS3, internal complementary address signals ay and y are formed and transmitted to the column decoder C-1)CR.

Column decoder C-0CR receives the complementary address signal a
y, ding y-2 decode, data! Column switch circuit C-, which will be described later, is synchronized with -1 selection timing signal φy.
5WI, forms one column selection signal to be supplied to C-3W2.

Karanis 1' Tsuchi C-3'vV 1, C-3W
2 receives the selection signal formed by the column address decoder C.-DCR, and selects the memory array 4MARYl.
and two sets of common complementary data CDO corresponding to the two sets of complementary data lines in the memory M-ARY21,
CDL and CD2. Connect each to CD3. Common complementary data lines CDO, CDI and CD2. CD3 is arranged on the left and right sides of the column decoder C-0CR in the vertical direction of the drawing. These common complementary data lines CDO-CD3 are connected to input/output circuits l0O-IO, respectively.
2. These input/output circuits too-i.

3 consists of a data input circuit that performs a write operation and a data output circuit that performs a read operation. Therefore, the common complementary data lines CDO to CD3 are coupled to the output terminals of the corresponding data input circuits and the input terminals of the data output circuits.

Input/output circuit ■OO~103 is write enable signal W
In the case of a read operation in which E is at a high level, each data output circuit is activated by a predetermined timing signal (not shown), and in that operational state, the signals on the common complementary data lines CDO to CD3 are amplified and output to the external terminal DO. ~D
Send to 3.

At this time, each data input circuit is rendered inactive and placed in an output high impedance state.

In a write operation in which the write enable word WE is set to low level J, the data input circuit is selectively activated by the timing signals φ10 to φi3 generated according to the levels of the corresponding column address strobe signals CASO to CAS3. In this operating state, a write signal supplied from external terminals Do-D3 is transmitted to common complementary data lines CD0-CD3. At this time, the data output circuit is rendered inactive and placed in an output high impedance state.

The address power counter C0UNT forms a refresh address signal ax'. This address counter detects the column address strobe signal CASO before the row address strobe signal RAS is set to low level.
When at least one of
Inform the DB input. Row address buffer R-ADB
has a multiplexer function at its input section, and in the refresh mode generates internal complementary address signals ax and ax for refresh in response to the refresh address signal ax'. As a result, one word line and dummy word line of memory arrays M-ARYl and M-ARY2 are selected, sense amplifiers SAI and SA2 are activated, and a refresh operation is performed (CAS before RAS refresh).

The timing generation circuit 'rG receives a control signal RAS (row address strobe signal) supplied from an external terminal, a total of four CASO=CAS3 (column address strobe signals) provided corresponding to the input/output circuits I00 to 103, and Upon receiving WE (write enable signal), it forms and sends out the various timing signals necessary for memory operation according to the operation mode.

FIG. 2 shows a timing diagram for explaining an example of the operation of the RAM.

When the row address strobe signal RAS is changed from a high level to a low level, in other words, when it is set to a chip selection level, the row address buffer R-A is changed as described above.
DB and row decoder R-DCR are activated, and a row-related address selection operation is performed in response to an address signal AX supplied from an external terminal.

Next, for example, when writing only the storage signals supplied from the external terminals DO and DI out of the 4-bit write signals supplied from the external terminals DO to D3 into the corresponding memory cells, the above four bits are written. Among column address strobe signals CASO to CAS3, column address strobe signals CASO and CAS1 corresponding to the above two bits are set to low level, and the remaining two bits (D2
゜It will be done. When any one of the four column address strobe signals CASO to CA S3 is set to low level, in other words, the timing generation circuit TG outputs the column address strobe signals CASO to CA S3.
According to the AND signal of AS3.

Column address buffer C-ADB as described above.

The column decoder C-DCR is brought into operation and a timing signal fδ is generated for performing a column-system address selection operation in accordance with the address signal AV supplied from an external terminal.

When a write operation is instructed by setting the write enable signal WE to low level, the column address strobe signals CASO and C set to low level are
The data input circuit corresponding to AS L is activated by the generation of operation timing signals φ10 and φif, and transmits write signals corresponding to the external terminals Do and Dl to the common complementary data at CD O and CDI. . This causes the addressing to heat up the memory cells coupled to the common complementary data lines CDO and CDI. On the other hand, the column address strobe signals CAS2 and CA kept at the high level are
The data input circuit corresponding to S3 remains in an inactive state because its operation timing signals φi2 and φi3 are not generated, and is brought into an output high impedance state. As a result, the write signals from the external terminals D2 and D3 are invalidated, and the memory cells coupled to the common complementary data lines CD2 and CD3 by the above addressing retain their stored information. In this way, column address strobe signals CASO to CAS3
can be written in arbitrary bit units by selectively setting the column address strobe signal corresponding to the signal to be actually written to low level among the write signals supplied from the external terminal Do-D3. .

The control signals used to write to any bit of the four bits are four write enable signals WE, instead of the column address stove signal, which are selectively set to low level. It may be something.

〔effect〕

+11 RAM address strobe signal or write enable signal is provided corresponding to the number of bits of the write signal,
By forming the operation timing signal of the data input circuit in accordance with the above control signal, it is possible to obtain the effect that stored information can be rewritten only for arbitrary bits among a plurality of focus points.

(2) With (1) above, already stored memory information can be rewritten in arbitrary bit units, so there is no need to read memory information without rewriting, and the memory information can be processed at high speed. Such processing of the t9 information, which produces the above effect, is often necessary, for example, in a storage device that stores color graphic information, to change or modify the pixels constituting it.

(31-? Since it uses timing signals such as the dress strobe signal and fto enable signal,
For example, an operation cycle (so to speak, a dummy cycle) just for capturing one write signal, such as a method that supplies a signal indicating the presence or absence of writing from an address terminal or a data terminal, is no longer necessary, and all pins are The effect is that the writing and the digging of any of the bits can be performed in the same way.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. do not have. For example, instead of dividing the memory array into the two memory arrays described above, the memory array may be divided into four and an input/output circuit for realizing the write/read operations described above may be provided for each pine l-.

Furthermore, the plurality of bits described above may be configured such that eight pairs of input/output circuits are provided for eight pairs of common complementary terminal lines in addition to the four bits. A column address stave signal or write enable signal is provided. Further, when a write enable signal is used, the row address signal and column address (No. 3) may be supplied from independent external terminals.

Further, a specific circuit for realizing writing in units of bits may be any circuit as long as the state of the memory cell corresponding to the bit to which no writing is performed is substantially the same as that of the reading operation.

[Application field]

Although the invention made by the present inventor is applied to a dynamic type RAM, which is the field of application behind the invention, it is not limited thereto. It can be widely used in RAM or various types of RAM built into one-chip microcomputers.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining an example of its operation. M-ARYI, M-ARY2...Memory array, SAI
, SA2... sense amplifier, R-ADB... row at L
/S buffer, C-3WI, C-5W2...Column switch, C-ADB...Column address buffer, R-D
CRI, R-DCR2...Row decoder, C-DCR...
・Column decoder, C0UNT...address counter,
100~I03...Input/output circuit, TG...Timing generation circuit Fig. 1 Fig. 2 00ku3

Claims (1)

[Claims] 1. An input/output circuit that writes/reads information in units of multiple bits, and the input/output circuit according to a column address strobe signal or write enable signal supplied in correspondence with the multiple bit signals. 1. A semiconductor memory device, comprising: a control circuit for selectively inhibiting a write operation on a bit-by-bit basis. 2. Claim 1, wherein the semiconductor memory device constitutes a dynamic RAM.
The semiconductor storage device described in 1.