JPS62223890A - Dynamic type ram - Google Patents

Abstract

PURPOSE:To shorten a memory test by simultaneously writing plural bits consisting of optional bit patterns by plural input and output circuits. CONSTITUTION:The plural input and output circuits DI, DO making an address terminal an external terminal to plural common data lines are provided in a dynamic type RAM of X1 bit constitution consisting of the first address selection circuit for transmitting plural data lines respectively to the plural corresponding common data lines by the selection operation of word lines and data lines according to a specific address signal on the address signals supplied from the external terminal and the second address selection circuit for transmitting the plural common data lines to one input and output circuit by the decode output of a remaining address signal. By a control signal supplied from the external terminal or the combination thereof, the memory access for one bit unit or plural bit unit is changed over. Thereby, the memory test can be shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a dynamic RAM (random access memory), and is applicable to a dynamic RAM having a large storage capacity of about 1 Mbit, for example. It is related to effective technology.

[Conventional technology]

Among dynamic RAMs, in addition to those that perform writing and reading in units of 1 bit, there are also those that perform access in units of multiple bits, such as ×4 bits (for example, (See "Hitachi IC Memory Data Book" published September 1958).

By the way, with the progress of semiconductor manufacturing technology, the miniaturization of elements has been attempted, and it has become possible to develop dynamic type RA k technology with a large storage capacity such as approximately 1M vias. In a dynamic RAM having such a large storage capacity, as the storage capacity increases, a huge number of test steps are required to test write/read operations. Therefore, for example, a dynamic RAM with a large storage capacity of about IM bits in a ×1-bit configuration is added with a function to read data in a ×1-bit configuration using the address terminal. Digest of Technical Papers (ISS CCD ig)
est of Te+=hnical P ape
rs), pp. 238-239.

[Problem that the invention seeks to solve]

In the dynamic RAM described above, in the write operation, write data supplied from a common external terminal is a 4-bit write signal, so
Even in a read operation in bit units, only the same signal as described above is obtained, and for example, in a write/read test using a bit pattern such as a checker pattern, it is necessary to write in ×1 bit units.

An object of the present invention is to provide a dynamic RAM that enables faster write/read tests.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief summary of typical inventions disclosed in this application is as follows.

That is, a first address selection circuit transmits a plurality of data lines to a plurality of corresponding common data lines by selecting a word line and a data line according to a specific address signal among address signals supplied from an external terminal; , and a second address selection circuit that transmits the plurality of common data lines to one input/output circuit by decoding output of the remaining address signals. A plurality of input/output circuits are provided for two common data lines using address terminals as external terminals, and memory access is performed in units of 1, 1 bit, or multiple bits using control signals supplied from the external terminals or a combination thereof. This is to switch between the two.

[For production]

According to the above-mentioned means, it is possible to write a plurality of bits of an arbitrary bit pattern using a plurality of input/output circuits having address terminals as external terminals, so that it is possible to shorten the memory test.

〔Example〕

FIG. 1 shows a block diagram of a dynamic RAM according to the present invention. Circuit elements constituting each circuit block in the figure are formed on a semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In this embodiment, although not particularly limited, the memory array M
-ARYO column system (data line) signal line consists of 4 pairs of complementary data lines arranged in parallel1.Although not particularly limited, 4 pairs of complementary data lines are considered as one set, and in the figure, 4 pairs of complementary data lines are arranged in the spear direction. It is constructed using a two-intersection method (folded bit line or digit line method) arranged so as to face . The above four pairs of complementary data lines are connected to, for example, four memory arrays (
×4) respectively, and via a column switch circuit C8W that receives a column selection signal, which will be described later.
Four pairs of common complementary data lines run parallel in the vertical direction. It is combined with Dandanl, Dandan2 and Dandan3. In addition, in the same figure, a non-inverted common data line CDO and an inverted common data line CDO
Together, they are expressed as a common complementary data line dandan 0.

Although not particularly limited, the one memory array M A
RY has a storage capacity of about 256 bits, and has a total storage capacity of about 1 Mbit.

The row address selection line (word line, dummy word line) is connected to each memory array M consisting of the four memory arrays A.
-Arranged so as to face vertically in the ARY. During write/read operations and refresh operations, the sense amplifier SA is activated by a timing signal φpa, and receives a minute read ratio voltage from a memory cell coupled to one data line 1 by a word line selection operation.
By selecting the dummy word line, the complementary data line is amplified to a high level and a low level by referring to the basic voltage from the dummy cell coupled to the other data line.

The row address buffer R-ADB receives address signals AO to A9 supplied in synchronization with the row address strobe signal RAS, and receives an internal complementary address signal axQ.
~ form ax9. The above complementary address signal axQ~a
A specific bit of x9, for example, the upper 1 bit ax
The lower complementary address signals axQ to a:ζ8 except for 9 are sent to the next row address decoder RL)CR.

The row address decoder R-DCR (X4) decodes each of the complementary address signals axo-ax8 and selects one word line and a dummy word line in each of the four memory arrays in synchronization with the word line selection timing signal φX. forming a selection signal;

Column address buffer C-ADB receives address signals AO to A9 supplied in synchronization with column address strobe signal CAS, and receives internal complementary address signal ayQ.
~ form ay9. The above complementary address signal ayo~a
A specific bit of y9, for example, the upper 1 bit ay9
The lower complementary address signal ayQxay8 except for ``ayQxay8'' is sent to the next column address decoder C-DCR.

The column decoder C-DCR receives the complementary address signal a
ye-ay8 is decoded to form a column selection signal for coupling the four pairs of complementary data lines to the corresponding four pairs of common data lines O-p-3 in synchronization with the data line selection timing signal φy. do.

The column switch C8W receives the selection signal formed by the column address decoder C-DCR, and selects the four pairs of complementary data lines in the memory array M-ARY from the corresponding four pairs of common complementary data lines O2, DAN, 1. Connect to Dandan 2 and Dandan 3 respectively.

The remaining address signals ax9 and ay9 are supplied to the decoder circuit DEC, where selection signals maO to ma3 for the four pairs of common data lines dan0 to dan3 are formed. The selection signals maO to ma3 are used as selection signals for the main amplifiers MAO to MA3.

The common complementary data lines O and D3 are respectively coupled to the input terminals of the main amplifiers M A0 to MA3. These main amplifiers MA O-MA 3 are selectively activated by the selection signals maQ to ma3 and a timing signal (not shown), and are connected to the common complementary data line CD.
Amplify the 0-CD3 signal. These main amplifiers M
The output signals of AQ-MA3 are coupled to the input terminal of the first output circuit DOO. The output circuit DOO is used as one of the output circuits for ×1 bit output and the output circuit for ×4 pinto output. Therefore, the output circuit.

0 is coupled to the external output terminal Dout. Note that the main amplifiers MAO to MA3 receive the selection signal maQ.
It should be understood that the circuit includes a switch circuit that transmits the signal (write signal) in the opposite direction depending on ma3. Therefore, the common (wired-OR) output terminals of the main amplifiers MAO to MA3 are also coupled to the output terminal of the first input circuit DIO which receives the signal from the external terminal Din.

The input circuit DIO is used for ×1 bit input. Further, each of the main amplifiers MAO to MA3 has an output terminal and a write signal terminal corresponding to two types of signal transmission paths coupled to the circuits DIO and DOO.

In addition to three external control signals (write enable signals), the timing generation circuit TO is configured with an 18-pin package to distinguish between access in units of ×1 bit and access in units of ×4 bits. A signal of an empty bin NG in a 1M bit dynamic RAM is supplied, and a signal of an address terminal A9 is supplied as an output enable signal OE when accessing a memory with a ×4 bit configuration in order to identify write/read operations. Ru.

Among the address terminals prepared for the x1-bit configuration, an address terminal that is unnecessary during x4-bit access, such as the most significant address terminal A9, is used as a control terminal during x4-bit access.

Although not particularly limited, the empty bin NC is usually provided with a circuit ground potential through a pull-down resistor.

Since the vacant terminal (NC) and the most significant address terminal are used to instruct and control access to x4 bits, access switching between x1 bit and x4 bit can be performed without increasing the number of terminals. Note that in the case of f5 where there is no empty bin NC, a dedicated bin may be provided or the address terminal or the like may be used. , the timing generation circuit TG receives these signals, and forms and sends out the various timing signals (f) necessary for identifying the operation mode and corresponding memory operation. In order to enable memory access in the main amplifier MAO or MA3,
The following input/output circuits are provided for each.

A second input circuit DIO' is added to the first output circuit 1DOO, which is used for memory access in units of 1.times.bits, thereby constructing one input/output circuit.

This input/output circuit (DOO1D10'') is provided in one-to-one correspondence with the main amplifier MAO.The other main amplifiers MAI to MA3 each have three input/output circuits consisting of input circuits Dll to DI3 and output circuits D01 to DO3. Circuit (DII, Dol) or DI3゜Do
3) are provided in one-to-one correspondence. These input/output circuits are used during ×4 bit access.

The input/output circuit (Dll, DOI) or DI3. D
O3) is an external terminal coupled thereto, although there is no particular restriction, 6 to A8 are used as address terminals.

From the above, address terminals A6 to A8 are used in common as external terminals corresponding to data DI to D3, in addition to supplying the above-mentioned address signals.

The address terminal A9 is not used for memory access in units of ×4 bits, but is used as the output enable signal OB as described above.

The data output terminal Dout is shared as an external terminal corresponding to the data Do when accessing the memory in the ×4 bit configuration.

Next, with reference to the timing diagram in FIG.
An example of memory access operation in bit units will be explained.

Prior to the row address strobe signal RAS, the terminal NC
is raised to a high level. Further, when instructing a write operation, the terminal A9 is set to a high level. As mentioned above, when the terminal NC is at a high level, the timing generation circuit TG puts the input circuit DIO in a non-selected state, and also recognizes the terminal A9 as an output enable signal δ〒-, and each signal is activated by the high level of the signal surface. Output circuit DOO or DO3
In other words, the output is placed in a high impedance state.

At the falling edge of the row address strobe signal RAS, the timing generation circuit TG generates a timing signal to take the address signal 'X supplied from the external terminals AO to A8 into the row address buffer R-ADB as a row address signal. Row address buffer y
Row address selection circuits such as R-ADB and row address decoder R-DCR select row address selection circuits (word line Performs selection operations (selection operation, sense amplifier amplification operation).

Next, when the column address strobe signal CAS rises from the high level to the low level, the timing generation circuit TG generates a timing signal to take in the address signals supplied from the external terminals AO to 88 as the column address signal Y. Column address buffer C-A
A column-system address selection circuit consisting of DB and a column address decoder C-DCR receives the above-mentioned address signals ayQ to ay8 and a timing generation circuit TG.
A column system (data line selection operation) is performed in response to a timing signal generated by the column selection operation. As a result, the four pairs of common data 1, 0 to 3 are coupled to the corresponding 4 pairs of complementary data lines of the memory array M-ARY.

During a write operation as shown in E, the write enable signal WE is connected to the column address strobe signal CA.
It is set to low level in synchronization with SO low level.

As a result, the timing generation circuit TG generates a timing signal that puts the input circuits DIO to DI3 into an active state after the column selection operation. As a result, 1. After supplying the column address signal Y, the terminals Dout and AS
The 4-bit signal Di supplied from A8 through A8 is taken into each input circuit DIO' through DI3.

Each of the input circuits DIO'' to DI3 amplifies the taken-in write signal and transmits the amplified signal to the common complementary data O to D3 via a switch circuit included in each main amplifier MAO to MA3.

As a result, 1, writing to the memory array M-ARY coupled via the column switch circuit C8W is performed.

In addition, during a read operation, after the write enable signal WE is set to high level and the column address strobe signal CAS is set to low level, in other words, after the column address signal Y is taken in, the terminal A9 is
This is performed by setting the output enable signal OE to a low level (1) to put the main amplifiers MAO to MA3 and the output circuits DOO to DO3 into the operating state.

In addition, the memory access operation in units of ×1 bits is performed by setting the terminal NC to a low level.
' and three input/output circuits (Dll.

DOI) or DI3.003) is set to a non-selected state, and only a 1-bit signal according to a row/column address signal from address terminals AO-A9 is written or read.

In place of the empty bin NG, when the row address strobe signal RAS changes from a high level to a low level, the column address strobe signal CAS and the write enable signal WE are set to a low level.
It may also be used to identify the memory access mode in units of 4 bits.In this case, contrary to capturing the column address signal in units of ×1 bit, the column address is changed from the above state (low level) to high level. By capturing the column address signal in synchronization with the rising edge of the strobe signal CAS, the latch circuit for storing the identification signal may be unnecessary.

The effects obtained from the above examples are as follows. In other words, [Effects] (1) Selecting a word line and a data line in response to a specific address signal supplied from an external terminal causes a plurality of data lines; and a plurality of corresponding common data lines. A dynamic RAM with a ×1 bit configuration, which includes a first address selection circuit that transmits the data, and a second address selection circuit that transmits the plurality of common data lines to one input/output circuit by decoding and outputting the remaining address signals.
A plurality of input/output circuits are provided with address terminals as external terminals for the plurality of common data lines, and memory access is performed in units of 1, 1 bit, or multiple bits by control signals supplied from the external terminals or a combination thereof. Switch. As a result, 1. writing of a plurality of bits consisting of an arbitrary bit pattern can be performed simultaneously by the plurality of input/output circuits, so that it is possible to shorten the length of the memory test.

(2) The number of external terminals is increased by using an empty bin and one unused address bin in a 1M-bit dynamic RAM consisting of an 18-bin package as a signal to switch to the memory access mode in units of multiple bits. It is possible to achieve the effect that the above-mentioned operation mode switching can be realized without any trouble.

(3) By using the data output circuit or data input circuit of the Xi bit configuration also when accessing memory in units of multiple bits, it is possible to achieve the effect of simplifying the circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, input circuit DI
O' is omitted, and the input circuit DIO is an output circuit for ×4 bit output.

In addition, in FIG. 1, by arranging memory arrays M-ARY on the left and right sides of the column address decoder C-DCR, and providing eight pairs of common complementary data lines. The Q-memory access method is not limited to ×4 bits, such as ×8 bits, and various embodiments can be adopted in units of multiple bits.Additionally, the address signal supplied to the decoder circuit DEC can be used as a column address. It is also possible to form a counter circuit incremented by the strobe signal CAS and add a nibble mode in which a 4 bit signal is serially written or read.

The memory array may adopt a half precharge method (dummy cellless method) in which complementary data lines are precharged to Vcc/2 and this precharge signal is used as a read reference potential.

This invention can be widely used in dynamic RAM.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. That is, a dynamic RAM having a plurality of ×1 bit configurations is provided with a plurality of input/output circuits whose external terminals are address terminals for the plurality of common data lines, and control signals supplied from the external terminals or their Depending on the combination 1
, switches memory access in units of one bit or multiple bits. As a result, 1. writing of a plurality of bits consisting of an arbitrary bit pattern can be performed simultaneously using the plurality of input/output circuits, so that the memory test can be shortened.

[Brief explanation of drawings]

FIG. 1 is an internal configuration block diagram showing an embodiment of a dynamic RAM according to the present invention, and FIG. 2 is a timing diagram showing an example of its operation. M-ARY...Memory array, SA...Sense amplifier,
C8W...Column switch circuit, R-ADB...Row address buffer, C-ADB...Column address buffer, R-DCR...Row address decoder, C-DCR
...Column address decoder, DEC...Decoder circuit, MA O-MA3...Main amplifier, DIO, DIO
'~DI3...input circuit, DOO~D03...output circuit, Fig. 1

Claims (1)

[Claims] 1. Transmitting a plurality of data lines to a plurality of corresponding common data lines by selecting a word line and a data line according to a specific address signal among address signals supplied from an external terminal. a second address selection circuit that transmits the plurality of common data lines to one input/output circuit by decoding and outputting the remaining address signals;
and a plurality of input/output circuits provided between the plurality of common data lines and the address terminal, the first and second address selection circuits select one bit based on a control signal supplied from an external terminal or a combination thereof. A dynamic RAM comprising an operation mode in which writing and reading are performed in units of , and an operation mode in which writing and reading are performed in units of a plurality of bits through the plurality of input/output circuits. 2. The above write and read operation modes in units of 1 bit use independent external input terminals and external output terminals, and the output circuit whose output is coupled to the external output terminal is equipped with an input circuit. 2. The dynamic RAM according to claim 1, wherein these input/output circuits are also used in the write and read operation modes in units of a plurality of bits.