JPS6089891A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To relax the limit of a maximum value of a read time of a cell and to attain low power consumption of a memory and high speed access by inactivating a row line after cell read and selecting the identical row line again and performing rewrite when the write is executed. CONSTITUTION:One row in row lines W101-W10M is selected by a selection circuit C10 in a memory matrix M100, a memory cell at cross point of column lines B101-B10N is read to each column line and a data is transferred to latch circuits L101-L10N. Every time a signal phi2 is given once, a selection circuit C11 continues to select different column lines. After a required data is accessed, the chip is activated again by using the phi2, the data of the L101-L10N is transferred to the column lines B101-B10N by the control of the signal R/S, the row line selected at read is selected again and rewrite is conducted to the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and particularly to a memory that is partially serially accessed.

In recent years, the capacity of semiconductor memories has increased due to the development of MOS-type dynamic memories, and the cost of semiconductor memory has rapidly declined, allowing them to be used in many fields. Particularly in the field of image processing, one pixel element on a cathode ray tube corresponds to one bit of memory, and the content written in memory is output as an image to the cathode ray tube, thereby improving the function of image representation. There is. Due to the structure of the cathode ray tube, high-speed serial access is required for such memory access, and the read cycle for one pixel is set at 50 to 7 Qns. However, the memory cycle is slow at 300 to 4001 g, so techniques such as interleaving are used. ◎Memory is usually configured in an M@N matrix, with N pieces arranged in one row. Cell data is read from the memory cells to N column lines connected to each cell, and then one of the column lines is connected to the outside to perform read/write operations. In recent address multiplex type memories, it is possible to randomly read out information from one row of memory cells drawn out to each column line during one memory cycle, which is called l-page mode. The advantage of this page mode is that the access cycles per pit are 150 to 2.
In a normal cycle, it is possible to read data from a memory cell to a column line at high speed and with low power consumption. However, in dynamic memory, the maximum time that a memory cell is read (hereinafter referred to as active width max)
) is specified, and it is not possible to continue accessing the memory beyond the active width max. This value is approximately 10 μS and 200 cycles in page mode.
In ns, only about 50 bits can be accessed. 64
In a bit memory, there are 256 column lines, which are accessed approximately four times. - In a cathode ray tube, it is necessary to provide data to the pixels in the horizontal direction of the screen at certain intervals, and when the active width exceeds the maximum active width that is accessed by dividing one page as described above, the memory becomes inactive. As a result, the data is interrupted and it is not possible to output the data for a certain period of time.Therefore, in order to eliminate such interruptions in the data, the memory access control becomes extremely complicated.

The purpose of the present invention is to provide a dynamic memory in which memory cells arranged in one row are sequentially and serially read out.
The object of the present invention is to provide a memory which eliminates the limitation on the maximum active width.

The following will be explained according to examples.

FIG. 1 shows one embodiment of the invention, and FIG. 2 shows the signals controlling the embodiment.

The memory matrix M100 is configured with M rows and N columns, one row of the row lines W101 to wlOM is selected by the selection circuit CIO, and the memory cells at the intersections of the column lines BIOI to BIQN are read out to each column line and each Data is transferred to latch circuits LIOI-LION connected to the column lines.

The above operation is executed at time Tl by the signal φ1 shown in the second factor, and when φl becomes a reset state (set to a level state), the selected row line becomes a non-selected state and the memory cell is closed. After that, at time T, the column selection circuit C is activated by the input signal φ3.
One column line is selected by switch circuit C13, and the column line is connected to input/output circuit C1 by switch circuit C13, and the signal of the selected latch circuit is output to the output. It is executed by rewriting information.

- For each signal φ2, the selection circuit C1l is different □
Continue selecting the column line. After accessing the necessary data, the chip is activated again at time T3 and read/read.
Silatch circuit LI controlled by store signal R/8
The data of OI-L1ON is transferred to the column lines B101 to BIQN, and then the row line selected at the time of reading is selected again and rewritten to the memory. By performing such □ operation, the active rfJ'max of the memory becomes the time '
It is possible to access one row's worth of cell information even if it is small because it only needs to be done between i' and 'r and between times T3 and T4. The configuration of the dynamic selection circuit Cxi can be of various types, such as a decoder determined by an external input address, a decoder determined by an address signal derived from an internal counter, or a shift register that transfers a selection signal.

In addition, the latch circuits L101 to LIQN and each column line B101 to W
If ION connectivity/disconnection can be controlled,
It is also possible to perform a cell refresh or ledge crystal while accessing latch data.

FIG. 3 is another example of the present invention, which uses a one-transistor type memory. The row line W and the dummy row line DW are selected by the row selection circuit, and the information of the cell C1l and the dummy cell CZZ is read out as minute signals to a pair of column lines B and B, which are precharged in advance. And when the signal φS is leveled, the transistor Qs Qz
If the ON state is maintained, the signals read out to the column lines B and B are transferred to the nodes Nl and N2. After that, the signal φ makes the second transistor Q7 conductive and discharges the nodes N, , N, @here, the node N1. Since there is a signal difference, that is, a potential difference in N1, a difference occurs in the conduction resistance of the transistors Qs, Q, -.
Node N! There is a difference in the discharge speed of N2, and the m width is completed by positive feedback by the 7 lip-flop connection. After the width increase is completed, the second transistor Qs and Qa are brought into a non-conductive state by φS, so that the cell C! The signal of I is input to the sense amplifier C3, and then the switch signal Yi makes the transistors Qs and Qs conductive, and the correction input/output line I
10. By connecting it to I10, the SiSense amplifier q■
1 iL per day. It becomes possible to connect the stored cell C2, (7) information to the outside. In other words, time T in Figure 2
During I-T, the cell is read out and latched into the sense amplifier CZS, and from time 1 to 2, external connections are made between the latched signal and the outside.Therefore, as in the previous embodiment, from time T2, the row line W and the dummy row line DW are connected. can be deactivated. Now, the signal externally written after time T2 is once transferred to the sense amplifier C18, but at time T3, writing to the sense amplifier starts, but the correction column that has been precharged again 1 to 11BB, the signal φ, φ is passed through the transistor Q7. By making Qs and Qa conductive, it is possible to transfer the signals of nodes N and N to column line BB, and therefore by selecting the same word line, cell C! In the above explanation, the relationship between the signal φ and the signal φ during reading is that after the amplification is completed with the signal φ1, the transistors Qs and Qa are connected to the signal φ1.
t-If made non-conductive, the corrective column lines B and B will be connected to the cell C.
Since rewriting is performed to the cell Co by the row line W to set the potential to 1.0 according to the information of Wt, if writing is not performed during the input/output cycle from time T2 to time T3. There is no need to rewrite the data. However, due to signal φ8, transistor Q3. After Q4 is made non-conductive, sense amplifier C23
Activation destroys cell information, so a rewrite cycle must be performed. However, if the latter method is adopted, there is almost no need to re-precharge the column lines, so power consumption can be reduced.

By using the present invention, low-power, high-speed memory access is possible without limiting the maximum active width in a memory that is primarily serially accessed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the invention, FIG. 2 is an input signal waveform diagram of the invention, and FIG. 3 is a diagram showing another embodiment of the invention. Mloo・・・Memory Matrix Agent Patent Attorney Susumu Uchihara Tobe Shino I Sekiman 2 Kuni

Claims (1)

[Claims] In a semiconductor dynamic memory, each column line has a latch circuit, and after reading a memory cell, the row line is inactivated, and the input/output is 2.
Border. A semiconductor memory characterized in that when writing is executed after being written in a circuit, the same row line is selected again and the writing is performed again in row 5.