JPS6258592B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device that improves the quality of reproduced images. One of the solid-state imaging devices is an interline transfer (IT) CCD image sensor.
There is a sensor. CCD _ _
As is well known, a semiconductor device has a plurality of electrodes arranged continuously on an insulating layer formed on a semiconductor substrate, and by applying a desired voltage to the plurality of electrodes, the semiconductor device A depletion layer is generated at or near the substrate surface, and signal charges formed by electrical or optical means are accumulated in the depletion layer, or the signal charges are generated in any direction along the semiconductor substrate surface or near the semiconductor substrate surface. It has a function that allows you to transfer. Figure 1 shows a schematic diagram of the IT-based CCD image sensor. In the figure, 1ij (i=1, 2,...,
m, j=1, 2, . The photosensitive sections 1ij undergo photoelectric conversion along the array of the photosensitive sections 1ij, and then a vertical CCD 2i for reading out the accumulated signal charges and an overflow for removing excess signal charges photoelectrically converted in the photosensitive sections 1ij. There are four drains (over flow drain: OFD). An overflow control electrode 5i is provided between the OFD 4 and the photosensitive portion 1ij to ensure that excess signal charges are removed from the OFD 4. The signal charge accumulated in the photosensitive section 1ij is transferred to the vertical CCD 2i, and then transferred column by column to the horizontal CCD 3 shown in the figure, and then transferred within the horizontal CCD 3.
It is read out from the output unit 6 in chronological order. The vertical CCD 2i and the horizontal CCD 3 can transfer signal charges by applying single-phase, two-phase, three-phase or four-phase clock pulses to the transfer electrodes. Here, since the vertical CCD 2i is an ineffective portion for light incidence, it is necessary to maximize the amount of signal charge that it can handle and minimize the area it occupies. For this purpose, a four-phase drive type is preferable. However, compared to other driver circuits, especially 2-phase and single-phase types, this 4-phase drive type requires a higher original oscillation frequency when creating the driver circuit, and the circuit itself has to be adjusted to ensure the phase relationship between each phase. Power consumption increases and complexity increases. This is a vertical CCD that will be explained later.
This becomes a big problem when operating at high speed. In this IT-CCD image sensor, while signal charges are accumulated in the photosensitive section 1ij, the adjacent vertical CCD 2i transfers the signal charges of the previous field column by column to the horizontal CCD 3 and reads them out. For example, the signal charges in the photosensitive sections 1 ₁₁ , 1 ₂₁ , . . . 1 m ₁ that are farthest from the horizontal CCD 3 stay in the solid-state imaging device for a time close to one field period in addition to the actual storage time. and,
The signal charges accumulated in these photosensitive areas are vertically
Before the signal charges of the next field are read out by the CCD 2i and transferred to the vertical CCD 2i by the photosensitive section 1ij, no signal charges must remain in the vertical CCD 2i. However, in reality, signal charges are formed within the semiconductor substrate forming the solid-state imaging device due to light incident on the photosensitive section, so a small amount of signal charges diffused within the semiconductor substrate leak into the vertical CCD 2i. It's gone. This small amount of leakage of signal charges causes bright lines in the vertical direction on the reproduced image, that is, vertical smear. This becomes noticeable when capturing an image of a subject with high brightness, so it significantly changes the image quality. In order to reduce this vertical smear, the leakage charge that causes the above-mentioned vertical smear must be swept out at high speed before the signal charge is transferred from the photosensitive section 1ij to the vertical CCD 2i during the vertical blanking period. Since this high-speed sweep must be performed during the vertical blanking period, it must be performed at least 20 times faster than the signal charge readout operation during the valid period. If the vertical CCD is of a 4-phase drive type in order to have a large dynamic range, this high-speed sweep will also be a 4-phase drive type. In this case, as mentioned above, there are disadvantages in that a high original oscillation frequency is required, and in order to maintain the phase relationship between each phase, the circuit becomes complicated and power consumption increases. A conventionally well-known four-phase drive type CCD will be explained using FIG. FIG. 2 is an explanatory diagram of the cross-sectional structure of a typical four-phase drive type CCD. This is an N-channel CCD that treats electrons as signal charges. The vertical CCD of the IT-CCD uses a buried channel type CCD that transfers signal charges within a semiconductor substrate with high signal charge transfer efficiency. Therefore, this explanation will also be made using the embedded channel CCD. As shown in the figure, about 1 μm is placed on the P-type semiconductor substrate 11.
An N ⁺ layer 12 having a thickness of about m is provided. The N ⁺ layer 12
A first insulating film 13 is formed on the first insulating film 13, and for example, first layer poly-Si electrodes 14 ₁ , 14 are formed on the first insulating film 13 .
₂ ,... and second layer poly-Si electrodes 15 ₁ , 15 ₂ ,...
form. The first layer poly-Si electrode 14 ₁ , 14
₂ and the second layer poly-Si electrodes 15 ₁ , 15 ₂ , . . are electrically insulated by a second insulating film 16 .
For example, if the electrode 15 ₁ is a φ ₁ electrode, the following electrode 14
₁ , 15 ₂ , and 14 ₂ are φ ₂ , φ ₃ , and φ ₄ electrodes. The 4-phase drive type CCD has φ ₁ , φ ₂ , φ ₃ , φ
One cell is composed of _four electrodes, and a plurality of cells are arranged in the direction of signal charge transfer. This signal charge transfer is performed by applying four-phase clock pulses φ ₁ , φ ₂ , φ ₃ , and φ ₄ as shown in FIG. Incidentally, in order to quickly sweep out the leakage charge that causes vertical smear, it is desirable to use a vertical CCD single-phase drive. However, for example, in the structure shown in Fig. 2, the φ ₁ and φ ₂ electrodes are connected to form the φ ₁ ' electrode, the remaining φ ₃ and φ ₄ electrodes are connected to form the φ ₂ ' electrode, and the fourth
Even if the single-phase clock pulses φ ₁ ' and φ ₂ ' shown in the figure are applied to these, the signal charges cannot be transferred in a certain determined direction. Therefore, either the CCD structure shown in FIG. 2 should be changed to a single-phase drive type, or the _φ2 and _φ4 electrodes should have an offset voltage for the single-phase clock pulses _φ1 ' and _φ2 ' in FIG. It is conceivable to use pseudo-single-phase drive, but the former would reduce the dynamic range of the vertical CCD, and the latter would complicate the circuit. The present invention has been made in view of the above points, and is
-Vertical CCD in CCD image sensor etc.
The object of the present invention is to provide a solid-state imaging device in which four-phase driving is performed during the vertical effective period, and single-phase driving is performed for high-speed readout to reduce vertical smear during the invalid period. In the present invention, the vertical CCD is basically 4
It is of a phase drive type, and signal charges are transferred using clock pulses whose phases are shifted by π/2 in a state where wells are formed under at least two consecutive electrodes of one transfer stage (four electrodes). As shown in Figure 8, when looking at the amount of signal charge that can be transferred per one transfer stage, the amount of signal charge that can be transferred per transfer stage is 1/4 stage in the case of two-phase drive, and 1/4 stage in the case of three-phase drive.
In contrast to the 1/3 stage, in the case of this 4-phase drive
This is because it has a 1/2 step, so the dynamic range is larger than other drive systems. In FIG. 8, the shaded area is the electrode area within one vertical CCD stage where signal charges are accumulated. In the case of two-phase drive, as is well known, charge transfer is performed by changing the potential as shown in FIG. The structure is such that when the same voltage is applied to the first to fourth electrodes, the substrate surface potentials under the first and third electrodes are slightly different from those under the second and fourth electrodes. That is, a potential step that defines the charge transfer direction is formed on the substrate surface by a well-known method such as changing the impurity concentration on the substrate surface or changing the thickness of the insulating film. Then, high-speed readout to reduce vertical smear is performed by short-circuiting two consecutive electrodes and driving in a single phase. That is, high-speed transfer is necessary to sweep out the leakage signal charge in an extremely short period within the vertical blanking period, but it is difficult to increase the speed with four-phase drive, and the power consumption is also large. Therefore, to sweep out this leakage signal charge, single-phase drive is used, which can easily increase the speed and consume less power. Single-phase drive has lower transfer efficiency than other drive methods, but as mentioned above, by selecting the substrate surface potential to generate an electric field in the charge transfer direction and driving with high-speed clock pulses,
Leakage signal charges are effectively swept away. Furthermore, by increasing the number of single-phase clock pulses to the vertical CCD transfer stage or more, signal charges can be swept out more effectively. As a result, vertical smear can be effectively reduced without reducing the dynamic range of the vertical CCD, and with a simple circuit configuration and low power consumption single-phase drive. An embodiment of the present invention will be described below. FIG. 5 is an explanatory cross-sectional view of a vertical CCD in an IT-CCD image sensor according to an embodiment of the present invention. The overall configuration of the image sensor is the same as that shown in FIG. In the sectional view of FIG. 5, parts corresponding to those in FIG. 2 are designated by the same reference numerals as in FIG. 2, and detailed explanation thereof will be omitted. The difference from FIG. 2 is that the second layer poly-Si electrodes 15 ₁ , 15 ₂ ,...
This is because N ⁺⁺ layers 17 ₁ , 17 ₂ , etc. having a slightly higher impurity concentration than the N ⁺ layer 12 are formed on the surface of the N ⁺ layer 12 below the N + layer 12 . Figure 6 shows the first layer poly-Si electrode 14.
₁ , 14 ₂ , ... and second layer poly-Si electrode 15 ₁ , 1
5 ₂ , . . . shows the dependence of the minimum potential V _n on the applied voltage V _G in the lower N ⁺ layer 12. The solid line is N ⁺⁺ layer 17 ₁ ,
17 ₂ ,... second layer poly-Si electrode 15 ₁ , 1
5 ₂ , . . _. The _dotted lines indicate the positions of the first layer poly-Si electrodes 14 ₁ , 14 ₂ , . . . Here, the first layer poly-Si electrodes 14 ₁ , 14 ₂ ,... and the second layer poly-Si electrodes 15
For example, V _n at ₁ , 15 ₂ , ... is for each V _G
Make sure to create a slight difference of about 0.5V. Moreover, the first layer poly-Si electrodes 14 ₁ , 14 ₂ ,...
Switches 18 ₁ , 18 ₂ , . . . are provided to short-circuit two adjacent second layer poly-Si electrodes 15 ₁ , 15 ₂ , . In such a configuration, the vertical CCD is
Phase drive. At this time, N ⁺⁺ layers 17 ₁ , 17
Since the impurity concentration of the N ⁺ layers 17 ₁ , 17 ₂ , . . . is only slightly higher than that of the N ⁺ layers 12, the dynamic range hardly changes compared to the case where the N ++ layers ₁₇ 1 , 17 2 , . And high-speed reading of the invalid period to reduce vertical smear is performed by switch 18.
₁ , 18 ₂ ,... are closed and φ ₁ and φ ₂ electrodes and φ
₃ and _φ4 electrodes are connected to each other and single-phase drive is performed. FIG. 7 is for explaining this high-speed reading. Here, the driving pulse voltage waveforms applied to the _φ1 electrode and the _φ3 electrode are shown. During the effective period, four-phase clock pulses are applied independently to the φ ₁ , φ ₂ , φ ₃ , and φ ₄ electrodes. Next, before transferring signal charges from the photosensitive section 1ij to the vertical CCD 2i during the invalid period, the _φ1 and _φ2 electrodes and the _φ3 and _φ4 electrodes are connected and driven in single phase to perform high-speed reading. During the invalid period, the same high-speed pulse is applied to the _φ1 and _φ2 electrodes, and the same DC voltage is similarly applied to the _φ3 and _φ4 electrodes.
The figure shows the driving pulse voltage waveforms applied to the _φ1 and _φ3 electrodes. Normally, in order to perform single-phase driving, the difference in Vm between the first layer poly-Si electrode and the second layer poly-Si electrode shown in FIG. 6 needs to be about 3 to 4 V. However, if four-phase driving is performed with such a difference in Vm, the dynamic range of the vertical CCD will be reduced. In the present invention, leakage charges can be sufficiently removed even if the single-phase clock pulse voltage value for high-speed reading is made small. Further, the effect remains the same even if the clock pulse voltage waveform is not a rectangular wave but a sine wave. This means that the voltage waveform can be highly distorted, allowing the circuit for vertical smear mitigation to consume less power and be simpler. In single-phase driving performed using only a minute difference in Vm as shown in FIG. 6, the maximum amount of signal charge that can be reliably transferred is small, as is usually said. However, the reason why vertical smear can be significantly reduced is that this high-speed readout does not require that the leakage charges from each stage of the vertical CCD2i be read out without mixing at each stage;
This is because the leakage charge remaining in the CCD 2i is required to be removed in the vertical invalid period regardless of the transfer efficiency. Therefore, even if the amount of charge that can be handled is small, vertical smear can be significantly reduced by generating some kind of electric field in the direction in which charge is desired to be transferred. From the above explanation, for this high-speed readout, the number of single-phase clock pulses to be applied is
Vertical smear can be more reliably reduced by increasing the number of stages to more than . This vertical smear is reduced the faster the high speed readout is performed. For example, since this high-speed readout must be performed within the invalid period (approximately 10% of one field period), if it is performed at 250 kHz, the one-stage transfer time will be 4 μsec, compared to the 4-phase clock pulse period of 60 μsec applied during the valid period. vertical smear is reduced to 1/15. Therefore, if this high-speed readout is performed at 1 MHz, for example, the reduction will be reduced to 1/60. The single-phase drive type is extremely advantageous compared to other drive types in terms of such speed increases. If the speed can be increased easily in this way, high-speed reading for vertical smear reduction will be possible not only once but multiple times during the invalid period. If multiple high-speed readouts are possible in this way, vertical smear can be more reliably reduced, and the single-phase clock pulse voltage amplitude value for high-speed readout shown in Figure 7 can be further reduced, resulting in lower power consumption. can be achieved. As described above, in the solid-state imaging device of the present invention, vertical smear can be significantly reduced by reducing power consumption and using a simple circuit without reducing the dynamic range for signal charges in the vertical CCD. In the above embodiment, the Vm below the first layer poly-Si electrodes 14 ₁ , 14 ₂ , . . . is larger than the Vm below the second layer poly-Si electrodes 15 ₁ , 15 ₂ , . It may be. for that purpose,
Second layer poly-Si electrode 15 ₁ , 15 ₂ ,... N ⁺ below
An N ^- layer having a lower donor impurity concentration than layer 12 may be provided. In this case, for single-phase drive, the fifth
In the figure, it is sufficient to connect φ ₂ and φ ₃ and φ ₄ and φ ₁ , thereby achieving the same reduction in vertical smear as in the above embodiment. In addition, as a means of creating a difference in Vm, the film thickness of the first insulating film 13 is changed between the thickness of the first insulating film 13 under the first layer poly-Si electrodes 14 ₁ , 14 ₂ , ... and the layer under the second layer poly-Si electrodes 15 ₁ , 15 ₂ , etc. It is also possible to make them different under...
Furthermore, the description of the above embodiment is based on the photosensitive section 1ij in FIG.
OFD 4, OFD control electrode 5i, and photosensitive section 1ij
Although there is no mention of the area necessary for moving from the CCD 2i to the vertical CCD 2i, any area that can perform basic imaging operations may be used. For example, although the case where poly-Si is used as the electrode of the vertical CCD 2i has been described, it goes without saying that other conductive electrode materials may be used. Furthermore, the photosensitive section may be formed not only by a photodiode provided on the same substrate as the semiconductor substrate, but also by a photoconductive film formed electrically connected to the photodiode. Even in a solid-state imaging device using a photoconductive film, when a light spot of extremely high light intensity is incident, signal charge leakage to the vertical CCD as described above occurs, and the present invention is effective in reducing this leakage. In FIG. 7, the amplitude of the single-phase clock pulse applied during the invalid period is made to be smaller than the amplitude of the four-phase clock pulse applied during the valid period, but it goes without saying that they may be the same.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram of an interline transfer type CCD image sensor, and Figure 2 is a conventional vertical type CCD image sensor.
3 and 4 are typical clock pulse voltage waveform diagrams for four-phase and single-phase driving, respectively. A cross-sectional structure explanatory diagram, FIG. 6 is a diagram showing the dependence of the minimum potential V _n under the first and second layer poly-Si electrodes on the applied voltage V _G , and FIG.
The figure also shows the clock pulse voltage waveform applied to the transfer electrode of the vertical CCD, Figure 8 shows a comparison of signal charge accumulation in each drive method, and Figure 9 shows the case of two-phase drive. FIG. 3 is a diagram showing the state of charge transfer. 1ij...Photosensitive section, 2i...Vertical CCD, 3...Horizontal CCD, 4...Overflow drain, 5i
... Overflow drain control electrode, 6 ... Output section, 11 ... P-type semiconductor substrate, 12 ... N ⁺
Layer, 13, 16...Insulating film, 14 ₁ , 14 ₂ ...
1st layer poly-Si electrode, 15 ₁ , 15 ₂ ... 2nd layer poly-Si electrode, 17 ₁ , 17 ₂ ... N ⁺⁺ layer, 18
_{1,18 2} ...Switch.

Claims (1)

[Claims] 1. A photosensitive section arranged in a matrix on a semiconductor substrate to accumulate signal charges generated by photoelectric conversion;
A charge transfer section that transfers and reads signal charges from these photosensitive sections in one direction along the arrangement thereof is formed in an integrated manner, and the charge transfer section is continuously formed on the semiconductor substrate with an insulating film interposed therebetween. In a solid-state imaging device in which one cell is constituted by first to fourth electrodes, the charge transfer unit is configured to change the substrate surface potential under the first and third electrodes when the same voltage is applied to the four electrodes. A potential difference that defines the charge transfer direction is formed between the substrate surface potential under the second and fourth electrodes, and during a period when the signal charges accumulated in the photosensitive section are read out, the first to fourth electrodes are The phase is sequentially π/
Before transferring signal charges from the photosensitive section to the charge transfer section by applying clock pulses shifted by 2 and performing four-phase driving in which charge transfer is performed with wells formed under at least two consecutive electrodes. A solid-state imaging device characterized in that two consecutive electrodes of the first to fourth four electrodes are short-circuited during a period to perform single-phase driving using a higher frequency clock pulse than in the case of the four-phase driving.