JPS6058779A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a signal output voltage with less loss by not transferring the stored photoelectric charge of a photo diode to a signal reading part but holding the photoelectric charge in each picture element cell to read out a signal when the stored photoelectric charge of the photo diode is read out. CONSTITUTION:When a signal phiG1 becomes VG by the operation of a vertical scanning circuit 22, a picture element group to which a vertical selecting line 104-1 is selected, and signals of picture elements 21-11, 21-12...21-1n are outputted successively from an output terminal when horizontal selecting switches 23-1, 23-2... are turned on successively by signals phiH1, phiH2,... outputted from a horizontal scanning circuit 24. This picture element group is reset when the signal phiG1 becomes a high-level VR. Next, when a signal phiG2 becomes VG, a picture element group connected to a vertical selecting line 104-2 is selected, and signals of picture elements 21-21, 21-22...21-2n are read out successively by horizontal scanning signals phiH1, phiH2..., and they are reset. Hereafter, signals of individual picture elements are successively read out similarly to obtain one-field components of video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a solid-state imaging device using a buried channel MO8FET as a readout transistor of a photodetecting element.

[Prior art]

In conventional MOS type or COD type solid-state imaging devices,
Most of them use a photodiode as a photodetection element (however, in COD, a depleted MOS capacitor may be used), and the PN of the photodiode
Photocharges, such as electrons, generated in the depletion region of the junction are accumulated in the N diffusion layer, and signal readout is performed by charging when the photodiode potential, which has dropped due to electron injection, is restored to the original video voltage in MO8 type solid-state imaging devices. In a COD solid-state imaging device, the photocharge itself accumulated in the photodiode is transferred to the gate t of a source follower type MOSFET, which is an output terminal, and is read as a change in the gate potential.

However, in any case, while obtaining the maximum number of potential changes of the photodiode, during reading, the signal charge is transferred to the signal readout section, which has a much larger capacity than the photodiode, for detection. Furthermore, in proportion to the ratio of the photodiode capacitance to the signal readout section capacitance, the signal can only be read out as a small output voltage change of one order of magnitude or less than the initial photodiode potential change. Furthermore, when solid-state imaging devices are made to be more densely packed, the photodiode area becomes smaller, and the signal output voltage becomes extremely small in proportion to the area reduction ratio.

〔the purpose〕

The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional solid-state imaging device, and the present invention does not transfer the photocharges accumulated in the photodiode to the signal readout section at the time of readout, but instead retains the photocharges within each pixel cell. It is an object of the present invention to provide a solid-state imaging device that can read out signals up to 100 nm and obtain a signal output voltage with little loss.

〔overview〕

The present invention is a buried channel MO8FET for optical signal readout.
A unit pixel cell is constituted by a photodetecting photodiode connected between the gate and source of the MO8FET, and a capacitor formed on the gate of the MO8FET,
By arranging a large number of unit pixel cells in a matrix,
The capacitors of each pixel cell group arranged in the Y direction are commonly connected to each vertical selection line, and the MO of each pixel cell group arranged in the Y direction is
The drains of the SFETs are commonly connected to each horizontal selection line, and the change in potential of the photodiode due to optical input is read out as it is and given as a change in the gate potential of the MOSFET.By applying a readout signal to the MO8FET via a capacitor, the photo A read signal current based on a change in the potential of the diode and a read signal voltage is sequentially extracted from each unit pixel cell to obtain a video signal.

〔Example〕

An embodiment of the present invention will be described below. The prisoners in Figure 1 are
FIG. 1 ( ] 3) is a sectional view taken along the person-A' line, and FIG. 1 (q is B - It is a cross-sectional view taken along the line B', and () in FIG. 1 is its equivalent circuit. Each pixel in this example is configured as follows. That is, an N-type buried diffusion layer 2 is formed on a P-type substrate 1, and an N-type buried diffusion layer 3.3' that becomes the source and drain of the readout buried channel MO8FETIOI is formed in the diffusion layer 2.
A MO8FETIOI silicon Φ gate 4 is formed on the buried diffusion layer 2 between the diffusion layers 3 and 3' with a gate insulating film 5 interposed therebetween. Note that both the N diffusion layer 3.3' and the silicon gate 4 are formed by a self-alignment method. 6 is an insulating film, and 7 is a contact portion of the drain diffusion layer 3', to which a metal wiring layer 9 is connected. Note that this wiring layer 9 is connected to a horizontal selection line 105. The source diffusion layer 3 is connected to the metal film 10 through the contact portion 8,
The metal film 10 is configured as a light shielding film and is connected to earth.

11 is a shallow P diffusion layer formed in the N type buried diffusion layer 2;
A photodiode 102 is configured by a P+N junction with. This bi-diffusion layer 11 and the MO8FET 1 for reading
The gate 4 of No. 01 is connected at the contact portion 12 via a polysilicon electrode 4' which is an extension of the gate electrode. A polysilicon electrode 13 is formed on the P diffusion layer 11 via the gate insulating film 5, thereby forming a capacitor 103 between this electrode 13 and the gate 4 of the read MOFET.

Further, this polysilicon electrode 13 is arranged horizontally and constitutes a vertical selection line 104.

In FIG. 2, an imaging device is constructed by arranging the unit pixels shown in FIGS. 4 to 4 in a matrix. a scanning circuit 22 for vertical selection lines with respect to the pixel matrix 21;
A horizontal scanning circuit 24 is arranged to scan the horizontal selection line via a horizontal selection switch 23 consisting of a MOSFET and a MOSFET.
It is connected to a video power supply Vv via an ET (or load resistor) 5.

) in FIG. 2 is an example of a signal waveform for operating the solid-state imaging device. Signal φv1 applied to the vertical selection line,
φV2, . Blanking period tllT before moving to horizontal scanning.

is set to be the value of VR. Signals φold, φ[2, ·
. . . is a signal for selecting the horizontal selection line, and a low level is set to a voltage value that turns off the horizontal selection FET, and a high level is set to a voltage value that turns it on. Note that ■out is an example of the output voltage waveform obtained from the output terminal.

The operating principle of this embodiment will be explained based on the circuit configuration for the unit pixel shown in Fig. 3 (At). Fig. 3 (T3) is for explaining the operation of the unit pixel shown in Fig. 3 (A). 2 is an operation waveform diagram of. In the third doujin, the parts with the same reference numerals as those in FIG. 1 n1 and FIG. 2 It is.

The potential Vp of the gate point of the read MO8FET 101, that is, the point A in FIG. (see B)), a positive voltage of aVR is applied. Here, α is α-CG/ (Oc
+Op), and aVR means the pulse amplitude voltage that is effectively applied to point A out of the pulse amplitude voltages of φV.

By the way, when a voltage applied to point A is applied, since the photodiode 102 is connected to point A in the forward direction, A
At first, the potential at the point is about the forward voltage (commonly known as VBE) of a diode, and the potential gradually decreases until it reaches a slight positive voltage VA at time t2. At time t2, when φV becomes a low level, the potential Vp at point A decreases by aVR that is proportional to the amount of decrease VR.

Therefore, the potential at point A at this time t2 is VA -a
VR, and the photodiode 102 is reverse biased. The potential Vp at point A then increases due to the photocharge accumulated in the photodiode, and at the vertical selection time t3, the potential Vp at the photodiode 102 increases during the intervening time Ti.
Due to the photocharge Qp(Ti) accumulated in , △v
The potential increases by p(Ti)=Qp(Ti)/(Oc+Op). At time t3, when the pulse amplitude voltage ■G is applied to the vertical selection line again, the potential at point A further increases by αVc, and Vp = VA - α (VR - Vc) 10△
vp(Ti) and naru.

Threshold voltage of embedded channel MO8T'ETIOI (horizontal selection switch 23 is turned on,
The drain voltage (: Vv
) is applied, the threshold voltage) is VA-α
(VR-Vc), the time T
MO8F for the first time when there is accumulation of photocharge during i.
ETIOI can be turned on, and the drain current when turned on corresponds to the increase in gate potential during time Ti. Therefore, after this time t3, when the horizontal selection switch 23 is turned on by φH,
The above drain current flows, and this current causes the load MO8]
A voltage drop occurs between the 'i' ET25 and can be taken out as an output signal voltage Vo corresponding to the direction of light incidence at the output terminal.As shown in Figure 3 (A), the video power supply Vv and the readout MO8FET1 .O], the horizontal selection switch 23 and the load MO8FET 25 are connected, but due to the operating characteristics of the depression type load MO8FET, the output voltage Vout
E T 101 The voltage can be approximately proportional to the change in the gate potential. In FIG. 3 (I3), time t
When the signal φG becomes VR again at step 4, the potential at point A becomes VA, and the accumulated charge Qp(Ti) up to that point is cleared. At time t5, when the signal φG becomes low level, A
The potential at the point is reset to VP-VA-aVR again,
Charge accumulation for the next field begins.

Next, the operation of the solid-state imaging device shown in FIG. 2(A) will be explained based on the above operating principle. When the signal φG1 reaches VG due to the operation of the vertical scanning circuit 22, the vertical selection line 10
The pixel group tangential to 4-1 is selected, and the signals φold, φH2, . . . are output from each horizontal scanning circuit.
Accordingly, the horizontal selection switches 23-1, 23-2, . . .
. . . turn on sequentially, pixels 21-41 .
2]-12,...2l-1n signals are output from the output terminal.

Subsequently, this pixel group is reset when the signal φGl becomes high level VR. Next, when the signal φG2 becomes VG, the pixel group connected to the vertical selection line 104-2 is selected, and the horizontal scanning signals φold, φH2, . . .
・Yoshi, pixel 21-21.21-22,...
...2l-2n signals are sequentially read out and then reset. Thereafter, the signals of each pixel are sequentially read out in the same manner, and a video signal of one field is obtained.

Next, the buried channel MO8FE used in the present invention
Add an explanation about 'TI'. FIG. 4(A) is a cross-sectional view thereof, and FIG. 4(]3) is a potential diagram along line A-A,'. An N-type buried diffusion layer 2 is formed on a P-type substrate 1''2 to a depth of 1 to 3 μm, and an N-type buried diffusion layer 3.3' that becomes a source and a drain is formed in the diffusion layer 2.
Further, a gate electrode 4 is attached to the surface of the buried diffusion layer 2 between the N diffusion layers 3 and 3' via a gate insulating film 5 to form a MOSFET.
Form ET. Potential of substrate 1 VSUI! , and the source 3 are grounded, and the drain 3' is connected to the voltage shown in Figure 4 (I3
), if a voltage higher than the maximum potential value φM is applied,
As shown in the potential in (a) of Figure 4 (I3),
The channel portion is completely depleted, allowing electrons, which are majority carriers, to flow. Drain voltage φ
When M or less or OV, the potential becomes as shown in (b), and electron conduction becomes impossible. When the gate voltage is made negative, a state can be created in which the channel portion is depleted and no drain current flows, as shown in potential (C), under the application of a small drain voltage. The gate voltage at this time is the buried channel MO8
This is the threshold voltage of the FET. The features of this buried channel MO8FET are that it uses majority carriers, and since the channel is formed in the bulk rather than near the surface, carrier mobility is high, and the current density is higher than that of the surface channel MO8FET. You can get the following.

Therefore, by using a MOSFET with such a configuration as a read transistor, a high output signal voltage can be obtained.

〔effect〕

The present invention provides a unit pixel of a solid-state imaging device that includes a buried channel MO8FET for optical signal readout, a photodetection photodiode connected between the gate and source of the FET, and the M8FET for optical detection.
Since it is configured by combining a capacitor formed on the gate of an O8FET, it is possible to read out a signal while the photocharge generated by the photodetection photodiode is accumulated in the readout MO8FET. By using the change in the potential of the photodiode as the change in the gate potential of the MO8FET for reading, it is possible to obtain an output signal voltage with less loss.

It's a good idea to use a buried channel MO as a readout transistor.
Since 8FETs are used, a large output current can be extracted and a high output signal voltage can be obtained.

[Brief explanation of the drawing]

FIG. 1(A) is a plan view of a unit pixel portion of an embodiment of the solid-state imaging device of the present invention; , Figure 1 (to) is
The equivalent circuit, FIG. 2(A), is an overall circuit configuration diagram of an embodiment of the solid-state imaging device of the present invention, and FIG. 2(I3) is a circuit diagram for the operation of the device shown in FIG. 2(A). Signal waveform diagram, Figure 3 (
A) is a circuit diagram to explain the operating principle of the device shown in FIG. 2 (5), FIG. 3 (I3) is a waveform diagram to explain the operation of the circuit, and FIG. ), but) are a cross-sectional view of the buried channel MOS Ti"ET and a potential diagram along the line A-A'. In the figure, ■ is the substrate, 2 is the buried diffusion layer, and 3.3' is the source and drain. 4 is a gate, 5 is an insulating film,
11 is a diffusion layer for a photodiode, 101 is a buried channel MO8FET for signal readout, 102 is a photodiode for photodetection, 103 is a capacitor, 104 is a vertical selection line, 105 is a horizontal selection line, 22 is a vertical scanning circuit, 23 is a Horizontal selection switch, 24 horizontal scanning circuit, 25 M for load
Indicates O8F'ET. Patent applicant Olympus Optical Industry Co., Ltd. 1)-1)-
19 t U 〉

Claims (1)

[Claims] Embedded channel MO8FET for optical signal readout and the MO
A unit pixel is formed by a photodetecting photodiode connected between the gate and source of the 8FE'r and a capacitor formed on the gate of the MO8FET.
', 4?7T: ;'','', the capacitors of each pixel cell group arranged in the X direction are commonly connected to each vertical selection line, and the MO8I of each pixel cell group arranged in the Y direction is
! 1. A solid-state imaging device characterized in that the drain of the T is commonly connected to each horizontal selection line, and the signal current corresponding to the optical input of each unit pixel cell is sequentially read out using an XY addressing method.