JPS6256719B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to color television receivers, and more particularly to improvements in color decoding circuits.

Conventionally, this type of circuit separates and extracts a luminance signal and a color subcarrier signal from a television video signal, and detects an I signal and a Q signal from the separated and extracted color subcarrier signal via a phase detection circuit. The I signal and Q signal obtained by this are configured by a means for obtaining image signals corresponding to the three primary colors of light using a video matrix circuit, etc., and the disadvantage is that the circuit is complicated and the adjustment is also complicated. be.

SUMMARY OF THE INVENTION An object of the present invention is to provide a color television receiver that eliminates the above-mentioned drawbacks and digitizes the color decoding circuit to simplify the circuit configuration and facilitate adjustment.

The receiver of the present invention includes a burst signal detection circuit that detects a burst signal from a television video signal, and a receiver that is synchronized with the burst signal detected by the burst signal detection circuit and at least three of the burst signals.
a clock signal generation circuit that generates a clock signal with twice the frequency; and a clock signal counter that counts the clock signal with one cycle of the burst signal as one period and outputs it as a plurality of parallel digital signals of a predetermined number of bits. a video signal digital conversion circuit that receives a clock signal generated by the clock signal generation circuit and uses it as a sampling clock signal to convert the television video signal into a digital signal of a plurality of parallel bits having a predetermined number of bits; a read-only memory circuit configured to receive a parallel digital signal output from the clock signal counting circuit and a parallel digital signal output from the video signal digital conversion circuit and output a plurality of groups of prespecified parallel digital signals of multiple bits; , an analog conversion circuit that converts the multiple-bit parallel digital signals of multiple prespecified groups output from the read-only memory circuit into analog signals for each group, and outputs the analog signals;
It is configured to include a low-pass filter circuit that receives a plurality of groups of analog signals output from the analog conversion circuit, filters them with a low-pass filter having a predetermined low cut-off frequency, and outputs the filtered signals.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment of the present invention shown in FIG. 12,
13 and a color cathode ray tube circuit 100.

A television video signal (hereinafter simply referred to as a video signal) 1001 input to an input terminal 1000 is input to a burst signal detection circuit 1 and a video signal digital conversion circuit 4.

The burst signal detection circuit 1 generates a burst signal from the input video signal 1000 and sends it to the clock signal generation circuit 2 via the output line 101.

The clock signal generation circuit 2 generates a digital clock signal in synchronization with the input burst signal and has a frequency four times that of the burst signal, and sends this to the output line 2.
01 to the clock signal counting circuit 3 and video signal digital conversion circuit 4.

When the clock signal counting circuit 3 receives the input digital clock signal, it counts one cycle of the burst signal as one counting period, and measures the corresponding digital clock signal from 0 to 3. In the example, this is sent as a 2-bit parallel digital signal to the three ROMs 51, 52, 5 of the ROM circuit 5 via the output line 301.
Send to 3. As is well known, a burst signal is a subcarrier that is added approximately 10 Hz after a horizontal synchronizing signal included in a normal video signal, and therefore, one counting period of the clock signal counting circuit 3 corresponds to one period of the subcarrier signal. becomes.

On the other hand, the video signal digital conversion circuit 4 receives a digital clock signal received via the output line 201, which, as is clear from the above, has a frequency equal to four times the frequency of the subcarrier signal. This is digitized as a sampling clock pulse by an A/D converter containing the video signal 1001, and is sent to three of the ROM circuits 5 via an output line 401 as a prespecified n-bit parallel digital signal.
A 2-bit parallel digital signal received from the clock signal counting circuit 3 and an n-bit parallel digital signal received from the video signal digital conversion circuit 4 are input to the ROMs 51, 52, and 53, respectively.

In this embodiment, the ROM circuit 5 includes three ROMs 5.
1, 52, and 53, each ROM contains data for color television image configuration written in accordance with prespecified conditions, and includes a clock signal counting circuit 3 and a video signal digital conversion circuit 4. By receiving the above-mentioned two parallel digital signals inputted from the address terminal of the read-only memory and reading them under the control of the built-in program, multiple parallel bit numbers of multiple groups of signals, in this case three signals, are generated. These are output as ROM circuit outputs, and these are sent to the three D/A converters and D/A converters 61 and 6 of the analog conversion circuit 6 via output lines 511, 512, and 513, respectively.
Send on 2,63.

The parallel digital signals from the clock signal counting circuit 3 and the parallel digital signals from the video signal digital conversion circuit 4 input to the three ROMs 51, 52, and 53 of the ROM circuit 5 are each input to the three ROMs 51, 52, and 53 of the ROM circuit 5, respectively.
The data pre-stored in the ROM is addressed, and the parallel digital signal output from the video signal digital conversion circuit corresponds to the above-mentioned I signal and Q signal, and the phase is changed according to the method of specifying the subcarrier in advance. The parallel digital signal output from the clock signal counting circuit 3 is a burst signal, that is, a standard necessary for synchronously detecting the two color signal components mentioned above on the receiving side. It is a subcarrier wave that is transmitted after the horizontal synchronization signal, and is usually added about 10 cycles after the horizontal synchronization signal.By inputting these two parallel digital signals, the ROM circuit 5
The data is read out while faithfully holding the phase information of the subcarrier and by setting the readout timing.

In this embodiment, ROM51, 52, 53
The three parallel bit signals read from the ROM 51 correspond to red, blue, and green, which are the three primary colors of light, and the ROM 51 corresponds to red, the ROM 52 corresponds to blue, and the ROM 53 corresponds to green. Data is written in each memory in advance, and these data are read out in correspondence with the two input parallel bit symbols and sent to the analog conversion circuit 6 as m-bit digital electric signals.

The analog conversion circuit 6 has output lines 511 and 52.
The digital signals corresponding to the three elements of red, blue, and green input through the D/A converter 6
1, 62, 63 into an analog signal,
These are output lines 611, 621, 6 respectively.
31 to the low-pass filter circuit 7.

The low-pass filter circuit 7 includes three low-pass filters LPF.
(LowPass Filter) 71, 72, and 73, each of which sets a pre-specified low cutoff frequency that removes conversion noise and other unnecessary components in the analog conversion circuit 6.These LPFs remove unnecessary components. The output of each removed is red,
Output lines 7 respectively serve as a red video signal, a blue video signal, and a green video signal corresponding to the three primary colors of blue and green light.
Video amplification circuit 1 via 11,721,731
1, 12, and 13, and is amplified to a predetermined level.
The signal is sent to the color cathode ray tube circuit 100 via signals 101, 1201, and 1301, and an image is displayed in accordance with the video signal 1001.

The present invention relates to a color television receiver.
A digital video signal obtained by converting an input video signal into a digital quantity using a sampling signal that is three times or more as large as the subcarrier signal, and a multi-bit digital signal obtained by counting the sampling signal with one cycle of the subcarrier signal as one period. A plurality of image configuration data each having pre-specified content stored therein.
Input to ROM, read these data and write to ROM.
The signals are output as multiple parallel bit signals of multiple groups obtained in accordance with the number of bits and the contents of the data to be read.
The decoding circuit of a color television receiver is digitized by obtaining a plurality of image constituent signals corresponding to the data content written in the receiver and displaying them on a color cathode ray tube to display a desired image. , its basic features lie in its simplification and ease of adjustment, and various modifications of the embodiment shown in FIG. 1 are conceivable.

For example, in the embodiment of FIG. 1, the output lines 611, 621, 631 of the analog conversion circuit 6
The signals output from the ROM circuit 5 are assumed to correspond to the three primary colors of light, red, blue, and green, respectively, but these are not necessarily limited to the three primary colors of light, and other hues can also be output from the ROM circuit 5. It is clear that this can be easily implemented by changing the data content.

Further, in this embodiment, the plurality of parallel bit signals of the plurality of groups are arranged in three groups, but this does not necessarily have to be limited to three groups, and for example, a four-group arrangement including similar processing for luminance signals, etc. It is clear that it is also possible to easily implement the following.

Furthermore, it is clear that the ROM circuit 5, analog conversion circuit 6, and low-pass filter circuit 7 can be easily combined into an integrated configuration, and all of the above defeats the purpose of the present invention. Both can be easily implemented without any hassle.

As explained above, according to the present invention, in a color television receiver, by providing means for digitizing the color decoding circuit, the adjustment of the color decoding circuit can be made extremely easy and the circuit can be made simple. This has the effect of realizing a color television receiver whose circuit configuration can be greatly simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Burst signal detection circuit, 2... Clock signal generation circuit, 3... Clock signal counting circuit, 4... Video signal digital conversion circuit, 5... ROM circuit, 6... Analog conversion circuit, 7... Low-pass filter circuit, 11. 1
2, 13...Video amplification circuit, 100...Color cathode ray tube circuit.

Claims (1)

[Claims] 1. A burst signal detection circuit that detects a burst signal from a television video signal, and a clock signal generation circuit that generates a clock signal that is synchronized with the burst signal detected by the burst signal detection circuit and has a frequency at least three times that of the burst signal. a clock signal counting circuit that counts the clock signal with one cycle of the burst signal as one period and outputs it as a digital signal of a plurality of parallel bits of a predetermined number of bits; and a clock signal generated by the clock signal generation circuit. a video signal digital conversion circuit that receives a signal and converts the television video signal into a digital signal of a plurality of parallel bits having a predetermined number of bits as a sampling clock signal; and a parallel digital signal outputted from the clock signal counting circuit. a read-only memory circuit configured to receive the parallel digital signal output from the video signal digital conversion circuit and output a plurality of groups of pre-specified multi-bit parallel digital signals; An analog conversion circuit that converts multiple groups of parallel digital signals of multiple bits into analog signals for each group and outputs them, and a low cutoff frequency that receives the multiple groups of analog signals output from the analog conversion circuit and specifies each of them in advance. 1. A television receiver comprising: a low-pass filter circuit that performs color decoding of the television video signal;