KR950007303B1 - Image signal recording & reproducing system - Google Patents

Abstract

The video signal is digitized by one A/D converter for the digitized video signal to be recorded or reproduced by frame units according to a horizontal and a vertical synchronous signal. The circuit includes a decoder(17) for decoding color video signal and for dividing and for filtering a luminance signal and color difference signals (B-Y, R-Y), an encoder(19) for digitizing output signal of the decoder(17), a memory control circuit(21) for generating read/write control signal according to address and field control signal generated by an address signal generator(15), and a decoder(25) for converting video data read from the video memory to analog signal and for demultiflecsing the luminance signal and the color difference signal transmitted from a first frequency divider(13).

Description

Video signal recorder

1 is a circuit diagram of a video signal recording and reproducing apparatus according to the present invention.

2 is a detailed view of the multiplexer shown in FIG.

3 is an output waveform diagram of the first divider shown in FIG.

4 is a configuration diagram of the first data controller shown in FIG.

5 is a configuration diagram of an address carried on an address bus of the memory control circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

11: synchronous separation circuit 13: first divider

15: address generator 17: decoder

19: encoder 21: memory control circuit

23: image memory 25: decoder

27: encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal recording and reproducing apparatus of an image processing system, and more particularly, to converting a video signal into a digital signal using an analog / digital converter and generating an address as a horizontal and vertical synchronization signal of the video signal. The present invention relates to an apparatus for recording and reproducing video signals in units of frames.

A general image processing circuit, for example, an image processing circuit such as a multifunctional VTR, an optical videoconferencing apparatus, a video telephone, etc., has a device for digitally processing a frame-by-frame image to record and reproduce in a memory area. The image processing circuit as described above has a donation of storing a still image of a video signal in a frame unit or a video unit in a continuous unit and reproducing it if necessary. As described above, the above functions can be used for special display such as still image display in video telephone, digital slow motion, still image playback, 4x speed in VTR case, and picture in picture. It is also used to implement the function.

A conventional circuit for performing the above function decodes an image signal into a luminance signal (Y) and a color difference signal (RY) (BY), and uses the three ADCs (Aanalog to Digital Converter) to decode the luminance signal. Digitizing the (Y) and the chrominance signal (RY) (BY), respectively, required a lot of ADCs, and because of this, the peripheral circuit was very complicated, which caused a problem of cost increase due to the increase of components.

Accordingly, an object of the present invention is to provide a video recording and reproducing apparatus which decodes a color video signal and digitizes it into one ACD, generates an address as a horizontal and vertical synchronization signal of the video signal, and records and reproduces the digitized image data in an image memory. In providing.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to an embodiment of the present invention, in which a synchronous separation circuit 11 for outputting a horizontal synchronous signal HSYNC and a vertical synchronous signal VSYNC by synchronously separating an input video signal and a horizontal synchronous signal HSYNC described above. A first divider 13 for dividing (trinally counting) to output a multiplexing control signal, and counting and feeding the horizontal synchronizing HSYNC and vertical synchronizing VSYNC output from the synchronous separation circuit 11 The address generator 15 generating the control signal, the column address and the row address, and the input color image signal are decoded and separated into the luminance signal Y and the color difference signal BY. A decoder 17 for outputting, an encoder 19 for selectively digitizing the output of the decoder 17 under the control of the first divider 13, and converting the output into a predetermined bit of digital data; and the address generator Address and feed control signal output from (15) A memory control circuit 21 which inputs and generates an address and lead / write control signal in response to an input of a recording or playback key, and stores data output from the encoder 19 under control of the memory control circuit 21. And a decoder 25 for converting the output of the image memory 23 into output data of a predetermined bit, converting it into an analog signal, and demultiplexing the output of the first divider 13. And an encoder 27 for encoding the luminance signal Y outputted from the decoder 25 and the color difference signal BY (RY) and outputting them as a composite video signal.

In the above configuration, the address generator 15 includes a horizontal synchronous counter 52, a binary counter 56, and a vertical synchronous counter 58. The decoder 17 is composed of a chroma decoder 29 and a low pass filter (hereinafter referred to as LPF) 31 for low-pass filtering an input signal having a predetermined filtering frequency band. The encoder 19 is composed of a multiplexer (hereinafter referred to as MUX) 33, an ADC 35, and a first data controller 39. The decoder 25 is composed of a second data controller 41, a DAC 45, and a demultiplexer 47. The encoder 27 is composed of an LPF 49 and a chroma encoder 51 having a predetermined filtering frequency.

FIG. 2 is a detailed configuration diagram of the MUX 33 in the encoder 19 shown in FIG. 1, in which the luminance signal Y and the color difference signal (input) are input in response to the control signals A, B and C. MUX 33a for selecting and outputting RY (BY) and a buffer 33b for buffering the output of the MUX 33a to the ADC 35.

3 is an operation waveform diagram of the first divider 13 shown in FIG. 1 and an output waveform diagram of the MUX 33A shown in FIG.

4 is a detailed configuration diagram of the first data controller 39 shown in FIG. 1, which includes a clock generator 39a for generating a clock by input of a predetermined signal and 6 bits output from the ADC 35. FIG. A first shift register 39b for shifting data by the clock of the clock generator 39a, and a second shift register 39c for shifting the output of the first shift register 39b and outputting the data in parallel data. .

5 is an address carried on the address bus of the memory control circuit 21. As shown in FIG.

Hereinafter, an operation of an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

When a color image signal is input to the terminal 9, the chroma decoder 29 decodes the image signal into luminance Y and color difference signal BY (RY), and outputs each of the predetermined signals. The branches are filtered by the LPF 31 and input to the MUX 33. At this time, the sync separating circuit 11 separates the horizontal sync VSYNC and the vertical sync VSYNC from the color image signal inputted to the terminal 9 and outputs them. The first divider 13 connected to the synchronous separation circuit 11 counts the horizontal synchronization HSYNC in a ternary manner, so that the same clock as shown in FIG. A multiplexing control signal is generated and provided as a selection signal (A) (B) (C) of the MUX 33.

In addition, the horizontal synchronization counter 52 in the address generator 15 is started by the separated horizontal synchronization (HSVNC) to count 455 signals oscillated in the crystal 54 to provide the memory control circuit 21, The vertical synchronizing counter 58 is started by the vertical synchronizing signal VSYNC to count the horizontal synchronizing signal HSYNC 263 and provides it to the memory control circuit 21. At this time, the 455-digit counting output of the horizontal synchronous counter 52 is provided as an open dress, which will be described later, and the 263-digit counting output of the vertical synchronous counter 58 is provided as a row address. In addition, the binary counter 56 outputs a control signal for dividing the field by counting the vertical synchronization signal VSYNC in binary.

On the other hand, the MUX 33, which receives the same clock as the third diagrams A, B, and C from the first divider 13, receives the luminance signal Y and the color difference signal BY. ) Will be output multiplexed. That is, when the outputs A, B, and C of the first divider 13 become “high-low-low” as shown in FIG. 3, the MUX 33 outputs the luminance signal Y, and “low”. If it is -high-low ", the color difference signal BY is output, and if it is" low-low-high ", the color difference signal RY is selected and output to the ADC 35. At this time, the ADC 35 samples the output of the MUX 35 at the frequency due to the oscillation of the crystal 37 and converts the output into 6-bit digital, so that the data output from the ADC 35 is shown in FIG. It becomes like (D).

The digital conversion data output from the ADC 35 as shown in FIG. 3D is input to the first shift register 39b of the first data controller 39 configured as shown in FIG. The first shift register 39b shifts data inputted in parallel by a clock generated by the clock generator 39a into serial data and inputs the data to the second shift register 39c. At this time, the clock generator 39a generates six clocks for each input of the third clock (A) output from the first divider 13 and provides them to the first shift register 39b. Therefore, when the MUX 33 selects and outputs both the luminance signal Y and the color difference signal B-Y (R-Y), the first shift register 39b shifts 18 bits. Therefore, the second shift register 39c outputs 18-bit parallel data to the image memory 23 by shifting the output of the first shift register 39b to parallel data.

When a key signal, for example, a storage key signal for storing image data, is input to the terminal 30 while operating as described above, the memory control circuit 21 responds to the input of the stored signal. An address counted and output from the counter 52 and the vertical synchronization counter 58 is inputted and output to the address bus ABUS, and the data control signal IHL is transmitted to the data control terminal DCE every one horizontal synchronization period 1H. Output The write control signal (terminal of the R / W is " low ") and the chip enable signal (-CSD-terminal are " low ") are supplied to the image memory 23. At this time, the address loaded on the address bus (ABUS) is a total of 19 bits as shown in Fig. 5A, A0-A9 is an open dress, and the 455-degree counting output of the above-described horizontal sync counter 52 and A10-A18 is vertical sync. The row address is used as the 263-degree counting data of the counter 58. A19 is the output of the binary counter 56, which is the first field when it is "0" and the second field when it is "1".

Therefore, the memory controller 21 outputs an address signal by the counting output of the horizontal sync counter 52 and the vertical sync counter 58 and the output of the binary counter 56. Therefore, when the data control signal IHL is output from the memory control circuit 21 to the second shift register 39c of the first data controller 39 every 1H period, the output of the second shift register 39c is The address output from the memory control circuit 21 is stored in the address of the designated image memory 23.

That is, when the color image signal is input to the terminal 9, it is digitized with 18 bits of data as described above. When the storage key signal is input to the terminal 30 in such a state, the memory controller 21 “lows” the terminal of the data control signal IHL and the write control signal R / -W--. Outputs a signal of?) To the first data controller 39 and the image memory 23, respectively. At this time, the first data controller 39 outputs the digitally converted data to the image memory 23 in response to an input of the data controller IHL, so that the image memory 23 outputs the input data to a memory controller ( 21 is stored in the area of the address output from 21).

The reading of the data recorded in the image memory 23 by the above operation is started by inputting a reproduction key signal for reproduction to the terminal 30. When the user inputs a reproduction key signal for reading data recorded in the image memory 23, the memory control circuit 21 responds to the input of the reproduction key signal and the address output from the address generator 15 as described above. Is supplied to the image memory 23, and at the same time, the read control signal (terminal of R / -W- is " high ") is outputted, and the data control signal IHL is input to the second data controller 41. At this time, the image memory 23 accesses the image data stored in the corresponding address by inputting the read control signal and the address and outputs the image data to the second data controller 41.

The second data controller 41 is operated inversely to the aforementioned first data controller 39 by the input of the data control signal IHL. That is, the second data controller 41 shifts and outputs 18 bits of data output from the image memory 23 three times by six bits within a 1H period. The output of the second data controller 41 is converted into an analog signal by the DAC 43 for converting 6-bit data into an analog signal and input to the DEMUX 47.

The DEMUX 47 operates in contrast to the above-described MUX 33, and the output of the first divider 13 is "low-low-low" as shown in FIG. 3 (A) (B) (C). When the output is in the state, the luminance signal (Y) is selected and output. When the output is in the state of "low-high-low", the color difference signal (BY) is selected and output. When the output is in the state of "low-low-high", The color difference signal RY is selected and output. The configuration of the DMUX 47 as described above is to demultiplex the signal input to one input terminal to three output terminals, as opposed to the second diagram, so that an analog demultiplexer produced universally can be used. The output of the DEMUX 47 is filtered and output from each filtering area of the LPF 49, which is input to the chroma encoder 51 and output as an analog composite video signal.

As described above, the present invention digitizes a luminance signal and a chrominance signal of a video signal as a single ADC using multiplexing, opens it using horizontal synchronization and vertical synchronization, and provides a dress and a row drag to record / reproduce in a predetermined control. There is an advantage that the required screen can be played back at high speed at any time.

Claims (3)

A video signal recording and reproducing apparatus, comprising: a synchronous separation circuit (11) for outputting a horizontal synchronous signal (HSYNC) and a vertical synchronous signal (VSYNC) by synchronously separating input analog color video signals from the synchronous separation (11); The first divider 13 generating the multiplexing control signal by dividing the output horizontal synchronization HSYNC, and counting the horizontal synchronization HSYNC and the horizontal synchronization VSYNC separately outputted from the synchronization separation circuit 11, A decoder for decoding the control signal, the address generator 15 for generating the open and hang addresses, and the color image signal of the analog signal, separating the luminance (Y) and the chrominance signal (BY) (RY) into low-pass filtering outputs. (17), an encoder (19) for selectively digitizing the output of the decoder (17) in response to an input of the multiplexing control signal output from the first divider (13) to output digitally changed image data; uh A memory control circuit 21 for inputting an address and a feed control signal output from the response generator 15 and generating an address, a read / write control signal, and a data control signal according to the input of the write key control signal and the reproduction key control signal; ) And an image memory 23 for storing image data output from the divider 19 in accordance with an address output from the memory control circuit 21 and a read / write control signal, or for accessing and outputting stored image data. And converts the image data output from the image memory 23 into an analog signal, and decodes it into a luminance signal and a color difference signal BY (BY) by a multiplexing control signal output from the first divider 13. A decoder 25 for multiplexing and outputting, an encoder for encoding the luminance signal Y and the color difference signal BY (RY) output from the decoder 25 and outputting them as analog color image signals. An image signal recording and reproducing apparatus, characterized by comprising a coder (27). 2. The address generator (15) according to claim 1, wherein the address generator (15) is configured to generate a horizontal synchronization counter (52) for generating an open dress by counting the horizontally synchronized signal (HSYNC) and the vertically synchronized signal (VSYNC). Video signal recording and reproducing, characterized in that it comprises a binary counter 56 for generating a feed control signal by dividing by two and a counter 58 for generating a row address by counting the vertically synchronized vertical synchronization signal VSYCNC. Device. The multiplexer according to claim 1, wherein the encoder (19) multiplexes the separated luminance signal (Y) and color difference signal (RY) (BY) in response to a multiplexing control signal output from the first divider (13). (33), an ADC (35) for converting the multiplexed analog signals to digital image data, and a digital image data output from the ADC (35) by shifting predetermined bit data into parallel data; A video signal recording and reproducing apparatus, characterized in that it is constituted by the first data control (39) outputted to (23).

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