GB2226733A - Digital recording of colour television signals - Google Patents
Digital recording of colour television signals Download PDFInfo
- Publication number
- GB2226733A GB2226733A GB8919337A GB8919337A GB2226733A GB 2226733 A GB2226733 A GB 2226733A GB 8919337 A GB8919337 A GB 8919337A GB 8919337 A GB8919337 A GB 8919337A GB 2226733 A GB2226733 A GB 2226733A
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- United Kingdom
- Prior art keywords
- signals
- signal
- converter
- video
- luminance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
- H04N9/82—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback the individual colour picture signal components being recorded simultaneously only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/87—Regeneration of colour television signals
- H04N9/877—Regeneration of colour television signals by assembling picture element blocks in an intermediate memory
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Color Television Systems (AREA)
- Processing Of Color Television Signals (AREA)
- Television Signal Processing For Recording (AREA)
Abstract
A video signal IN is separated and filtered at 10 into luminance and two color difference components. Sync signals HS & VS from separater 30 are fed to logic 40, 50 for addressing a digital memory 70 and to a three phase clock 25 whereby a multiplexer 20A passes the signal components in time division multiplex to an A/D converter 20B. A shift register system 20C converts each set of three serial words relating to a single pixel into a parallel output (i.e. a single digital word) for storage in memory 70. A complementary arrangement 80, 90 is provided for reproduction under the control of a read/write input 60. Arrangement 20 permits the use of a single A/D converter for all the signal components. <IMAGE>
Description
VIDEO SIGNAL RECORDING AND REPRODUCING DEVICE
Field of the invention
The present invention relates to a video signal recording and reproducing device for use in a video processing system, and particularly to a video signal recording and reproducing device in which luminance signal and two color difference (chrominance) signals contained in composite video signals are converted into digital signals by means of A/D (analog-to-digital) converter, and then, address signals are generated by means of horizontal and vertical synchronizing signals of the composite video signals, so that it should be possible to record and reproduce the digital signals for respective frame units.
Background of the invention
In the general video processing apparatuses, there have been proposed many kinds of circuits for functions such as stationary image display for video telephones, digital slow motion, still picture reproduction, double speed video reproduction, and PIP (picture in picture) function in VTR.
Most of such circuits are capable of treating digital conversions for the video for the respective frame units in order to carry out recordings and reproductions.
The above mentioned video processing circuits are capable of storing a still picture from among the video signals of frame units or of field units, and capable of reproducing the still picture if need comes up.
In the conventional circuits for carrying out the above mentioned functions, video signals are decoded into luminance signal Y and color difference signals (B-Y) (R-Y), and these decoded luminance signals Y and color difference signals (B-Y) (R-Y) are digitized by means of an analog-todigital converter ADC, with the result that numerously large number of ADC came to be required, and that the number of the devices within the blocks of the circuits is accordingly increased, thereby increasing the manufacturing cost and the defective product rate.
Then modified circuits have appeared such as a circuit for carrying out samplings after converting the color signals of composite video signals to low frequency signals; a circuit capable of obtaining a good quality image even in the case where the broadcast color signals have weak amplitudes; and a circuit capable of receiving signals to the proper address of the field memory even without using a buffer memory and a control circuit.
An invention basically providing a video processing device through the separation the video signals, and through the related decoding and encoding is disclosed in U.S.
Patent No. 4,652,938 which is issued to Murakami et al.
In the above U.S. Patent color signals are converted to low frequency signals, and then, the converted signals are fed into an ADC, so that a low cost converter ADC could be used, and that the cost for the total system could be saved.
However, in U.S. Patent No. 4,652,938, the incoming composite video signals are separated into luminance signal and color difference signals by means of a luminance signal/ color difference signal separator and the luminance signals are sent to a first ADC, while the color difference signals are first converted into low frequency signals by means of a low frequency converter, and then, are sent to a second ADC.
The signals from the first and the second ADC are transmitted through a transmission line. The transmitted signals are sent to a first and a second digital-to- analog converters (DAC) so that the signals should be converted to analog signals again. Then these converted analog color difference signals pass through a modulator to be combined with the luminance signals at a mixer.
In spite of the above described arrangement, when decodings and encodings are carried out, as many ADC/DAC as the number of the different signals are needed, with the result that the cost of the whole system becomes rather expensive.
SummarY of the invention
Therefore, it is the object of the present invention to provide a video recording and reproducing device which is capable of digitalising the separated luminance signal and the color difference signals of composite video signals by means of a single analog to digital converter, capable of storing these signals in accordance with the address designated by the vertical and horizontal synchronizing signals of the composite video signals, and capable of reading out the stored signals to reproduce them.
In achieving the above object, the device of the present invention comprises:
a Y/C separating means for separating the luminance signal and the two color difference signals from the inputted composite video signals;
an A/D converter means for converting to digital signals the analog signals obtained from the Y/C separating means;
a frequency dividing means for being enabled in accordance with horizontal synchronizing signals when digitalising the respective analog signals obtained from the
A/D converter means and for dividing a predetermined oscillating frequency to generate different control signals for the A/D converter means;
a synchronization signal separating means for separating out horizontal and vertical synchronizing signals from the inputted composite video signals;;
an address signal generating means for outputting field designating signals and signal for row and column addresses of the memory based upon the horizontal and vertical synchronizing signals obtained from the synchronization signal separating means;
a memory control means for outputting control signals for the data outputting of the A/D converter means and the data inputting of a D/A converter means (to be described later) and a read/write control signal for a video memory means after receipt of the write or read instruction signals inputted through a data input means and after receipt of the field control signals and address signals outputted from the address signal generating means;
a D/A converter means for converting the digital signals from the video memory means into analog signals; and
a Y/C mixing means for mixing the luminance signals and the color difference signals which are converted into analog signals by means of the D/A converter means.
Brief descriDtion of the drawings
The above object and other advantages of the present invention will become more apparent by describing the preferred embodiment of the present invention in more detail with reference to the attached drawings in which;
Figure 1 schematically illustrates the video signal recording and reproducing device according to the present invention;
Figure 2 illustrates the connections of a multiplexer 20A installed in the video signal recording and reproducing device of Figure 1;
Figure 3 illustrates the wave patterns of the output signals of a frequency dividing means 25 and the output data of and A/D converter 20B installed in the video signal recording and reproducing device of figure 1;
Figure 4 is a detailed circuital illustration of a first data controller 20C provided in the video signal recording and reproducing device of figure 1; and
Figure 5 shows the construction of the address signal transmitted via an address bus AB between a memory control means 50 and a video memory means 70.
DescriDtion of the preferred embodiment
Referring to Figure 1, the video signal recording and reproducing device according to the present invention comprises the following components.
First, a Y/C separating means 10 consists of a decoder ICA used for separating luminance signals Y and the two color difference signals B-Y, R-Y from the composite video signals supplied to an input terminal IN, and a low pass filter 10B for filtering the luminance signals Y and the two color difference signals B-Y,R-Y with different cut-off frequencies (1.3 E , 0.2 S , 0.2Mi ).An A/D converter means 20 consists of a multiplexer 20A for carrying out multiplexings for the signals outputted from the Y/C separating means 10; an A/D converter 20B for converting the multiplexed analog signals to digital signals; and a first data controller 20C for shifting the digital signals corresponding to the luminance and the two color difference signals outputted sequentially from the A/D converter 20B, and for outputting them in parallel simultaneously.
An address signal generating means 40 consists of a first counter 40A for being initiated by horizontal synchronizing signals HS outputted from a synchronization signal separating means 30, and for counting an output signal of a crystal oxcillator CX2 during a predetermined period of time (for example, modulo-455 counti ng time) to generate a column address signal for the video memory means; a second counter 40B for counting in binary scale vertical synchronizing signals VS, and for supplying signals for designating the fields to a memory control means 50 (to be described later); and a third counter 40C for being initiated by the vertical synchronizing signals VS, and for counting the horizontal synchronizing signals HS during a predetermined period of time (for example, modulo-263 counting time) to generate a row address signal for the video memory means.
A memory control means 50 outputs signals for controlling the data outputting of the A/D converter means 20 and the data inputting of the D/A converter means 80 after receipt of the address signal and the field designating signals outputted from the address signal generating means 40 and after receipt of the read/ write instruction signals outputted from a data input means 60; and also outputs reading/writing control signals for a video memory means 70.
A D/A converter means 80 consists of a second data controller 80A for separating the luminance and two color difference signals of the video memory means 70 based on a reverse process of that of a first data controller 20C in accordance with the control signals IHL outputted from the memory control means 50; a D/A converter 80B for converting the digital signals of the second data controller 80A to analog signals; and a demultiplexer 80C for carrying out demultiplexings in accordance with the output signals of the frequency dividing means 25, for the analog signals corresponding to the converted luminance and two color difference signals.
A Y/C mixing means 90 mixes the outputted luminance and two color difference signals of'the demultiplexer 80C based on a reverse process of that of the Y/C separating means 10, and consists of a low pass filter 90A and an encoder 90B.
Figure 2 is a detailed illustration of the circuit of the multiplexer 20A of Figure 1. This multiplexer 20A is enabled by the three clock signals as shown by A,B and C in
Figure 3, which are outputted from the frequency dividing means 25, and consists of a buffer BU and analog switches
SW1 -SW3 which select the separated luminance signals Y and the separated two color difference signals B-Y,R-Y in response to three clock signals A,B and C.
The frequency dividing means 25 consists of three sections, which are adapted to generate the clocks A, B and
C respectively by dividing the frequency of the prescribed clock signal from a clock generator(not shown).Three clocks
A,B and C have the same frequency, but out of phase not to be crossed each other within the single period of the horizontal synchronizing signal.
Figure 4 is a detailed circuital illustration of the first data controller 20C. The first data controller 20C consists of a clock generator 0KG for generating shifting clock signals in the number of N in accordance with the respective output signals A,B and C of the frequency dividing means 25; a first shift register SR1 for sequentially shifting the respective N-bit luminance and
by two color difference signals incoming in turns response to the shifting clock of the clock generator 0KG to output serial data; and a second shift register SR2 for receiving 3N serial output data of the first shift register SR1 and for supplying 3N-bit data in parallel to the video memory means 70 in accordance with the output signals IHL from a data control terminal DEC of the memory control means 50 when the data corresponding to the write instruction signals are inputted via the data input means 60. That is, the second data controller 80A of Figure 1 operates in a manner opposite to that of the first data controller 20C.
Figure 5 shows the address data transmitted via an address bus AB which is disposed between the memory control means 50 and the video memory means 70.
Now an overall description will made as to the operation of the video signal recording and reproducing device constituted as above.
If composite video signals are inputted into the input terminal IN of the video signal recording and reproducing device shown in Figure 1, the luminance signals Y and the color difference signals B-Y,R-Y are separated from the composite video signals by the decoder 10A of the Y/C separating means 10. These separated signals are respectively filtered by a low pass filter 10B having filtering bands prearranged, and then, are supplied to the multiplexer 20A of the A/D converter means 20.
After receipt of the composite video signals, the synchronization signal separating means 30 separates out the horizontal synchronizing signals HS and the vertical synchronizing signals VS, and supplies them to the first, second and third counters 40A,40B,40C of the address signal generating means 40. That is, the horizontal synchronizing signals HS are supplied to the first and third counter 40A,40C, while the vertical synchronizing signals VS are supplied to the second and third counters 40B,40C.
If the horizontal synchronizing signals HS outputted from the synchronization signal separating means 30 are supplied to the frequency dividing means 25, then a prescribed clock is subjected to frequency divisions in the frequency dividing means 25 to obtain the clocks A,B,C of
Figure 3 out of phase each other within a single period of the horizontal synchronizing signals, and then, the resultant clocks A,B,C are supplied to the selector terminals a,b,c of the multiplexer 20A of Figure 2.
Therefore, the data outputted through the buffer BU after being multiplexed by the multiplexer 20A will have relationships as shown in Table 1 below.
Table 1
a b c Output
1 0 0 Luminance signal Y
0 1 0 Color difference signs B-Y
0 0 1 Color difference signal R-Y
In the above table, a, b and c represent the selector terminals of the multiplexer 20A.
The luminance signals Y and the two color difference signals B-Y,R-Y outputted after being multiplexed by the multiplexer 20A within a single period of the horizontal synchronizing signals as shown in Table 1 will be supplied to the A/D converter 208.
The signals supplied to the A/D converter 20B will be subjected to a sampling in accordance with the oscillating frequency of a crystal oscillator CX1, and will be converted into digital signals as shown by the wave pattern D of
Figure 3 so as for them to be supplied to the first data controller 20C. That is, the A/D converter 20B converts the luminance signal Y to N-bit data in the interval T1 of a single period of the horizontal synchronizing signals, and converts the two color difference signals B-Y,R-Y to N-bit synchronization signal separating means 30 separates out the horizontal synchronizing signals HS and the vertical synchronizing signals VS, and supplies them to the first, second and third counters 40A,40B,40C of the address signal generating means 40.That is, the horizontal synchronizing signals HS are supplied to the first and third counter 40A,40C, while the vertical synchronizing signals VS are supplied to the second and third counters 40B,40C.
If the horizontal synchronizing signals HS outputted from the synchronization signal separating means 30 are supplied to the frequency dividing means 25, then a prescribed clock is subjected to frequency divisions in the frequency dividing means 25 to obtain the clocks A,B,C of
Figure 3 out of phase each other within a single period of the horizontal synchronizing signals, and then, the resultant clocks A,B,C are supplied to the selector terminals a,b,c of the multiplexer 20A of Figure 2.
Therefore, the data outputted through the buffer BU after being multiplexed by the multiplexer 20A will have relationships as shown in Table 1 below.
Table 1
a b c Output
1 0 0 Luminance signal Y
0 1 0 Color difference signal B-Y
0 0 1 Color difference signal R-Y
In the above table, a, b and c represent the selector terminals of the multiplexer 20A.
The luminance signals Y and the two color difference signals B-Y,R-Y outputted after being multiplexed by the multiplexer 20A within a single period of the horizontal synchronizing signals as shown in Table 1 will be supplied to the A/D converter 20B.
The signals supplied to the A/D converter 208 will be subjected to a sampling in accordance with the oscillating frequency of a crystal oscillator CX1, and will be converted into digital signals as shown by the wave pattern D of
Figure 3 so as for them to be supplied to the first data controller 20C. That is, the A/D converter 20B converts the luminance signal Y to N-bit data in the interval T1 of a single period of the horizontal synchronizing signals, and converts the two color difference signals B-Y,R-Y to N-bit data respectively in the intervals T2,T3 of a single period of the horizontal synchronising signals as shown in Figure 3, and these converted signals are supplied to the first data controller 20C.
Meanwhile, the first counter 40A of the address signal generating means 40 will start a counting operation in accordance with inputting of the horizontal synchronizing signals HS, that is, the first counter 40A will count the signals generated by a crystal oscillator CX2 in a modulo455, and will supply the counted result to an input port P1 of the memory control means 50.
The second counter 40B will count the vertical synchronizing signals VS in a modulo-2, and then, will supply field- designating signals to an input port P2 of the memory control means 50. The third counter 40C will start a counting operation in accordance with inputting of the vertical synchronizing signals VS, and will count the horizontal synchronizing signals HS in a modulo-263 to supply the counted result to an input port P3 of the memory control means 50.
The count output from the first counter 40A will be served as for the column address of the video memory means 70, while the count output from the third counter 40C as for the row address of the video memory means 70.
Now, the data outputted in-the form of the wave pattern
D of Figure 3 from the A/D converter 208 will be inputted into the first shift register SRl of the first data controller 20C, and the data will be shifted into serial data in synchronization with the shifting clocks generated by the clock generator CKG, the serial data being stored in the second shift register SR2. Each time when a clock pulse in the form of the wave pattern A,B,C of Figure 3, from the frequency dividing means 25 is applied to the shifting clock generator CGK, the clock generator 0KG will generate shifting clocks in the number of N(6) to be supplied them to the first shift register SR1.
Therefore, when the multiplexer 20A has multiplexed the luminance signal Y and the two color difference signals B-Y,R-Y, the second shift register SR2 will store 3N!18)-bit data outputted from the first shift register SR1.
Under the above-described condition, if write instruction signals is inputted through the data input means 60, the memory control means 50 will output the address signals to the address bus AB based upon the result of the countings by the first and third counters 40A,40C, while the memory control means 50 also will output data control signals IHL through the data control terminal DEC at each period 1H of the horizontal synchronizing signals.
The address signal transmitted via the address bus AB consists of 19 bits in total as shown in Figure 5, of them,
A0-A8 constitute column address signals which are the modulo-455 count output of the first counter 40A, and A9
A17 which are the modulo-263 scale count data of the third counter 40C constitute row address signals, while A18 is an output of the second counter 408, which is characterized in that, if it is at a low state, it indicates the first field, and if it is at a high state, it indicates the second field.
Accordingly, the address signal outputted from the memory control means 50 are decided by the outputs of the first, second and third counters 40A-40C. The data control signal IHL is outputted from the data control output terminal DEC of the memory control means 50 in each period 1H of the horizontal synchronizing signals, and the signal
IHL is supplied to the second shift register SR2 of the first data controller 200.
if the data control signal IHL is supplied in the manner described above, 3N-bit data are outputted in parallel from the second shift register SR2, and are stored to the memory region of the video memory means 70 at the address givin by the address signal generating means 4G, this state being referred to the write mode of the video memory means 70.
As described above, if write instruction signals is inputted through the data input means 60 in order to store the luminance signal Y and the two color difference signals B-Y,R-Y belonging to a single period of the horizontal synchronizing signals into the video memory means 70, then a read/write terminal R/W of the memory control means 50 will output a low signal, so that the video memory means 70 should be set to a write mode.
Therefore, when a write instruction signal is inputted through the data input means 60 as described above, the luminance signal and the two color difference signals of the composite video signals inputted through the input terminal
IN and belonging to a single period of the horizontal synchronizing signals are digitalized and stored in the video memory means 70.
After storing of the data into the video memory means 70 in the manner described above, if a read instruction signal is inputted through the data input means 60 in order to reproduce the stored data, then the memory control means 50 supplies to the video memory means 70 an address signal as shown in Figure 5 in accordance with the output of the address signal generating means 40, and the memory control means 50 also supplies a high signal to the read/write terminal R/W of the video memory means 70.
Accordingly, a 3N-bit video data will be outputted from the video memory means 70, and more specifically, the 3N-bit data will be outputted after being shifted thrice by N bits at a time within a single period 1H of the horizontal synchronizing signals by the second data controller 80A which is operated in a manner reverse to that of the first data controller 20C.
The data outputted by the second data controller 80A are converted to analog signals by the D/A converter 80B, and then are supplied to the demultiplexer 80C.
The demultiplexer 80C which receives the analog signals of 3N bits demultiplexes to output the luminance signal Y and the two color difference signals B-Y,R-Y in a separate form in accordance with the signals A,B,C of Figure 3, which are outputted from the frequency dividing means 25.
The output of the demultiplexer 80C is filtered by the low pass filter 90A having different filtering bands, and then, is outputted through an output terminal OUT in the form of composite video signals in which the luminance signal Y and the two color difference signals B-Y,R-Y are mixed together by the encoder 90B.
As described above, the device of the present invention is capable of storing the incoming composite video signals in the form of a still picture based on the user's intention, and is capable of reading out the stored video, in such a manner that the stored video could be reproduced in a high speed whenever the user wants them.
Claims (9)
- CLAIMS:A video signal recording and reproducing device comprising: a Y/C separating means for separating luminance signal and the two color difference signals from the composite video signals inputted into the input terminal of the system; an A/D converter means for converting the respective analog signals obtained from said Y/C separating means to digital signals; a frequency dividing means for dividing a predetermined oscillating frequency to generate different control signals for said A/D converter means after being enabled by horizontal synchronizing signals which are separated out from the composite video signals when the respective analog signals obtained from said A/D converter means are digitalized; a synchronization signal separating means for separating horizontal and vertical synchronizing signals from the inputted composite video signals;; an address signal generating means for outputting the field designating signals and signal corresponding to the row and column address of a video memory means based upon horizontal and vertical synchronizing signals obtained from said synchronization signal separating means; a memory control means for outputting control signals for the data outputting of said A/D converter means and the data inputting of a D/A converter means and a read/write control signal for a video memory means receipt of write and read instruction signals inputted through a data input means, and after receipt of an address signal and a field control signal outputted from said address signal generating means; a D/A converter means for converting the digital signals read out from the video memory means to analog signals; and a Y/C mixing means for mixing the luminance signals and the color difference signals which have been converted to analog signals by said D/A converter means.
- 2. The video signal recording and reproducing device as claimed in claim 1, wherein said Y/C separating means consists of a decoder for separating the luminance signal Y and the two color difference signals B-Y,R-y from the composite video signals supplied to the input terminal of the system; and a low pass filter for filtering the separated luminance signal Y and the separated color difference signals B-Y,R-Y.
- 3. The video signal recording and reproducing device as claimed in claim 2, wherein said A/D converter means consists of a multiplexer for carrying out multiplexings for the output signals from said Y/C separating means; an A/D converter for converting the multiplexed analog signals to digital signals; and a first data controller for shifting the digital signals corresponding to the luminance and color difference signals outputted sequentially from said A/D converter, and for outputting them in parallel simultaneously.
- 4. The video signal recording and reproducing device as claimed in any one of claims 1 to 3, wherein said address signal generating means consists of a first counter for counting the output clocks of a crystal oscillator during a predetermined period of time to generate a column address signal for the video memory means, after said first counter 40A being initiated by the horizontal synchronizing signals HS outputted by said synchronization signal separating means; a second counter for counting in a binary scale the vertical synchronizing signals VS, and for supplying field disignating signals to the memory control means;and a third counter for counting the horizontal synchronizing signals HS during a predetermined period of time to generate a row address signal for the video memory means, after said third counter being initiated by the vertical synchronizing signals VS.
- 5. The video signal recording and reproducing device as claimed in claim 1, wherein said D./A converter means consists of a second data controller for separating the 3N-bit combination data of the luminance and color difference signals outputted from the video memory means, said separation being made by the amounts of N bits; a D/A converter for converting to analog signals the digital signals outputted from said second data controller 80A; and a demultiplexer for demultiplexing the analog signals corresponding to the luminance and color difference signals outputted from said D/A converter, in accordance with the signals of said frequency dividing means.
- 6. The video signal recording and reproducing device as claimed in claim 3, wherein said multiplexer consists of three switches for selecting the separated luminance and color difference signals Y, B-Y,R-Y in response to three different clock signals outputted by said frequency dividing means; and a buffer for buffering the signals selected by said switches.
- 7. The video signal recording and reproducing device as claimed in claim 3, wherein said first data controller consists of a clock generator for generating shifting clock signals in the number of N in accordance with the frequency-divided output signal of said frequency dividing means; a first shift register for sequentially shifting the respective N-bit luminance and color difference signals in response to the shifting clocks of said clock generator to output serial data; and a second shift register for receiving 3N serial output data of said first shift register, and for supplying 3N-bit data in parallel to the video memory means in accordance with the signals outputted through a data control terminal DEC of said memory control means when a write instruction signal is inputted through the data input means.
- 8. A video signal recording and reproducing device comprising means for separating analog luminance and colour difference signals out of an incoming composite video signal, means for multiplexing said luminance and colour difference signals, means for digitising the multiplexed analog signal from the multiplexing means, means for storing the digitised signal constituting a representation of a still picture, and means for reconstituting a video signal from the stored digitised signal.
- 9. A video signal recording and reproducing device substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880018131A KR950007303B1 (en) | 1988-12-31 | 1988-12-31 | Image signal recording & reproducing system |
Publications (2)
Publication Number | Publication Date |
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GB8919337D0 GB8919337D0 (en) | 1989-10-11 |
GB2226733A true GB2226733A (en) | 1990-07-04 |
Family
ID=19281132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8919337A Withdrawn GB2226733A (en) | 1988-12-31 | 1989-08-25 | Digital recording of colour television signals |
Country Status (3)
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KR (1) | KR950007303B1 (en) |
DE (1) | DE3928026A1 (en) |
GB (1) | GB2226733A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0474305A2 (en) * | 1990-09-07 | 1992-03-11 | Philips Patentverwaltung GmbH | Device for A/D conversion of color information from two picture signals |
GB2264608A (en) * | 1992-02-28 | 1993-09-01 | Samsung Electronics Co Ltd | Reading and separating colour video data stored in a memory |
WO1994010807A1 (en) * | 1992-11-05 | 1994-05-11 | Ampex Systems Corporation | Method and apparatus for providing noise immunity for an input interface of a digital video recorder |
WO1994010806A1 (en) * | 1992-11-05 | 1994-05-11 | Ampex Corporation | Digital video flywheel circuit phasing method and apparatus |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100781359B1 (en) | 2005-03-23 | 2007-11-30 | 삼성전자주식회사 | Apparatus for generating high voltage by digital control and method thereof |
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GB2103046A (en) * | 1978-03-21 | 1983-02-09 | Vital Ind | Video special effects generator |
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- 1988-12-31 KR KR1019880018131A patent/KR950007303B1/en not_active IP Right Cessation
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1989
- 1989-08-24 DE DE3928026A patent/DE3928026A1/en active Granted
- 1989-08-25 GB GB8919337A patent/GB2226733A/en not_active Withdrawn
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GB2103046A (en) * | 1978-03-21 | 1983-02-09 | Vital Ind | Video special effects generator |
GB2037530A (en) * | 1978-11-30 | 1980-07-09 | Sony Corp | Processing reproduced pal colour television signals |
EP0025364A2 (en) * | 1979-09-11 | 1981-03-18 | Nec Corporation | Digital television video signal storage system |
GB2122047A (en) * | 1982-04-16 | 1984-01-04 | Victor Company Of Japan | Digital video signal recording system and reproducing apparatus |
GB2141894A (en) * | 1983-03-31 | 1985-01-03 | Victor Company Of Japan | Recording system for recording a time-division-multiplexed video signal |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0474305A2 (en) * | 1990-09-07 | 1992-03-11 | Philips Patentverwaltung GmbH | Device for A/D conversion of color information from two picture signals |
EP0474305A3 (en) * | 1990-09-07 | 1993-06-30 | Philips Patentverwaltung Gmbh | Device for a/d conversion of color information from two picture signals |
GB2264608A (en) * | 1992-02-28 | 1993-09-01 | Samsung Electronics Co Ltd | Reading and separating colour video data stored in a memory |
GB2264608B (en) * | 1992-02-28 | 1995-08-30 | Samsung Electronics Co Ltd | Data read device for video memory |
CN1041157C (en) * | 1992-02-28 | 1998-12-09 | 三星电子株式会社 | Data reading unit in indeo memorizer |
WO1994010807A1 (en) * | 1992-11-05 | 1994-05-11 | Ampex Systems Corporation | Method and apparatus for providing noise immunity for an input interface of a digital video recorder |
WO1994010806A1 (en) * | 1992-11-05 | 1994-05-11 | Ampex Corporation | Digital video flywheel circuit phasing method and apparatus |
Also Published As
Publication number | Publication date |
---|---|
KR950007303B1 (en) | 1995-07-07 |
DE3928026A1 (en) | 1990-07-05 |
KR900010741A (en) | 1990-07-09 |
GB8919337D0 (en) | 1989-10-11 |
DE3928026C2 (en) | 1992-02-20 |
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