KR101299420B1 - Nicam processor - Google Patents

Abstract

The NICAM processor 82 includes a first memory 100 that temporarily stores the A-channel and B-channel data of the current frame, wherein the current frame data is stored in the first memory at a first clock rate. The second memory 106, 108 temporarily stores the companded A-channel and B-channel of the previous frame in a format different from the interleaved format according to the NICAM specification request. The interleaving circuit 105 reads the previous frame companded data from the second memory at a second clock rate in a manner that interleaves the previous frame data in the NICAM specification required interleaved format. The bit stream generator 114 generates a first portion of the output bit stream, multiplexes it with the payload portion, and outputs an output bit stream, where the first portion includes frame alignment words, control information, and additional data. The payload portion includes interleaved data of the previous frame. The companding and storing circuit 104 composes the input data of the current frame and stores the companded data in the second memory at a third clock speed in a format different from the NICAM interleaved format. The companding and storing circuits operate for an interval within the current frame after storing in the first memory and reading from the second memory.

NICAM Processor, Interleaving Circuit, Companding and Storage Circuit, First Memory, Frame

Description

NICAMC processor {NICAM PROCESSOR}

TECHNICAL FIELD The present invention relates to stereo audio encoders, and more particularly, to a NICAM processor and a method for implementing NICAM processing.

Near-Instantaneously Companded Audio Multiplex (NICAM) encoding improves sound quality and provides multiple channels of data or digital sound compared to other TV sound systems. It is generally used in countries that use PAL and SECAM television systems for digital multisound transmission. 1 is a schematic block diagram of a prior art composite video and dual channel audio system 10, wherein the dual channel audio system includes an analog filter 12, a dual channel analog-to-digital converter (ADC) 14, and digital sound. NICAM encoder 16, analog QPSK transmitter 18 and RF modulator 20. The analog filter 12 filters the two audio inputs 22 and 24, respectively, and outputs the filtered signal on the outputs 26 and 28. Outputs 26 and 28 of analog filter 12 are input to dual channel ADC 14. ADC 14 receives a first clock at an integer multiple of 34 (CLK1), 32 kHz, and converts signals from ADC inputs 26, 28 into corresponding digital signals on ADC outputs 30, 32, respectively. . As shown, the outputs of the dual ADCs 14 have 14-bit resolution. Digital sound encoder 16 receives a second clock at 38 (CLK2) and processes the signals of encoder inputs 30 and 32 into digitally encoded signals on encoder output 36 in accordance with the NICAM specification. As a result, encoder output 36 is input to analog QPSK transmitter 18. QPSK stands for Quadrature Phase Shift Keying. Analog QPSK transmitter 18 receives a third clock at 42 (CLK3), and QPSK modulates the signal received at input 36 to output 40. Thereafter, the QPSK modulated signal on output 40 is combined with the composite video at signal line 44 by RF modulator 20. The RF modulator then RF modulates the combined QPSK modulated signal and composite video to the RF modulator output 46.

Also, with respect to the system of Figure 1, pre-emphais can be applied with two inputs in either the analog or digital domain. The two input signals are digitized to 14-bit resolution at 32 kHz sample rate (CLK1 or CLK1 integer divide) via the ADC 14. Samples are grouped into 32 14-bit data blocks during A and B channels, such as a 1 ms duration. In the digital sound encoder 16, the samples of each block are companded into 10 bits with the same scaling factor. Then, one bit of parity is added to each 10-bit sample for error detection and scale-factor signaling purposes. Thereafter, the A channel and B channel data are multiplexed, and the bits are interleaved according to the interleaving pattern described in the NICAM specification, forming a frame of 704 bits. Then, an 8-bit frame alignment word, 5-bit control information and 11-bit additional data are added to the beginning of the block of 704 bits to form a frame of 728 bits. Each frame is transmitted continuously every millisecond, for example, on signal line 36. The overall bit rate is 728 bits / second, corresponding to clock 38 (CLK2). The bit stream is then converted into two streams of scrambled (except bits belonging to the frame alignment word) and quadrature data sampled at in-phase 1-bit and 364 kHz (symbol rate), and the QPSK transmitter. 18 is differentially encoded and QPSK modulated using a clock 42 (CLK3) on a 5.85 MHz subcarrier for the TV system (B, G, H, L) or a 6.552 MHz subcarrier for the TV system (I). Thereafter, the QPSK modulated audio signal 40 is combined with the composite video 44 and RF modulated with the RF modulator 20. The RF modulator generates RF signals 46 on the VHF and / or UHF channels.

Conventional implementations of NICAM encoding systems require the need for multiple clocks, and tuning, and in terms of integration into an audio / video chip or single-chip encoder due to the use of non-portable analog blocks when integrated It is not very cost effective. Moreover, conventional implementations of NICAM encoding system implementations are not very cost effective due to memory requirements and the complexity of the bit interleaving process.

With regard to the NICAM algorithm implementation, memory requirements indicate that the companding process and the operation of the changed bits can be performed only when all 32 A-channel and B-channel input samples have been obtained. Thus, the algorithm requires that 32 samples for each channel A and channel B be obtained before performing the NICAM encoding. In addition, a NICAM encoded output stream of 728 bits must be generated continuously without a gap every millisecond. In conventional implementations, extra memory and circuitry are used to meet these needs. In addition, the interleaving process is complex. The interleaving process according to the NICAM specification is based on a (44 X 16) matrix structure in which four condensed words are written in columns at a time and one bit at a time is read in rows. In addition, conventional implementations of scramblers require extra processing hardware. As a result, the digital functions of NICAM encoders, in particular the NICAM algorithm, have been implemented with digital signal processors (DSPs) and field-programmable gate arrays (FPGAs). In addition, pre-emphasis filtering (if not implemented in the analog domain), companding and scale factor encoding are implemented in the DSP, while NICAM bit interleaving, scrambling and differential encoding are performed by the FPGA. These DSP and FPGA chips are expensive even when they are mass produced.

NICAM encoders are generally used in TV stations and typically involve very expensive rack mount units. While less expensive versions exist for different applications, other applications also require a printed circuit board with several separate components. As a result, in terms of cost and complexity, NICAM encoders are mainly used in broadcast equipment and not in equipment for home use.

Accordingly, there is a need for improved methods and apparatuses to overcome the problems of the prior art as discussed above.

The invention is not limited by the accompanying drawings, but is described by way of example, wherein like reference numerals indicate similar elements.

1 is a schematic block diagram of a dual channel audio system having a conventional composite video and a NICAM encoder equipped with an analog RF modulator;

Figure 2 is a diagram of the structure of the components of a 728-bit frame before (I) interleaving and (II) a bit stream of 728-bit frame bits after interleaving;

3 is a schematic block diagram of a dual channel audio system and composite video with a single-chip NICAM encoder implementation in accordance with an embodiment of the present invention;

4 is a schematic block diagram illustrating a detailed NICAM encoder implementation of FIG. 3 in accordance with an embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating the NICAM processor of FIG. 4 in more detail in accordance with an embodiment of the present invention; FIG.

6 is a timing indication diagram of a timing relationship between input samples and bit pairs during a portion of data compression of NICAM encoder implementation processing in accordance with an embodiment of the present invention;

FIG. 7 is a schematic block diagram of parity bits and scrambling blocks encoding with compand, parity operation, scale factors of the NICAM processor of FIG. 4 in more detail in accordance with an embodiment of the present invention; FIG.

8 is a matrix structure of input RAM content, FAW / C / AD partial frame, interleaved complied samples and condensed data RAMs, according to an embodiment of the present invention; And

9 is a schematic block diagram of the bit stream generation block of FIG. 5 in more detail in accordance with an embodiment of the present invention.

Using the same reference numerals in different drawings represents similar or identical items. Those skilled in the art will also recognize that elements of the figures are shown for simplicity and clarity and need not be drawn to scale. For example, the size of some elements in the figures may be exaggerated in conjunction with other elements to facilitate understanding of embodiments of the present invention.

Figure 2 is a diagram of the bit stream of 728-bit frame bits after (I) interleaving, the structure of the components of a 728-bit frame and (II) after interleaving. Referring to FIG. 2 (I), the components of the bit stream 11 before performing the bit interleaving process are: 8-bit frame alignment word (FAW) 13, 5-bit control information 15, 11 -Bit additional material 17, and 64 11-bit A and B processed words, generally indicated by reference numeral 19. In FIG. The 728-bit frame 11 also shows the relationship between bits and word and bit numbering. That is, bit 1 is the first bit of FAW 13 and bit 728 is the last bit of word B32.

In addition, along with the entire frame structure of FIG. 2 (I), an 8-bit FAW 13, 5 control bits 15 and 11 additional data bits 17 are added to the payload 19. FIG. In addition, it forms a frame of 728 bits with the reference number 11. As shown, FAW 13 is 01001110 and the leftmost bit (ie BIT 1) is transmitted first. With regard to the control information 15, the information consists of a frame flag bit C ₀ , three application control bits C ₁ , C ₂ , C ₃ and a designated sound switching flag C ₄ . The frame flag bit C ₀ is set to 1 for 8 consecutive frames and to 0 for the next 9 frames, defining 16 frame sequences. The 16 frame sequence is used to synchronize changes to the type of information carried on the channel. The application control bits are set according to the desired content of the 704-bit sound / data of the payload 19. Regarding the designated sound switching flag C ₄ , if the analog signal does not carry the same program as the digital signal, C ₄ is set to zero, otherwise it is set to one. Since eleven additional data bits 17 are designated for next use (not yet defined), eleven additional data bits can be arbitrarily set to zero.

2 (II) shows how bits 11 of a frame are rearranged at the bit level after the bit interleaving process. In particular, interleaving is applied to the companded fountains of the structure of FIG. 2 (I) to minimize the impact of multiple bit errors. The condensed samples are rearranged according to the (44 X 16) matrix structure described above, as shown by reference numeral 19 in Fig. 2 (II). According to the NICAM specification, a (44 X 16) matrix has four concatenated words written in rows at the same time and one bit read in columns at a time. The 44 bits of each column of the matrix are indicated by reference numeral 21, the 16 bits of each row of the matrix are denoted by reference numeral 21, and the 16 bits of each column of the matrix are denoted by reference numeral (23). Is represented by). The bits of each frame are transmitted in the order shown in Fig. 2 (II). In FIG. 2 (II) (ie after interleaving), bit numbering is numbering as used in FIG. 2 (I) (ie after interleaving). In addition, the bit stream 11 of FIG. 2 (II) is a representative output 36 of the digital sound encoder 16 of FIG. Note that before performing differential encoding according to the NICAM standard, the bits of the bit stream of FIG. 2 (II) need to be grouped in bit pairs (ie, pair bits). In one embodiment, the NICAM processor immediately generates this bit pair.

3 is a schematic block diagram of a composite beading and dual channel audio system 50 having a single-chip NICAM encoder implementation in accordance with one embodiment of the present invention. The composite video and dual channel system 50 includes a first analog filter 52, a NICAM encoder 54, a second analog filter 56 and an analog RF modulator 58. The analog filter 52 filters the two inputs 60, 62, respectively, and outputs the filtered signals on the outputs 64, 66, respectively. Dual inputs may include independent channels (ie, A and B) or a left and right audio channel in a stereo pair. In one embodiment, analog filter 52 includes an analog anti-aliasing filter.

Outputs 64, 66 of analog filter 52 are input to NICAM encoder 54. NICAM encoder 54 receives a single clock at 68 (CLK) and converts the signals on inputs 64 and 66 into corresponding QPSK modulated signals on output 70. In one embodiment, the clock at 68 includes a crystal oscillator. NICAM encoder 54 also provides a clock output on signal line 72 as described below. As shown, the output 70 of the NICAM encoder 54 is input to the second analog filter 56. Filter 56 provides a filtered QPSK modulated signal with a carrier of 6.552 or 5.85 MHz on output signal line 74. In one embodiment, filter 56 includes an analog recovery filter. Thereafter, the filtered QPSK modulated signal on output 74 is combined with composite video on signal line 76 by RF modulator 58. The RF modulator then RF modulates the composite video and the QPSK modulated signal coupled to the RF modulator output 78 as an RF signal (VHF / UHF). RF modulator 58 also receives a clock input on signal line 72.

4 is a schematic block diagram of a detailed implementation of the NICAM encoder of FIG. 3 in accordance with an embodiment of the present invention. The NICAM encoder 54 includes a front end input section 80, a NICAM processor 82 and a front end output section 84. As discussed above, the NICAM encoder 54 includes inputs 64 and 66 and receives a single clock at 68 (CLK). In one embodiment, the clock output on signal line 72 is from a clock input on signal line 68 (CLK) using, for example, a suitable integer separator. NICAM encoder 54 converts the signals on inputs 64 and 66 into corresponding QPSK modulated signals on output 70. In one embodiment, the front end of the NICAM encoder 54 includes a front end input section 80 and a front end output section 84.

In addition to responding to data signals on inputs 64 and 66, in response to clock input 68, front end input section 80 outputs inputs to produce 14-bit data at 32 kHz in accordance with the NICAM specification. Process to (86,88) respectively. Pre-emphasis is performed in the analog domain or front end input section 80. In one embodiment, pre-emphasis filtering may be performed by the NICAM processor 82, even though the mapping of the analog filter into the digital domain is not accurate due to limitations on the sampling frequency.

In one embodiment, the outputs 86, 88 of the front end input section 80 correspond to individual inputs to the NICAM processor 82. In addition to responding to signals on inputs 86, 88, the NICAM processor responds to in-phase (I) and quadrature (Q) in response to a clock strobe 68 and a processor strobe on signal line 94. Single-bit data stream signals are processed into output lines 90 and 92, respectively. In other words, the NICAM processor 82 allows samples generated at 32 kHz by the front end input section 80. The NICAM processor 82 then performs digital companding on inputs 86 and 88, and scrambled, differentially encoded in-phase (I) and quadrature (Q) data sampled at 364 kHz relative to the NICAM specification. On output 90, 92, respectively. In alternative embodiments, I and Q data on signal lines 90 and 92 may also be provided on a single signal line (not shown) at 728 kHz, using suitable circuit implementations.

As detailed herein, various aspects of NICAM processing in accordance with the NICAM specification are known in the art and are only briefly described herein. However, with respect to the NICAM processor 82, the embodiments herein will be fully described below.

Referring again to FIG. 4, the outputs 90, 92 of the NICAM processor 82 correspond to individual inputs to the front end output section 84. A front output section in response to clock input 68 as well as in response to in-phase (I) and quadrature (Q) single-bit data stream signals on outputs 90, 92 (ie, bit pairs). 84 processes the inputs into a corresponding QPSK modulated signal on output 70. The QPSK modulated signal on output 70 includes a signal that meets the NICAM specification. In addition, the front end output section 84 creates a processor strobe on the signal line 94 discussed herein. In one embodiment, the shear input section 80 and the shear output section 84 are assigned by Zoso et al. On April 29, 2005, a co-pending patent specification, assigned to the assignee of the present invention and incorporated herein by reference. Shear input as disclosed in S / N 11 / 117,820, filed with the name of the filed invention "FRONT-END METHOD FOR NICAM ENCODING" and S / N 11 / 118,211, filed with "NICAM ENCODER WITH A FRONT END". And an output section. To simplify the discussion, additional details of the shear input section 80 and the shear output section 84 are not provided herein. In other embodiments, processor strobes on signal line 94 may be provided by any suitable control logic or circuit implementation.

Referring back to the NICAM processor 82, the processor processes 14-bit A and B data (on signal lines 86 and 88, respectively) sampled at 32 kHz provided by input section 80 and conforms to the NICAM specification. Thus generating in-phase and quadrature phase data sampled at 364 kHz (on signal lines 90 and 92). In particular, in accordance with an embodiment of the present invention, the NICAM processor 82 is configured to: acquire data, compute a scale factor, compress 14-bit introduced data to 10-bit resolution, compute parity bits, calculate scale factors and parity bits. Encoding, bit interleaving, generation of 728-bit bit streams, scrambling of all data frames performed in 32 cycles of the system clock, converting bit streams into two streams of 1-bit in-phase and quadrature data, and of differential encoding Perform the join. Processor 82 outputs a pair of bits on output signal lines 90, 92 in response to each generation of strobes on signal line 94 from front output section 84. In one embodiment, strobe 94 is generated at a frequency of about 364 kHz and may be generated by suitable control logic included in front output section 84 or elsewhere. In one embodiment, scrambling of A-channel and B-channel condensed data is performed in all generations of strobe 94.

5 is a schematic block diagram of the NICAM processor 82 of FIG. 4 in more detail in accordance with an embodiment of the present invention. The processor 82 includes: 1) blocks 100 and 102 for data acquisition and computation of scale factor respectively, 2) block 104 for companding, parity bit operations, encoding and scrambling of parity bits with scale factors, 3) block 105 for bit interleaving; And several main blocks including block 114 for bit stream generation.

In particular, 14-bit A-channel and B-channel data (sampled at 32 kHz) on input signal lines 86,88 are combined into 28-bit words and stored in 32 × 28 input RAM 100. The 14-bit A-channel and B-channel data stored in RAM 100 is provided to block 104 via output data bus 122 as discussed herein. In one embodiment, the input RAM data format includes that indicated by reference numeral 252, as shown in FIG. As shown in FIG. 8, the 32-bit size of the RAM data format 252 is indicated by reference number 260, and the 28-bit size is indicated by reference numeral 262. As shown in FIG.

In one embodiment, the NICAM processor 82 may also include a pre-emphasis filter (not shown). That is, A-channel and B-channel data may be filtered by a pre-emphasis filter before being combined into 28-bit words and stored in the input RAM 100. Pre-emphasis filtering can be implemented using any suitable circuit element or implementation that performs pre-emphasis filtering in accordance with the requirements of the NICAM specification.

Referring again to FIG. 5, the NICAM processor 82 also includes a scale factor block 102. Scale factor block 102 receives data on input 120 and provides A-channel and B-channel scale factor outputs R _A , R _B on signal lines 124, 126, respectively. In particular, the calculation of the largest absolute value is performed in scale factor block 102 simultaneously with the acquisition of data samples. That is, at the beginning of the frame, the absolute values of the first A-channel and B-channel data samples are stored in two registers (not shown) in block 102. The magnitude of the second A-channel and B-channel samples is compared to the contents of the register, and if the latter sample is larger, they replace the register contents. The process is repeated for all 32 A-channel and B-channel input samples. When the last A-channel and B-channel input samples are stored in RAM 100, the largest value is available in two registers. Thereafter, scale factor block 102 determines scale factors, for example, by comparing the largest values stored in two registers with multiple thresholds. In one embodiment, the number of thresholds includes seven thresholds, and the A-channel and B-channel scale factors R _A and R _B include three bits in each of the signal lines 124 and 126. .

Block 104 is an A-channel on each of the input data and signal lines 124 and 126 on signal line 122 for companding, parity bit operations and encoding of scale factors and parity bits, as described below with respect to FIG. And B-channel scale factors R _A and R _B. Block 104 provides 22 bits of condensed data on output signal bus 130, in addition to writable signals on WRITE_EN (1) and WRITE_EN (0) lines, indicated by reference numerals 128 and 132, respectively. In other embodiments, the writable signals may be provided by any suitable control logic or circuit implementation. In one embodiment, scrambling is performed at block 104, but scrambling may also be performed outside block 104 (not via block NX 22 ROM 183), which is not related to block 104, or It may be performed at block 114 of FIG. 5 (via MX 2 ROM 183) to be discussed. In one embodiment, scrambling is accomplished with the use of a look-up table, where the scrambling is restarted at the beginning of every frame. Look-up table implementations require conventional hardware, as described in the NICAM specification, because look-up tables require less processing hardware, and look-up table addresses are readily available through, for example, address generator 160. More cost effective than scramblers In other words, address generation for the look-up table can be obtained without the specific requirement of implementing a counter to generate an address. The bit stream generator 114 loads the FAW 13, the control information 15, and the additional data 17 into the bit stream 11 of the A-channel and B-channel data processed as shown in Fig. 2 (II). ) As discussed herein, the NICAM processor 82 operates with limited or minimal amounts of memory to implement the NICAM algorithm in a very efficient manner, making the NICAM processor 82 more suitable for single-chip integration.

In one embodiment, processor 82 includes two 32 X 28 RAM 100 for input data and two 16 X 22 RAMs 106 and 108 within block 105 for condensed data. Block 105 of processor 82 (i) stores the condensed data with modified parity bits in the condensed data RAM 106,108 in a particular order, thereby (ii) two bits (or bits per RAM access). A complex interleaving process is performed by reading from the RAM 106, 108 multiple times using each of the bit extractors 110, 112, extracting the pair). RAM 106 and 108 couple to bit extractors 110 and 112 via 22 bit signal buses 134 and 136, respectively. In addition, the bit stream generator 114 is extracted and compressed on the signal lines 111 and 113 to generate I and Q data on each of the signal lines 90 and 92, as described herein with respect to FIG. Respond to interleaved data bits. In another embodiment, the bit stream generator 114 may be configured to generate a single bit stream from the extracted companded interleaved data bits, wherein the companded interleaved data bits are in the form of a single bit stream. Extracted from memory.

In addition, the address generator 160 of FIG. 5 includes any suitable address generator. In addition, address generator 160 is configured to provide addresses to various components of NICAM processor 82 as appropriate, performing the NICAM encoder embodiments and NICAM encoding method of the present invention.

FIG. 6 illustrates the timing relationship between input samples and bit pairs (also referred to as “twin bits”) in addition to the timing for processing of input memory data to produce companded samples, as shown herein. . In timing indication 140, and with respect to input sample timing, there are 32 samples per frame on each A-channel input and B-channel input. Timing indication 140 includes frames 142 and 144 and additional frames (denoted by "..." denoted by reference numeral 145). Note that one frame is equivalent to 32 input samples at 32 kHz, which is equivalent to 364 bibit output at 364 kHz. The interval 146 represents the interval between the last acquired input sample data of the frame 142 and the first obtained input sample data of the next frame 144. An enlarged view 148 of the spacing 146 of the sample 31 contains about 11.375 pairs of bits. Furthermore, in magnification 148, note that output pair bit 353 is not aligned exactly at the beginning of sample 31. In other words, any given output pair of bits in a frame may be generated at a different timing than the timing of the input sample, ie the output pair of bits may not directly collide with the generation of the input sample. In addition, the interval 150 represents the interval between the last output pair of bits and the first output pair of bits of the next frame 144 during frame 142. An enlarged view 152 of the spacing 150 of the twin bits 363 includes NICAM processing and compressed data RAM 106,108 of input RAM data (ie, sampled A-channel and B-channel input data in RAM 100). A sub-interval 154 is included in which storage in) is achieved. Sub-interval 154 may include any portion or portions of overall interval 150, except for the ends of interval 150. In one embodiment, the top level system clock includes a 24 MHz clock and the interval 150 includes about 65.93 cycles of the 24 MHz clock. In addition, for a 24 MHz clock, the interval 154 will include 32 cycles of a 24 MHz clock, assuming that two channels of data are processed at the same time. This is repeated to the next frame 144 at an interval 156 or the like for the next frames. Interval 156 represents the interval between the last acquired input sample data of frame 144 and the first acquired input sample data (not shown) of the next frame.

While the processor 82 acquires data, it must output a pair of bits continuously, i.e. without a gap, at a rate of 364 kHz. Portions of timing diagram 140, represented by reference numeral 148, indicate the timing of the pair of bits for the last portion of frame 142. In addition, according to an embodiment of the present invention, NICAM processing of the acquired data is performed during the time interval 150. The interval 150 is very important that (i) all input data of the current frame is obtained, and (ii) simultaneously output all condensed data stored in the condensed data memory 106, 108 from the previous frame. This means that the acquired data (ie input A-channel and B-channel data) of the current frame can be processed (according to the NICAM specification) and the result can be stored directly in the companded data memory (RAM 106, 108). Means that. As a result, no additional memory is needed. The processor 82 must also be fast enough to process all input data after the last pair of bits are output from the condensed data memory and before a new input sample is obtained.

In one embodiment, companding of each A-channel and B-channel sample is performed by the circuit implementation shown in FIG. 7, with the computation of parity bits and the encoding of parity bits and scale factors. The format of the companded samples is also shown as indicated by reference numeral 211. In particular, the format 211 includes 22-bits, shown from MSB to LSB, where the modified parity bit P _A (reference 213) is of the companded A data, corresponding to A ₈ -A ₀ . This is followed by a sine bit A ₉ (ref. 215). Subsequent to A ₀ is a modified parity bit (P _B ) (reference 217), which is followed by a sign bit (B ₉ ) (reference 219). Following the sine bit B ₉ is the remainder of the condensed B data corresponding to B ₈ -B ₀ . The modified parity bit P _A represents the MSB, while the B data bit B ₀ represents the LSB of the format 211 of the companded samples. Each sample is read from the input RAM, processed, and written to the condensed data RAMs using a format 211 or other suitable format as shown, in one cycle of the system clock. According to one embodiment of the present invention, 32 cycles of the system clock are taken during the interval 150 at the end of each frame to process the entire input RAM 100. As discussed above, FIG. 6 shows not only the timing relationship between the input samples and the bibit, but also when the input RAM data is processed to produce compressed samples.

In one embodiment, block 104 of Figure 7 includes (i) companding means, (ii) means for performing parity bit operations, (iii) scale factors and parity bit encoding means, and (iv) scrambling means. do. The selection of the desired bits of scale factors R _A , R _B , each scale factor having three bits, is as shown in the NICAM specification. In one embodiment, scale factor bit selection is performed by Modulo-3 counter 180. Alternatively, the scale factor function can be implemented in other ways, for example with a suitable look-up table. In addition, the scale factor bits are EX-ORed with the parity bits as described in the NICAM specification. In one embodiment, the selected bits of scale factors R _A , R _B are EX-OR with parity bits via EX-OR gates at multifunction blocks 168, 178, as discussed further herein.

In one embodiment, block 104 of FIG. 7 includes an A-channel processing portion, generally indicated at 162 and a B-channel processing portion, generally indicated at 172. A-channel processing portion 162 includes right shifter 164, EX-OR tree 166, multifunction block 168, and EX-OR gate block 170, where EX-OR gate block 170 Is shared with the B-channel processing portion 172. From the input RAM 100 on the signal bus 122, fourteen MSBs are routed to the right shifter via the signal bus 190. Right shifter 164 operates in response to fourteen MSBs on signal bus 190 and scale factor R _A on signal line 192 to provide a shifted output on signal bus 194. Four MSBs of the shifted output are discarded on the signal bus 196 and ten LSBs of the shifted output are transmitted on the signal bus 198. Six MSBs of ten LSBs on signal bus 198 are routed to EX-OR tree 166 via signal bus 200. EX-OR tree 166 operates in response to six MSBs on signal bus 200 to provide an output on line 202. That is, EX-OR tree 166 performs an EX-OR of all six inputs and produces a single bit output. The signal on line 202 is input to multifunction block 168. Multifunction block 168 provides a signal on line 202, an output 204 of Modulo 3 counter 180 and a scale factor R _A on signal line 192 to provide an MSB on output signal bus 206. In response to). In other words, the multifunction block 168 is based on the scale factor R _A 192 based on the control signal 204 generated by the Modulo 3 counter 180 in accordance with Equation 1 and Table 1 as discussed herein. ) Bit. In addition, the multifunction block 168 EX-ORs the selected bits of R _A with the output of the EX-OR tree 166, thus modifying the parity bits P _A of the format 211 output on the line 206. ) 213. The MSBs on bus 206 are combined with ten LSBs on bus 198 to generate eleven MSBs of corresponding companded samples on signal bus 208. The eleven MSBs on bus 208 are combined with eleven LSBs (to be discussed) of the corresponding condensed samples on bus 238 to produce 22 bits of condensed samples on signal bus 210 and EX−. Input to OR gate block 170. In one embodiment, EX-OR gate block 170 includes 22 EX-OR gates, each of which performs an EX-OR of bits of signal 210 and corresponding bits of signal 212. Produces a 22-bit output on line 130.

B-channel processing portion 172 includes right shifter 174, EX-OR tree 176, multifunction block 178, and EX-OR gate block 170 shared with A channel processing portion 162. . From the input RAM 100 on the signal bus 122, 14 LSBs are routed to the right shifter via the signal bus 220. Right shifter 174 operates in response to fourteen LSBs on signal bus 220 and scale factor bits R _B on signal bus 222 to provide a shifted output on signal bus 224. Four MSBs of the shifted output are discarded on the signal bus 226 and ten LSBs of the shifted output are delivered to the signal bus 228. Six MSBs of ten LSBs on signal bus 228 are connected to EX-OR tree 176 via signal bus 230. EX-OR tree 176 operates in response to six MSBs on signal bus 230 to provide output on line 232. That is, the EX-OR tree 176 performs all six EX-ORs and produces a single bit output. The signal on line 232 is input to multifunction block 178. Multifunction block 178 provides a signal on line 232, an output 204 of Modulo 3 counter 180 and a scale factor R _B on signal line 222 to provide an MSB on output signal bus 236. In response to). In other words, the multifunction block 178 is based on the scale factor R _B 222 based on the control signal 204 generated by the Modulo 3 counter 180 in accordance with Equation 1 and Table 1, as discussed herein. Select one bit of). Moreover, the multifunction block 178 EX-ORs the selected bits of R _B with the output of the EX-OR tree 176, thus modifying the parity bits P _B of the format 211 output on the line 236. Generate (217). The MSB on bus 236 is combined with ten LSBs on bus 228 to produce eleven LSBs of corresponding companded samples on signal bus 238. The eleven LSBs on bus 238 are combined with eleven MSBs (already discussed) of the corresponding condensed samples on bus 208 to produce 22 bits of condensed samples on signal bus 210. Input to the EX-OR gate block 170. As discussed herein, in one embodiment, EX-OR gate block 170 includes 22 EX-OR gates, with each gate representing a bit of signal 210 and a corresponding bit of signal 212. EX-OR with, produces a 22-bit output on line 130.

It is noted in FIG. 7 that block 104 is illustrated and illustrated as including separate other processing portions 162, 172 that process channel A data and channel B data, respectively. However, in another embodiment, block 104 of FIG. 7 may include a single processing unit 162 or 172 multiplexed between two channels, thus reducing the overall hardware complexity of NICAM processor 82.

In one embodiment, scrambling is provided by scrambler 182 (FIG. 7) in the form of N X 22 ROM, where N is 32 in this example. The scrambler 182 responds to an input RAM address on the address input line 161 to provide a 22 bit scrambling output on the bus 212. The address on address line 161 may be provided by address generator 160 (FIG. 5) as appropriate. EX-OR gate 170 responds to the bits on buses 210 and 212 to provide 22 bits of scrambled and compressed data on output signal bus 130. Signal bus 130 is input to condensed data RAM 106, 108 of FIG. 5, as discussed herein. Block 104 also stores the appropriate write-enabled signals WRITE_EN (1) 128, WRITE_EN (0) 132 (FIGS. 5 and 7), respectively, with the compressed data RAM 1 106 and RAM 0 108. 5 and 8, together with the address provided by the address generator 160 of FIG. 5, for example, of the paired A-channel and B-channel word pairs as shown in FIG. Allow storage

Since only new input samples are obtained, the compressed samples for the current frame are stored in the compressed data RAM, and then all input samples of the current frame are processed after the last pair of bits related to the previous frame are output, so that only one 32 X 28 RAM 100 and two 16 × 22 RAMs 106 and 108 are needed to store the input samples and the compressed samples, respectively. Thus, no extra memory is needed to store the input or processed data.

Also, with respect to FIG. 7, the shifter (at 164 and 174 respectively) is a 14-bit A-channel and a B- (at 162,172 respectively) based on the corresponding scale factors (R _{A at} 192 and R _{B at} 222). Shift channel samples to the right. Shifters 164, 174 may shift input by factors 4, 3, 2, 1 or 0 to the right. For example, if the scale factor is 7, the input is shifted to the right by four bits. Since the signal bits are automatically shifted, this is always the MSB of 10 LSBs (at 198 and 228 respectively). Therefore, four MSBs can be discarded (at 196 and 226 respectively). Each parity bit is computed by EX-ORing six MSBs (at 200 and 230, respectively), and the resulting bits (at 202,232 respectively) are scale factors (R _A and R _B , respectively) according to equation (1). EX-OR with DML scale factor bits. Modified parity bits P'i (at 206 and 236, respectively) are obtained by encoding parity bits Pi with scale factor words R _A and R _B in the following manner:

는 EX-OR 동작을 나타낸다. 페이로드 블록 내에서, 64를 통해서 패리티 비트들(55 내지 64)은 범위 비트를 전달하는데 포함되지 않는다. 수학식1에서, 홀수-번호화된 인덱스들을 갖는 Pi 및 P'i는 채널 A에 관련되는 반면, 짝수-번호화된 인덱스들을 갖는 Pi 및 P'i는 채널 B에 관련된다.Where i is the index of 64 sample structures (indicated by reference number 19 in FIG. 2 (I)), where R _2A , R _1A , R _0A and R _2B , R _1B , R _0B are R _A and R _B, respectively Is a bit of,

Indicates EX-OR operation. Within the payload block, parity bits 55 through 64 through 64 are not included in carrying the range bits. In Equation 1, Pi and P'i with odd-numbered indices are related to channel A, while Pi and P'i with even-numbered indices are related to channel B.

Table 1, derived from Equation 1, links each RAM address with a corresponding scale factor bit. Synchronized with the address count, Modulo-3 counter 180 or a suitable look-up table (LUT) selects the scale factor needed to EX-OR along with the current parity bits for the A- and B-channels. Thereafter, the modified parity bits are inserted before the MSB of the companded data. The two 11-bit data are combined to form a 22-bit word on the output 130 shown in FIG. In this embodiment, scrambling is performed directly on the samples before the interleaving process.

Input RAM address Modulo 3 Scale factor bits Position before interleaving Input RAM content Interleaving
All locations Scale factor bits 0 2 R _2A One A1 B1 2 R _2B One One R _1A 3 A2 B2 4 R _1B 2 0 R _0A 5 A3 B3 6 R _0B 3 2 R _2A 7 A4 B4 8 R _2B 4 One R _1A 9 A5 B5 10 R _1B 5 0 R _0A 11 A6 B6 12 R _0B 6 2 R _2A 13 A7 B7 14 R _2B 7 One R _1A 15 A8 B8 16 R _1B 8 0 R _0A 17 A9 B9 18 R _0B 9 2 R _2A 19 A10 B10 20 R _2B 10 One R _1A 21 A11 B11 22 R _1B 11 0 R _0A 23 A12 B12 24 R _0B 12 2 R _2A 25 A13 B13 26 R _2B 13 One R _1A 27 A14 B14 28 R _1B 14 0 R _0A 29 A15 B15 30 R _0B 15 2 R _2A 31 A16 B16 32 R _2B 16 One R _1A 33 A17 B17 34 R _1B 17 0 R _0A 35 A18 B18 36 R _0B 18 2 R _2A 37 A19 B19 38 R _2B 19 One R _1A 39 A20 B20 40 R _1B 20 0 R _0A 41 A21 B21 42 R _0B 21 2 R _2A 43 A22 B22 44 R _2B 22 One R _1A 45 A23 B23 46 R _1B 23 0 R _0A 47 A24 B24 48 R _0B 24 2 R _2A 49 A25 B25 50 R _2B 25 One R _1A 51 A26 B26 52 R _1B 26 0 R _0A 53 A27 B27 54 R _0B

In one embodiment, N is selected to be 32 (FIG. 7), and the pseudo-random sequence generator or scrambler stores the stored 1-bit pre-computed pseudo-random numbers in such a way that it is output at the correct time with respect to the condensed data before interleaving. It includes a 32 X 22 look-up table (ROM 182). Although the repetition period of the pseudo-random sequence is 511, 22 X 32 = 704 values are stored to simplify the design. In this way, 1-bit pre-computed pseudo-random numbers can be EX-ORed (with the EX-OR gate 170) with the 22 bit complied samples generated by the processor 82. In one embodiment, it is determined that only data to be companded needs to be scrambled as a result of the implementation of several predetermined conditions. Predetermined conditions include the following:

1) The FAW does not need to be scrambled per the requirements of the NICAM specification;

2) By definition in the NICAM specification, 5-bit control information is output during the beginning portion of a pseudo-random sequence containing only zeros; And

3) The value of the eleven additional data bits can be set to an absolute value (i.e., 0), so as to prescramble the additional data bits first.

In another embodiment, 704 pseudo-random numbers are stored in an MX 2 look-up table, such as ROM 138 (M is 352), and scrambling is performed in bit stream generator 114 (FIG. 5 and FIG. 9).

Figure 8 shows an example of memory mapping 250 for acquisition and companding according to one embodiment of the present invention. Block 252 shows memory mapping for acquisition of A-channel and B-channel. Thirty-two samples of each row of the matrix are indicated by reference numeral 260 and 28 bits of each column of the matrix are denoted by reference numeral 262. 32 14-bit A-channel and B-channel data are stored as generated by the input section of FIG. Block 254 represents a 24-bit frame alignment word (FAW), control information (C) and additional data (AD) from the LSB to the MSB. Block 256 originates from FIG. 2 (II), which corresponds to what is defined in the NICAM specification to describe the bit interleaving process. Block 256 shows the matrix structure used to perform bit interleaving using data words instead of bits. The 44 bits (or four condensed words) of each column of the matrix 256 are indicated by reference 264, and the 16 bits of each column of the matrix are indicated by reference 266. The first and second columns of the matrix are indicated by reference numbers 268 and 270, respectively. The last row of matrix 256 is indicated by reference numeral 272. In particular, block 256 is shown in FIG. 8 as including a 44 X 16 matrix structure written in columns (four condensed words at a time) and read in columns (one bit at a time). In the past, the cost of this structure of block 256 was not very efficient because it would require either (i) specific RAM that could be written in rows and read in columns or (ii) FPGAs. to be. However, the practice of the present invention overcomes these problems in the prior art.

In accordance with one embodiment of the present invention, the bit interleaving process includes a combination of memory mapping (blocks 106 and 108, Figure 8) and bit extraction (blocks 110 and 112, Figure 5). In other words, the NICAM processor 82 performs the bit interleaving process in two steps.

First, the condensed samples are stored in two 16 × 22 RAMs 106,108, which are constructed as shown in FIG. 8 and indicated together by reference numeral 258. FIG. As shown, the 16 bits of each row of RAM 106,108 are indicated by reference numeral 274, and of each column (including A-channel and B-channel condensed samples) of RAM 106,108. Twenty-two bits are indicated by reference numerals 276 and 278, respectively.

Secondly, the RAM locations are read several times, extracting only one bit from RAM 1 106 and one bit from RAM 0 108 in each RAM access. This simplifies the bit interleaving process and allows the generation of paired bits (or bit pairs) directly. In particular, eleven MSBs of RAM 1 and RAM 0 for addresses 0 through 7 correspond to the first column of matrix 256 shown in FIG. 8, and of RAM 1 and RAM 0 for addresses 0 through 7. The eleven LSBs correspond to the second column of the matrix 256. The 11 MSBs and 11 LSBs of RAM 1 and RAM 0 relative to addresses 8 through 15 of RAM 1 and RAM 0 include samples of the third and fourth columns of matrix 256, respectively. In other words, RAM 1 and RAM 0 are each pair of bits (eg, pair bits A1 _j, A3 _j ), pair bits A5 _j , A7 _j ,..., Pair bits A29 _j , A31 _j ; Bit (B1 _j , B3 _j ), pair bits (B5 _j , B7 _j ), ..., pair bits (B29 _j , B31 _j ); pair bits (A2 _j , A4 _j ), pair bits (A6 _j , A8 _j ) , ..., pair bits (A30 _j , A32 _j ); pair bits (B2 _j , B4 _j ), pair bits (B6 _j , B8 _j ), ..., pair bits (B30 _j , B32 _j ), where j is the bit index And their range includes MSB and LSB of 0 to 10).

The address counters of RAM 1 106 and RAM 0 108 are incremented every hour, and processor output strobe 94 is received from front end output section 84. Strobe 94 is generated at approximately symbol speed. The locations are read twenty-two times at addresses 1 through 7 of RAM 1 106 and RAM 0 108. The complete words are read, but only two bits are actually used (ie extracted) every hour. The first time, all LSBs of word A (corresponding to bits 25, 69, 113, 157, ..., 685 of FIG. 2 (II)) are read out, and the second time, all following LSBs of word A Bits (corresponding to bits 70, 114, 158, ..., 686, etc.) are read. After eleven times, all the bits of word A are read. The process is repeated another 11 times to read all the bits of word B. After that, the same process is applied to the addresses 8 to 15. The twin bits extracted from RAM 1 106 and RAM 0 108 are available on the outputs 111 and 113 of the bit extractors 110 and 112 of FIG.

9 is a schematic block diagram of the detailed bit stream generator 114 of FIG. 5 in accordance with an embodiment of the present invention. The bit stream generator 114 is responsible for processing 11-bit additional data combined with 8-bit FAW, 5-bit control information and payload. The resulting output bit stream is the same as the stream shown in FIG. 2 (II), where bits are grouped in bit pairs, odd-numbered bits are MSBs, and even-numbered bits are LSBs. In addition, in one embodiment, the bit stream generator 114 also performs differential encoding to generate in-phase and quadrature data transmitted to the output section 84 of FIG. In another embodiment, the bit stream generator 114 also performs scrambling of interleaved and condensed data bits via the ROM 138 and the EX-OR gates 1110 and 1113, as further discussed herein. .

As shown in FIG. 9, the bit stream generator includes two multiplexers 912 and 914, a preface generator 900 and a differential encoder 916. Prepaid generator 900 outputs one of the FAW, control information and additional data in pairs of bits in response to the appropriate control signals. In particular, in response to the bit pair counter input on signal line 902, a frame counter input on signal line 904, programmable control information input on signal line 906, and pre-pace generator 900 output MSB and LSB outputs. 908, 910 generate FAW, control information, and additional data, grouped into bit pairs on each. In response to the MUX control signal on signal line 917, multiplexer 912 multiplexes one of inputs 111, 908 on MUX output 913, and multiplexer 914 inputs 113, 910 on MUX output 915. Multiplex one of

For bit pairs 0-11, the multiplexer outputs are combined with the outputs of pre-pace generator 900, while for bit pairs 12-363, multiplexer outputs are combined with signals 111,113. In this way, FAW, control information and additional data, generated in bit pairs by the prepaid generator 900, are inserted at the beginning of the output bit stream before the payload. Recall that the payload includes the outputs of the bit extraction blocks 110, 112 of FIG. 5 on the signal lines 111, 113, respectively. In addition, in response to the data on processor strobe 94 and inputs 913, 915, differential encoder 916 generates differentially in-phase and quadrature data encoded on outputs I 90 and Q 92, respectively. . Output I 90 and Q 92 are sent to output section 84 of FIG. 4, where the output bit stream is sampled at 364 kHz. The various control signals (bit pair counter, frame counter, programmable control information, MUX control, and processor strobe) may be suitable circuitry or other means for implementing the signal with respect to NICAM encoder processing in accordance with an embodiment of the present invention. Not shown).

Further, as described above, in another embodiment, the bit stream generator may also include a scrambler in the form of (MX 2) ROM (or look-up table) 138 and EX-OR gates 1110 and 1130. Can be. ROM 138 receives address information through address input 161. The ROM (Look-Up Table) and EX-OR gates, as appropriate, are configured to perform scrambling of the input data of block 114. In particular, the ROM 138 is coupled with the first inputs of the EX-OR gates 1110 and 1130 via the signal lines 1380 and 1381 respectively. Second inputs of the EX-OR gates 1110 and 1130 are coupled to the MSB line 111 and the LSB line 113, respectively. In this embodiment, lines 111 and 113 will not be directly coupled with the first inputs of each of the MUXs 912 and 914. The outputs of the gates 1110 and 1130 are coupled with the first inputs of the MUXs 912 and 914, respectively. Also in this embodiment, the M value is 352.

In another embodiment, the outputs of the bit extraction circuit blocks 110, 112 are combined into a single bit stream, for example, by a serial-to-parallel converter (not shown), or the bits are compressed data RAMs 106,108. Are extracted one at a time. Prepaid data (FAW, control information and additional data) is generated by a modified prepace generator, similar to prepace generator 900 but with a single bit output. Preface data (FAW, control information and additional data) is multiplexed with the output of the parallel-to-serial converter, thus creating the bit stream shown in Fig. 2 (II). In this embodiment, the bit stream sampled at about 728 kHz is transmitted to an output section 84 that is converted into bit pairs by a parallel-to-serial converter (not shown). The bit pairs are then differentially encoded before performing QPSK modulation.

In one embodiment, NICAM processor 82 generates 364 in-phase and 364 quadrature data in every 1 ms frame, provided on signal lines 90 and 92, respectively.

In one embodiment, the system clock frequency is 24 MHz, which is generated directly by the crystal oscillator, and all other clocks are from this system clock 68 with integer separators. Thus, no PLL is needed. The single-chip implementation of the NICAM encoder is shown in FIG. In alternative embodiments, the front sections 80, 84 and the NICAM processor 82 may also be embedded in the audio / video integrated circuit chip.

As discussed, embodiments of the present invention not only require a limited amount of memory and circuit elements, but also provide a very efficient implementation of a NICAM algorithm that reduces the overall cost of system implementation. In addition, embodiments also solve problems in the technology by making it possible to have a VCR, a DVD player, a decoder, set-top boxes and other audio / video applications with NICAM encoders according to the invention. In fact, NICAM encoders related to RF modulators can provide high quality stereo sound and composite video through a single RF connector instead of a 21-pin SCART connector or three audio / video connectors (video, left audio and right audio). Because NICAM encoders can be used in DVD players, stereo VCRs, set-top boxes, game stations and stand-alone units, this simplifies the typical home entertainment wiring architecture and also allows them to connect remotely to a television set. . By using equipment with built-in NICAM encoders according to an embodiment of the present invention, multiple audio / video applications can be connected to the set-top box via possible coaxial and receive stereo audio. In addition, typical home entertainment wiring can be greatly simplified.

Embodiments of the present invention allow encoders to be produced at low cost. Thus, this allows NICAM encoders to be used extensively in consumer electronics applications. In addition, embodiments of the present invention address this issue by incorporating a NICAM processor with a limited number of circuitry and memories that enable the implementation of NICAM encoders that are much more cost effective than those already known.

According to one embodiment, the NICAM processor includes a first memory having inputs for receiving A-channel and B-channel input data and for temporarily storing A-channel and B-channel input data of a current frame. A-channel and B-channel input data of the current frame are stored in the first memory at a first clock rate. The NICAM processor also includes a second memory that temporarily stores the compressed A-channel and B-channel data of the previous frame in a format different from the interleaved format as required by the NICAM specification. The interleaving circuit interleaves the previous frame-compressed A-channel and B-channel data in an interleaved format according to the requirements of the NICAM standard, thereby interleaving the previous frame-compressed A-channel and B-channel data at a second clock rate. 2 Read from memory. The bit stream generator generates an output bit stream. In addition, the output bit stream may comprise either single bits or twin bits, each corresponding to a single bit stream at 728 kHz, or corresponding to a double bit bit stream at 364 kHz.

The bit stream generator comprises: (i) a prepaid generator for generating a first portion of the output bit stream, comprising a frame alignment word (FAW), control information and additional data; and (ii) the payload portion and output bits of the output bit stream. And a multiplexer for multiplexing the first portion of the stream. In addition, when a bit is generated, the bit stream generator also includes a differential encoder that differentially encodes the output bit stream before being output by the bit stream generator. The payload portion is interleaved through the read from the second memory to include interleaved and condensed A-channel and B-channel data of the previous frame. The companding circuit compresses the A-channel and B-channel input data of the current frame, and compresses the compressed A-channel and B-channel input data of the current frame into a second memory in a format different from the interleaved format at the third clock rate. Save it. In one embodiment, the first portion of the output bit stream comprises (a) a frame alignment word (FAW), (b) control information and (c) pairs of additional data, wherein the payload portion of the output bit stream Contains two bits of interleaved and condensed A-channel and B-channel data of the previous frame. In addition, the first clock speed, the second clock speed, and the third clock speed are different from each other. In one embodiment, the companding and storing circuitry operates only during the interval within the current frame after storing in the first memory and reading from the second memory.

In yet another embodiment, the format other than the interleaved format according to the NICAM standard includes a dual word pre-interleaved format. In addition, the dual word of the dual word pre-interleaved format includes 22-bits of the paired A-channel word and the paired B-channel word pair.

In another embodiment, the interleaving circuit that reads previous frame compressed A-channel and B-channel data from the second memory comprises: (i) an MSB word of the compressed A-channel word pair or the compressed B-channel word pair. Means for reading a corresponding first word and (ii) a second word corresponding to an LSB word and means for extracting bits from the first word and bits from the second word to form a pair of bits, wherein the readout The means and extracting means are configured to repeat reading and extracting until all the pair bits contained in the second memory have been read and extracted. In addition, all read and extracted paired bits all form a bit stream of 704 bits of interleaved and companded A-channel and B-channel rates, as required by the NICAM specification.

In another embodiment, the second memory of the NICAM processor includes first and second condensed data RAMs, wherein the companding and storing circuits store the condensed data in the first and second condensed data RAMs in the order described above. It further comprises means for. In addition, the interleaving circuit reading means further includes first and second bit extractors for reading from each of the first and second compressed data RAMs and extracting two bits for each access of the first and second compressed data RAMs. . Two extracted bits per access correspond to pair bits. In addition, the interval of the current frame in which the companding and storing circuit operates is during the interval before the beginning of the next frame after reading the last pair of bits from the second memory.

In yet another embodiment, the first memory stores A-channel and B-channel input data of the current frame simultaneously with interleaving circuit reading means for reading previous frame-compressed A-channel and B-channel data from the second memory. . The first clock rate includes 32 kHz, the second clock rate includes about 364 kHz (for twin bit implementation) or 728 kHz (for single bit implementation), and the third clock rate comprises about 24 MHz. The NICAM processor includes a single integrated circuit chip implementation. The first memory includes (32 X 28) RAM, and the second memory includes first and second (16 X 22) RAM. In the latter embodiment, the first and second (16 X 22) RAMs store the paired A-channel and B-channel word pairs in a pre-interleaved manner, wherein the interleaving circuit reading means is provided in an interleaved manner. Read A-channel and B-channel word pairs companded from the first and second (16 × 22) RAMs.

In an additional embodiment, the compressed A-channel and B-channel data of the current frame includes word pairs of each of the 22-bits, and the NICAM processor also performs each 22-bit, performed with respect to the companding and storage circuitry. And a scrambling circuit that scrambles paired A-channel and B-channel data word pairs, wherein the scrambler includes a (NX 22) ROM and an EX-OR gate, and also a 22-bit output of (NX 22) ROM. The first inputs of this EX-OR gate are coupled, and the 22-bit condensed A-channel and B-channel data word pairs are combined one word pair at a time with the second input of the EX-OR gate, where N is 32. In the latter embodiment, the scrambler includes a look-up table, where scrambling is reinitialized at the beginning of every frame. In addition, the companding and storing circuit for the current frame also includes a scrambler.

In another embodiment, the NICAM processor also includes a scrambler that scrambles the interleaved and compressed A-channel and B-channel data of the previous frame, wherein the scrambler includes a (M X 2) ROM and an EX-OR gate. In addition, the 2-bit output of the (MX 2) ROM is coupled with the first inputs of the EX-OR gate, and the 2-bit MSB and LSB portions of interleaved and complied A-channel and B-channel data are EX-OR. Two bits are combined at one time with the second inputs of the gate, where M is 352. In this latter embodiment, the bit stream generator may further comprise a scrambler. In addition, the scrambler may also include a look-up table, where the scrambler is reinitialized at the beginning of every frame.

In the foregoing, the present application has been described with respect to various embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of embodiments. For example, one embodiment of the present invention includes stereo audio encoders used in audio / video consumer electronic devices. Embodiments of the invention also include a NICAM encoder having a NICAM processor that includes a single-chip NICAM encoder. Embodiments of the invention also include an integrated circuit that includes a NICAM encoder with a NICAM processor, as discussed herein. Further, in addition to the embodiments described herein with respect to the first and second memories, other sizes, types, and quantities of memories with appropriate modifications and / or variations, depending on the needs of a particular NICAM processing and / or NICAM processor implementation, may be employed. Can be used.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, any element (s) that could cause benefits, advantages, solutions to problems and any benefit, benefit or solution to be created or made more apparent will be decisive and necessary in any or all claims. It is not to be construed as an essential feature or element. As used herein, “comprises”, “comprising”, or any variation thereof, allows a list of elements to be covered to cover non-exclusive results such as processes, methods, clauses or devices. The processes, methods, clauses, or apparatuses they include may not only include these elements, but may include other elements that are not explicitly listed or that are not unique to such processes, methods, clauses, or apparatuses.

Claims (21)

delete delete delete delete delete delete delete delete delete delete In the NICAM processing method, Receiving current frames of A-channel and B-channel input data and temporarily storing them in a first memory at a first clock rate; Interleaving the compressed A-channel and B-channel data of the previous frame in an interleaved format according to the requirements of the NICAM standard, thereby reducing the compressed A-channel and B-channel data of the previous frame at a second clock rate. Reading from the second memory, wherein the compressed A-channel and B-channel data of the previous frame are temporarily stored in the second memory for a previous frame in a format different from the interleaved format according to the requirements of the NICAM standard, A format different from the inverbed format according to the NICAM standard includes a dual word pre-interleaved format, wherein each dual word of the dual word pre-interleaved format is a complied A-. Reading the compressed A-channel and B-channel data of the previous frame from the second memory, the channel word and the 22-bits of the paired B-channel word pair; And Companding the A-channel and B-channel input data of the current frame and storing the compressed A-channel and B-channel input data of the current frame in the second memory in a format different from the interleaved format, A-channel and B-channel input data of the current frame, performed at a third clock rate, during the interval occurring subsequent to both storage to the first memory and reading from the second memory within the current frame. Companding and storing the companded A-channel and B-channel input data of the current frame in the second memory. delete delete delete delete 12. The method of claim 11, wherein reading the compressed A-channel and B-channel data of the previous frame from the second memory: (i) reading a first dual word and a second dual word from an address of the second memory; (ii) extracting one bit from a first word of the first dual word and one bit from a second word of the second dual word to form a pair of bits, wherein one bit from the first word is The extracting step is a double bit MSB and one bit from the second word is the double bit LSB; And (iii) repeating the read and extract steps until all pairs of bits contained in the second memory have been read and extracted, wherein the read and extracted pairs of bits are interleaved together in accordance with the requirements of the NICAM specification; And repeating forming a bit stream of 704 bits of compressed A-channel and B-channel data. delete 12. The method of claim 11, wherein the interval is before the start of the next frame after reading the last pair of bits from the second memory. 12. The method of claim 11 wherein the companded A-channel and B-channel data of the current frame each comprise 22-bit word pairs, the NICAM processing method comprising: Compressing A-channel and B-channel input data of the current frame and storing the compressed A-channel and B-channel input data of the current frame in the second memory, respectively Scrambling the paired A-channel and B-channel data word pairs, The scrambling step includes the use of (NX 22) ROM and EX-OR gate block, and the 22-bit output of (NX 22) ROM is coupled with the first inputs of the EX-OR gate block, The bit-compressed A-channel and B-channel data word pairs are combined with the second inputs of the EX-OR gate block, one word pair at a time, and N is 32. delete 12. The A-channel of claim 11, wherein the second memory comprises a first RAM and a second RAM, wherein each dual word is stored in either the first RAM or the second RAM, and the compressed A-channel of the previous frame. And reading B-channel data from the second memory comprises: (i) reading a first dual word from an address of the first RAM and reading a second dual word from an address of the second RAM, the address of the first RAM and the address of the second RAM Has the same address value, the reading step; (ii) extracting one bit from a first word of the first dual word and one bit from a second word of the second dual word to form a pair of bits, wherein one bit from the first word is The extracting step is a double bit MSB and one bit from the second word is the double bit LSB; And (iii) repeating the read and extract steps until all pairs of bits contained in the second memory have been read and extracted, wherein the read and extracted pairs of bits are interleaved together in accordance with the requirements of the NICAM specification; And repeating forming a bit stream of 704 bits of compressed A-channel and B-channel data.

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