JPS6256654B2 - - Google Patents

Info

Publication number
JPS6256654B2
JPS6256654B2 JP53112593A JP11259378A JPS6256654B2 JP S6256654 B2 JPS6256654 B2 JP S6256654B2 JP 53112593 A JP53112593 A JP 53112593A JP 11259378 A JP11259378 A JP 11259378A JP S6256654 B2 JPS6256654 B2 JP S6256654B2
Authority
JP
Japan
Prior art keywords
film
psg film
psg
sio
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53112593A
Other languages
Japanese (ja)
Other versions
JPS5539634A (en
Inventor
Yukio Takizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP11259378A priority Critical patent/JPS5539634A/en
Publication of JPS5539634A publication Critical patent/JPS5539634A/en
Publication of JPS6256654B2 publication Critical patent/JPS6256654B2/ja
Granted legal-status Critical Current

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  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は、硅燐酸ガラス膜(以下PSG膜と記
す)とこの下に燐を含有しない酸化シリコン膜が
被着されてなる半導体基板上からPSG膜を選択的
に除去するにあたり、その下側にある酸化シリコ
ン膜に影響を及ぼすことなくPSG膜のみを除去す
ることのできる半導体装置の製造方法に関する。
Detailed Description of the Invention The present invention selectively removes a PSG film from a semiconductor substrate comprising a silicophosphate glass film (hereinafter referred to as PSG film) and a silicon oxide film that does not contain phosphorus deposited thereunder. In doing so, the present invention relates to a method for manufacturing a semiconductor device in which only the PSG film can be removed without affecting the underlying silicon oxide film.

半導体基板表面の安定化のために、半導体基板
表面を二酸化シリコン膜(SiO2膜)で覆うこと
はすでによく知られているところであるが、この
SiO2膜中に可動イオンが存在した場合、形成さ
れる半導体装置の電気的特性が不安定になる。し
たがつて、かかる可動イオンをSiO2膜中から除
去することは半導体装置の特性を安定化させる上
で極めて大切である。この目的達成のために、
SiO2膜上にPSG膜を形成し、SiO2膜中の可動イ
オンをPSG膜でゲツタさせる表面安定化処理方法
がすでに提案されている。また、PSG膜をN型不
純物源として用い、PSG膜中の燐を半導体基板内
へ拡散してN形領域を形成する拡散方法もすでに
提案されている。PSG膜は上記のような使用目的
に沿つて近年広く使用されるに至つているが、反
面、PSG膜の吸質性が極めて高くこのPSG膜の適
用される半導体装置の電極材料としてアルミニウ
ムなどが用いられた場合、高温多湿の条件下にお
いて電極に腐食がもたらされるところとなる。
It is already well known that the surface of a semiconductor substrate is covered with a silicon dioxide film (SiO 2 film) in order to stabilize the surface.
If mobile ions exist in the SiO 2 film, the electrical characteristics of the formed semiconductor device will become unstable. Therefore, it is extremely important to remove such mobile ions from the SiO 2 film in order to stabilize the characteristics of the semiconductor device. To achieve this purpose,
A surface stabilization treatment method has already been proposed in which a PSG film is formed on the SiO 2 film and mobile ions in the SiO 2 film are trapped by the PSG film. Furthermore, a diffusion method has already been proposed in which a PSG film is used as an N-type impurity source and phosphorus in the PSG film is diffused into a semiconductor substrate to form an N-type region. PSG films have come to be widely used in recent years for the above-mentioned purposes, but on the other hand, the extremely high absorption properties of PSG films make it difficult to use materials such as aluminum as electrode materials for semiconductor devices to which this PSG film is applied. If used, corrosion would result in the electrode under hot and humid conditions.

したがつて、PSG膜を使用した場合には上記の
不都合を招く部分に位置するPSG膜を除去するこ
とが必要となる。従来は、かかるPSG膜の除去に
あたり、弗化水素酸を主成分とするエツチング液
を用いてエツチング処理を施すことが一般に行わ
れていた。
Therefore, when a PSG film is used, it is necessary to remove the PSG film located in the portion that causes the above-mentioned inconvenience. Conventionally, when removing such a PSG film, etching treatment was generally performed using an etching solution containing hydrofluoric acid as a main component.

このエツチング液を用いた場合には、PSG膜を
除去する所期の目的は達成されるものの、PSG膜
の下にある燐を含まないSiO2膜(化学蒸着ある
いは熱酸化で形成されたSiO2膜)までが容易に
除去されてしまう不都合が派生する。たとえば弗
化水素酸と弗化アンモニウムを体積比で1:6の
割合で混合してなるエツチング液を用いて熱酸化
によるSiO2膜と五酸化燐(P2O5)のモル濃度が20
%のPSG膜とをエツチングした場合、両者のエツ
チング速度の比は約1:6程度となり、SiO2
とPSG膜との間エツチングの選択性はみられるも
のの、それほど顕著ではなく、SiO2膜に対して
もかなりのエツチングがなされるところとなる。
When this etching solution is used, the intended purpose of removing the PSG film is achieved, but the phosphorus-free SiO 2 film (formed by chemical vapor deposition or thermal oxidation) beneath the PSG film is removed. This results in the inconvenience that even the film is easily removed. For example, using an etching solution made by mixing hydrofluoric acid and ammonium fluoride at a volume ratio of 1:6, the molar concentration of SiO 2 film and phosphorus pentoxide (P 2 O 5 ) is 20 by thermal oxidation.
% of the PSG film, the ratio of etching rates between the two is approximately 1:6, and although there is etching selectivity between the SiO 2 film and the PSG film, it is not so remarkable ; A considerable amount of etching will also be done on the surface.

本発明は、以上説明したようにPSG膜の除去に
伴いSiO2膜も除去されてしまう不都合の排除を
目的としてなされたものであり、本発明の特徴は
燐酸イオンを含む溶液たとえば燐酸溶液を用いて
PSG膜をエツチングするところにある。
As explained above, the present invention was made with the aim of eliminating the inconvenience that the SiO 2 film is also removed when the PSG film is removed. hand
This is where the PSG film is etched.

以下に図面を参照して本発明の方法について詳
述する。第1図〜第4図はPSG膜を用いてN型エ
ミツタ領域が形成される半導体集積回路用NPN
トランジスタの製造過程を示す図であり、第1図
はN型エピタキシヤル島領域1の中へ酸化膜2を
マスクとしてP型不純物たとえば硼素を拡散しP
型ベース領域3を形成し、さらにベース領域上に
形成された熱酸化膜を選択的に除去したのちの状
態を示す。次いで、P型ベース領域2の中へN型
不純物を選択的に拡散してエミツタ領域を形成す
るわけであるが、この工程でPSG膜がN型不純物
源として用いられる。
The method of the present invention will be described in detail below with reference to the drawings. Figures 1 to 4 show NPN for semiconductor integrated circuits in which an N-type emitter region is formed using a PSG film.
FIG. 1 is a diagram showing the manufacturing process of a transistor, and FIG.
The state after forming the mold base region 3 and selectively removing the thermal oxide film formed on the base region is shown. Next, an N-type impurity is selectively diffused into the P-type base region 2 to form an emitter region, and the PSG film is used as an N-type impurity source in this step.

第2図はPSG膜を用いてN型エミツタ領域の形
成されたのちの状態を示す図であり、図中4が
PSG膜であり、5がPSG膜中の燐を拡散させて形
成したN型エミツタ領域である。かかるエミツタ
領域5の形成は次のようにしてなされる。すなわ
ち、化学蒸着法によりP2O5のモル濃度がたとえ
ば20%となるようなPSG膜4を約5000Åの厚さに
形成したのち1000〜1100℃の温度で熱処理を施こ
せばよい。
Figure 2 shows the state after the N-type emitter region is formed using the PSG film, and 4 in the figure shows the state after the N-type emitter region is formed.
This is a PSG film, and 5 is an N-type emitter region formed by diffusing phosphorus in the PSG film. The emitter region 5 is formed as follows. That is, after forming the PSG film 4 with a thickness of about 5000 Å with a molar concentration of P 2 O 5 of, for example, 20% by chemical vapor deposition, heat treatment may be performed at a temperature of 1000 to 1100°C.

このようにしてN型エミツタ領域5を形成した
のちPSG膜4のみを選択的に除去するわけである
が、燐酸イオンを含むエツチング液として燐酸溶
液を使用する。この燐酸溶液をたとえば150〜180
℃に加熱し、この中へ半導体基板を約15分間浸漬
することによつてPSG膜のみが選択的に除去され
る。
After forming the N-type emitter region 5 in this manner, only the PSG film 4 is selectively removed, and a phosphoric acid solution is used as the etching solution containing phosphate ions. For example, add this phosphoric acid solution to 150 to 180
Only the PSG film is selectively removed by heating to 0.degree. C. and immersing the semiconductor substrate therein for about 15 minutes.

たとえば、160℃に加熱された燐酸溶液(濃度
80%)でSiO2膜とP2O5のモル濃度が20%のPSG
膜をエツチングした場合、両者のエツチング速度
は前者が12Å/分、後者が500Å/分であり、エ
ツチング速度の比は約1:40となり、極めて大き
な選択性が示される。したがつて、上記のPSG膜
4の除去に際してはPSG膜4の下にあるSiO2膜は
殆んどエツチングされることはない。第3図は以
上の過程を経てPSG膜のみが選択的に除去された
のちの状態を示す。こののち必要であれば第4図
で示すように半導体基板上にたとえば化学蒸着法
によるSiO2膜6を設け、表面保護をより強化し
てもよい。
For example, a phosphoric acid solution heated to 160°C (conc.
80%) with SiO 2 film and PSG with 20% molar concentration of P 2 O 5
When etching the film, the etching rate for the former is 12 Å/min and the latter is 500 Å/min, and the ratio of the etching rates is approximately 1:40, indicating extremely high selectivity. Therefore, when removing the PSG film 4, the SiO 2 film below the PSG film 4 is hardly etched. FIG. 3 shows the state after only the PSG film has been selectively removed through the above process. Thereafter, if necessary, a SiO 2 film 6 may be provided on the semiconductor substrate by, for example, chemical vapor deposition, as shown in FIG. 4, to further strengthen the surface protection.

以上説明してきたところから明らかなように、
本発明の方法によれば、燐を含まない酸化膜に影
響を及ぼすことなくPSG膜のみ選択的に除去する
ことができ、したがつて、同一半導体基板上にお
けるPSG膜の厚さが不均一であること、あるい
は、半導体基板相互間においてPSG膜の厚さが不
均一であることなどの問題があつたとしてもこの
ことによる影響を受けることがなく、一度に大量
の処理が可能となり製造能率を高めることが可能
になる。また、不要なPSG膜のみの除去が確実と
なるため得られる半導体装置の信頼性を高める効
果も奏される。
As is clear from what has been explained above,
According to the method of the present invention, only the PSG film can be selectively removed without affecting the oxide film that does not contain phosphorus, and therefore the thickness of the PSG film on the same semiconductor substrate is non-uniform. Even if there is a problem such as uneven thickness of the PSG film between semiconductor substrates, it will not be affected by this problem, and it will be possible to process a large amount at once, increasing manufacturing efficiency. It becomes possible to increase it. Furthermore, since only the unnecessary PSG film can be removed reliably, the reliability of the obtained semiconductor device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は本発明の方法の適用された半
導体集積回路用NPNトランジスタの製造過程を
示す図である。 1……N型エピタキシヤル島領域、2……酸化
膜、3……P型ベース領域、4……PSG膜、5…
…N型エミツタ領域、6……化学蒸着による
SiO2膜。
1 to 4 are diagrams showing the manufacturing process of an NPN transistor for a semiconductor integrated circuit to which the method of the present invention is applied. DESCRIPTION OF SYMBOLS 1... N-type epitaxial island region, 2... Oxide film, 3... P-type base region, 4... PSG film, 5...
...N-type emitter region, 6...by chemical vapor deposition
SiO2 film.

Claims (1)

【特許請求の範囲】[Claims] 1 硅燐酸ガラス膜とこの下に燐を含有しない酸
化シリコン膜が被着されてなる半導体基板上の前
記硅燐酸ガラス膜を選択的にエツチングするにあ
たり、燐酸溶液を硅燐酸ガラスに作用させて前記
硅燐酸ガラス膜をエツチングすることを特徴とす
る半導体装置の製造方法。
1. When selectively etching the silicophosphate glass film on a semiconductor substrate, which is formed by depositing a silicophosphate glass film and a silicon oxide film that does not contain phosphorus therebelow, a phosphoric acid solution is applied to the silicophosphate glass to selectively etch the silicophosphate glass film. A method for manufacturing a semiconductor device, characterized by etching a silicophosphate glass film.
JP11259378A 1978-09-12 1978-09-12 Manufacture of semiconductor Granted JPS5539634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11259378A JPS5539634A (en) 1978-09-12 1978-09-12 Manufacture of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11259378A JPS5539634A (en) 1978-09-12 1978-09-12 Manufacture of semiconductor

Publications (2)

Publication Number Publication Date
JPS5539634A JPS5539634A (en) 1980-03-19
JPS6256654B2 true JPS6256654B2 (en) 1987-11-26

Family

ID=14590613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11259378A Granted JPS5539634A (en) 1978-09-12 1978-09-12 Manufacture of semiconductor

Country Status (1)

Country Link
JP (1) JPS5539634A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2820065B2 (en) * 1995-04-27 1998-11-05 日本電気株式会社 Method for manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952779A (en) * 1972-09-25 1974-05-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4952779A (en) * 1972-09-25 1974-05-22

Also Published As

Publication number Publication date
JPS5539634A (en) 1980-03-19

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