JPS6256512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a matrix display device using a matrix panel having LEDs, discharge cells, etc. as light-emitting pixels, and particularly to reducing the peak current capacity of a driver element for vertical scanning. At the same time, the purpose is to significantly reduce power consumption.

This type of matrix display device has a configuration as generally shown in the block diagram of FIG.

Matrix panel M forms a unit picture element
Light-emitting elements such as LEDs and plasma cells are arranged in a matrix, and X and Y electrodes are provided using Nesa film, etc., along the arrangement of each element in the X and Y directions, and signals are sent to the corresponding light-emitting element at the intersection of each electrode. The structure is such that it can be activated by a PWM signal with a pulse width proportional to .

Then, to the electrodes parallel to the Y direction, signals for one horizontal (X direction) are simultaneously applied to each electrode via the signal side driver SD, and to the X direction electrodes are sequentially applied via the vertical scanning driver VD. A scanning pulse is supplied to sequentially light up the light-emitting picture elements line by line (arrayed in the X direction) to form an image.

The arrangement of light-emitting pixels of matrix panel M is
Taking the case of 160 in the direction and 120 in the Y direction as an example, the vertical scanning driver VD generates sequential pulses of 2H (H is the horizontal synchronization period of the original video signal) synchronized with the output of the sync separation circuit SS. Scanning pulse generation circuit
Add TG output. In addition, the signal side driver SD adds the output of the A-D conversion circuit AD, which digitally converts the original video signal in, for example, 16 levels of gradation, to the line memory LM, and presets the serial-parallel converted signal (4-bit data). As an example, the output of a PWM modulation circuit PWM, which is a combination of a down counter and a flip-flop circuit that counts down a clock pulse that is a multiple of the horizontal synchronization signal, is applied to each signal electrode (160 in total) in a corresponding manner.

Figure 2 is for explaining the problems of the conventional example.
Only the parts connected to one scanning electrode and 160 signal electrodes of the drive circuit of the LED matrix panel are taken out.

SD1...SD160 indicates each output transistor of the signal side driver SD, and each base resistor R1
...R160 limits the peak current flowing through each LED to a constant value.

The unit output circuit of the vertical driver VD consists of an output transistor VD ₁ and a Darlington connection installed at the front stage so that VD ₁ can be sufficiently driven by the output of the C-MOSIC.
Consists of PVD ₁ .

The output transistor VD ₁ is a signal side driver
Current I1... supplied by SD1...SD160
It is essential to have enough capacity to flow the total current of I160. And 60m for one signal electrode
Since the current Ap-p flows, a total pulse current of 9600 mA flows through the output transistor _VD1 .

To pass a current of 9.6Ap-p through the driver VD ₁ ,
Even if a transistor with a large DC current amplification factor _hFE is used, it will actually fall to about 10th, so the Darlington connection at the front stage must have a capacity of 960 mAp-p.

Therefore, in the conventional example, the pulse C in Figure 3 every 2H is used as the load pulse of the down counter,
Input parallel data of line memory to preset,
By counting the clock pulses (for PWM) (FIG. 3 B) and using the count output to reset the flip-flop circuit set by the load pulse, the PWM signal (FIG. 3 D, H) is calculated. and f), even when the brightness level is low, the output transistor VD ₁ is always required to have a capacity of 9600 mA at its peak, and an increase in power consumption is unavoidable.

The present invention was developed in view of the drawbacks of the conventional example, and basically divides the signal electrode into two blocks, and one block receives the PWM leading edge modulation signal.
By adopting a configuration in which PWM trailing edge modulation is applied to the other block, the drawbacks of the conventional example mentioned above are improved.

The details of the present invention will be explained below with reference to FIGS. 4 and 5 showing main circuit block diagrams and FIG. 6 showing an explanatory diagram of operating waveforms.

In the following explanation, an example will be explained in which the signal electrode block of the matrix panel is divided into left and right halves (,), but other methods may also be used, such as dividing it into two blocks of odd numbers and even numbers. good.

In Fig. 4, which shows the block diagram of the main part, indicates the A block signal processing series, and indicates the B block signal processing series.
Each block signal processing sequence is shown.

The A block is the output (4) of the A-D converter circuit AD.
A line memory LM ₁ consisting of a serial input parallel output shift register that receives a clock signal (bit unit) as an input, a clock pulse (Fig. 6 b) generation circuit CL ₁ , and a fifth
The main part block diagram is shown in the figure.
Consists of PWM circuit PWM ₁ and A signal driver SDA.

The line memory _LM1 has a capacity of 80 bits for each of the 4 bits of brightness level digital information. The clock pulse generation circuit CL ₁ is configured to generate a pulse train whose pulse width is successively changed by γ correction in synchronization with the output of the synchronization signal separation circuit. 73568
I will omit the explanation as it is disclosed in the issue. PWM circuit PWM ₁ provided as many as the number of signal electrodes in A block
is basically a down counter as shown in Figure 5.
It consists of DC and flip-flop circuit FF.
The down counter DC takes in the 4-bit data of the line memory _LM1 by applying a load pulse (D in Fig. 6), counts clock pulses (B in Fig. 6) according to the value, and outputs the count. Then, reset the flip-flop circuit FF. Since the flip-flop circuit is previously set by the load pulse (FIG. 6 D), the pulse width modulation as shown in FIG. The output is supplied to the A signal driver SDA.

Next, the B block includes an inverter IN 1 that inverts the luminance digital information (4 bits each) transferred via the line memory LM ₁ , and an inverter IN ₁ that inverts the luminance digital information (4 bits each) transferred via the line memory LM 1, and inverts each bit of the 4-bit luminance information using the inverted output as input. As shown in Fig. 6C, the pulse width changes between _2H and the pulse width in Fig. 6B is exactly opposite to the pulse width in Fig. 6B, as shown in Fig. 6C. A clock pulse generation circuit CL ₂ that generates clock pulses (symmetrical about the midpoint 1H of the period 2H), a PWM circuit PWM ₂ as shown in the outline in FIG. 5, an inverter IN ₂ that inverts the PWM output, and a B signal. driver
Consists of SDB.

With this configuration, if the brightness level is "5" now, the output of the inverter IN ₁ will be:
Digital data obtained by inverting "0101" becomes "1010", that is, level 10.

Therefore, the down counter (DC in Figure 5) is preset to "1010" by the arrival of the load pulse and counts 10 clock pulses, so
The output of the PWM circuit is from 0 to 10 of the clock pulse.
The value up to 15 is “1”, and the value up to 15 is “0”.

This PWM output is inverted by inverter IN ₂ and
It is symmetrical (FIG. 6 H) with respect to the input waveform of the A signal driver (FIG. 6 G) with the scanning midpoint M as the center.

PWM circuit of the A block signal processing series
PWM ₁ is a method that fixes the leading edge of the pulse and modulates the trailing edge, so PWM circuit PWM ₂ of the B block signal processing system fixes the trailing edge of the pulse and modulates the leading edge. Since it is a method to do this, it is called a leading edge modulation (method). (Refer to "Color TV display using a 10-inch flat solar column type gas discharge panel" in the Technical Report of the Television Society, Vol. 2, No. 3, pp. 107-116) With this configuration, as an example, there are currently 160 signal electrodes. Assuming that pulses such as those shown in FIG. At that time, h _FE of the output transistor VD ₁ of the vertical driver VD is:
9.6Ap-p becomes larger (for example,
h _FE = 13 for 8App, h _FE = 32 for 4App), the current flowing through the Darlington connected transistor PVD is a fraction of that of 9.6A, which greatly reduces the power consumed by PVD and VD. Can be done.

In addition, when the luminance level of the original signal is high and the signal side driver SD is driven by a PWM signal with a pulse width exceeding the scanning midpoint M, the central part has 9.6 A for the T period as shown in FIG. However, since the peak period is significantly reduced compared to the conventional example, power consumption is significantly reduced. When the brightness is constant, such as in a character display, the current capacity of the vertical driver can be halved compared to the conventional one by setting the clock pulses at equal intervals and setting the modulation pulse width to H or less. In short, according to the present invention, it is possible to reduce the maximum capacity of a vertical driver and reduce power consumption in a matrix display device.

[Brief explanation of the drawing]

1 to 3 relate to a conventional example, in which FIG. 1 is a block diagram of a main part of a matrix display device, FIG. 2 is a circuit diagram of a main part, and FIG. 3 is an explanatory diagram of operating waveforms. 4 to 6 relate to the present invention, FIG. 4 is a block diagram of the main part, and FIG. 5 is a block diagram of the main part.
The block diagram of the PWM circuit, FIG. 6, is an explanatory diagram of operating waveforms. PWM ₁ , PWM ₂ ……PWM
Circuit, AD...A-D conversion circuit, LM ₁ , LM ₂ ...
Line memory, SD...signal driver.

Claims (1)

[Claims] 1. A matrix panel having a plurality of scanning electrodes, a plurality of signal electrodes, and a plurality of display elements arranged in a matrix, a PWM circuit that controls the pulse width applied to the signal electrodes, and sequentially selecting the scanning electrodes. A matrix display device comprising a first signal electrode group, a second signal electrode group, and a first clock pulse generation circuit that generates a first pulse train whose pulse width is successively changed. , a second clock pulse generation circuit that generates a second pulse train that is symmetrical with respect to the first pulse train with respect to the midpoint of the unit vertical scanning pulse period;
a first PWM circuit that counts the first pulse train, performs trailing edge modulation on the A/D conversion output of the video signal to be displayed as a modulation data signal, and energizes the first signal electrode group with this output; A matrix display device comprising a second PWM circuit that counts a pulse train, modulates the leading edge of an A/D converted output of a video signal to be displayed as a modulated data signal, and energizes the second signal electrode group with this output.