JPH0326549Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field This invention is applicable to liquid crystal display devices and light emitting diodes.
The target is a display device using a matrix panel consisting of elements, etc.

(b) Prior art Liquid crystal televisions using LCD matrix panels (hereinafter simply referred to as LCD panels) have been proposed as display devices as described above, and the schematic structure thereof is disclosed in, for example, Japanese Patent Laid-Open No. 57-41078. It is stated in the publication number etc. The panel display section of such a liquid crystal television is generally constructed as shown in FIG. That is, 1 is an LCD panel in which unit display elements constituting one pixel are arranged in a matrix by an X electrode group and a Y electrode group, 2 is a Y electrode driver circuit consisting of a shift register 3 and a sample hold circuit 4, and 5 is a Y electrode driver circuit. is an X electrode driver circuit consisting of a shift register. Further, 6 is a sync separation circuit, and 7 is a Y-side pulse generation circuit, which obtains the horizontal sync pulse from the sync separation circuit 6 and supplies the clock pulse CP and start pulse ST ₁ ( (see Figure 5).
Furthermore, this pulse generating circuit 7 holds (latches) the horizontal synchronization given to the sample hold circuit 4.
Also creates pulse HD. On the other hand, 8 is an X-side pulse generation circuit, which generates a start pulse _ST2 synchronized with the vertical synchronization pulse from the synchronization separation circuit 6. Note that the hold pulse HD is also given as a shift pulse to the X electrode driver circuit 5. Note that Q ₁ , Q ₂ , Q ₃ . . . in FIG. 5 represent the outputs of each stage of the shift register 3 in the Y electrode driver circuit.

By the way, the number of stages of the shift registers 3 and 5 is determined in the X direction (row direction) and Y direction of the panel 1, respectively.
Equal to the number of elements in the direction (column direction), for example, the former 3
The latter has 480 steps, and the latter 5 has 220 steps, which is an extremely large number of steps. Therefore, each of the above-mentioned shift registers 3 and 5 cannot be constructed with a single-chip IC.
Therefore, several shift register ICs are connected in series, but in this case, each of the above
It is used by constantly supplying clock CP and pulse (HD) to the IC.

(c) Problems to be solved by the invention However, in the above configuration, while the Y electrode driver circuit 2 and the X electrode driver circuit 5 are operating, each of the shift registers 3 and 5 is always in a shifting operation. For this reason, each of the above driver circuits 2,
5 had the disadvantage of extremely high power consumption.

Therefore, an object of the present invention is to reduce power consumption in an electrode driver circuit in a matrix panel display device.

(d) Means for solving the problem In the present invention, at least one of the X and Y electrode driver circuits is divided into a plurality of blocks each corresponding to one to several electrodes, and each block is divided into Drive pulses are supplied in sequence.

(E) Effect According to the above configuration, one of the plurality of blocks is selected in order, and only the selected block is sequentially operated, so that the power consumption of the electrode driver circuit is equal to that of one block. equals power.

(F) Embodiment FIG. 1 shows an embodiment of the present invention.
Corresponding parts with the figures are given the same figure numbers. In this embodiment, the LCD panel 1 has 480 Y electrodes and 220 X electrodes (480 x 220 elements), like the one in FIG. The even-numbered lead wires of the electrodes are drawn out on the upper side, and those of the even-numbered electrodes are drawn out on the lower side, and the first and second Y-electrode driver circuits 2 and 2' are connected to the odd-numbered and even-numbered Y electrodes, respectively. There is.

The first Y electrode driver circuit 2 has a power of 48
A shift register section 3 consisting of five stage shift register ICs, Sy ₁ to _{Sy 5} , connected in series; a sample hold circuit 4 to which the output of each stage is applied as a sampling pulse; and each of the above ICs, Sy _{1 to Sy 5} . Gate circuit that controls the cutoff of clock CP supply to Sy ₅
It consists of a clock pulse control section 9 having clock pulses Gy ₁ to Gy ₅ . Furthermore, since the second Y electrode driver circuit 2' is configured in exactly the same way, it is shown with the same symbol as the first Y electrode driver circuit 2 with a dash attached.

Each gate circuit in the clock pulse control section 9 has two gate circuits, Gy ₁ to Gy ₂ , as shown in FIG.
It consists of an AND gate Aa connected to the clock terminal CK side of each shift register IC, an RS flip-flop F that opens and closes this AND gate, an AND gate Ab and an inverter I provided on the reset terminal R side. . And especially 1
In the gate circuit Gy ₁ of the stage, the start pulse ST ₁ is applied to the set terminal S of the flip-flop F and the inverter I, but in the gate circuits Gy ₂ , Gy ₃ . . . of the second and subsequent stages, the set terminal S and the inverter I is the shift register IC of the stage immediately before it,
The outputs Qm ₁ , Qm ₂ ... of the final stage of Sy ₁ to Sy ₂ ... are respectively given, and one input of each AND gate Ab in the gate circuits Gy ₁ , Gy ₂ ... of each stage is provided. are given the final stage outputs Qm ₁ , Qm _{2 . .} . of their own stage ICs, Sy ₁ , Sy ₂ . The reason why the AND gate Ab and inverter I are provided on the reset terminal R side of each flip-flop F is to adjust the reset timing of each flip-flop F to each shift register IC,
By slightly delaying the rise of the final stage output of Sy ₁ , Sy ₂ ..., the final stage output can be made to
This is to ensure that the voltage is applied to the IC.

On the other hand, the X electrode driver circuit 5 provided for the 220 X electrodes of the panel 1 has 60
A shift register section 10 formed by cascading four shift register ICs, Sx ₁ to Sx ₄ , and each of its ICs.
The shift pulse control section 11 includes gate circuits Gx ₁ to _{Gx 4} that control the supply and cutoff of shift pulses HD to the shift pulses HD. Then, the control section 1
The internal configuration of circuit 1 is similar to that shown in Figure 2 above, and the clock pulse input to the circuit in Figure 2 is
The configuration is such that CP is replaced with shift pulse HD, and start pulse ST ₁ is replaced with start pulse ST ₂ .

Next, the Y-side pulse generation circuit 7 has a duty of 50
% of the 4.8MHz clock pulse CP, a start pulse _ST1 that rises at the beginning of the effective video section within one horizontal period 1H, and a clock pulse CP that is higher than this pulse _ST1 .
Start pulse delayed by 1/2T for 1/2 cycle of
It is now possible to create ST′ ₁ . Further, the video signal switching circuit 12 distributes the input video signal to the sample and hold circuits 4 and 4' every 1/2T by the clock CP, but the X-side pulse generation circuit 8 is configured as shown in FIG. It has exactly the same configuration.

Since this embodiment is configured as described above, the
In the 1Y electrode driver circuit 2, the clock pulse control circuit 9 sequentially controls the AND gates Aa in each gate circuit Gy ₁ to _{Gy 5} every time 48 clocks CP are supplied from the time when the start pulse ST ₁ is applied. Open to. The 48 clock pulse groups CP ₁ to _{CP 5} (see Figure 3) that have passed through each AND gate Aa are supplied to each shift register LC, Sy ₁ to _{Sy 5} , and output from each stage of each IC. is applied to the sample hold circuit 4 as a sampling pulse. Qm ₁ , Qm ₂ . . . in FIG. 3 indicate the final stage output of each IC, respectively. Similarly, the gate circuits Gy ₁ ′ to _{Gy 5} ′ in the clock pulse control circuit 9 also operate, but the start pulse supplied to this control circuit
ST ₁ ′ is 1/2T behind the aforementioned ST ₁ , and
Clock pulse CP' is also inverted by inverter 13, so that it lags behind CP by 1/2T. Therefore, the video signals corresponding to two display elements adjacent in the row direction of the matrix panel 1 are alternately sampled and held by the two sample and hold circuits 4 and 4'.

In addition, since two elements are driven within one clock cycle 1T, assuming that the effective video period within 1H is 50 μsec, the frequency of the above clock CP is 480 ÷ 2 ÷ 50 =
This means that it is 4.8MHz.

Also, in the X electrode driver circuit 5, 60 shift pulses HD are supplied to each shift register IC, Sx ₁ to Sx ₄ , in the same manner as described above.
The output of each stage is applied to the 220 X electrodes of the matrix panel 1.

In this manner, in this embodiment, the matrix panel 1 can be driven for display without any inconvenience, and the power consumption in the first and second Y electrode driver circuits 2, 2' and the X electrode driver circuit 5 is reduced. That is, unless the power consumption in the clock pulse control circuits 9, 9' and the shift pulse control circuit 11 are considered, the power consumption in the Y electrode driver circuits 2, 2' is approximately 1/5 of that in the case of FIG. Therefore, it is reduced to nearly 1/4 in the X electrode driver circuit 5. However, the actual power consumption will be larger than the above values due to the control circuits 9, 9' and 11.

In this embodiment, each of the control circuits 9, 9'
and each gate circuit in 11 is a shift register IC
were set up in a one-to-one correspondence with each of the
One may be provided for every several stages in the IC, and the number may be determined based on the balance between the degree of reduction in power consumption and the increase in cost due to an increase in the number of parts.

Furthermore, the Y electrode driver circuit need not be divided into two lines 2 and 2' as in the present embodiment, but may of course be provided as one line as shown in FIG.

Furthermore, in this embodiment, each shift register IC and sample hold circuit of the first and second Y electrode driver circuits 2 and 2' have been described as being provided separately from each other, but it is assumed that both of them are integrated into an IC. But that's fine.

(g) Effects of the invention According to the drive circuit of the invention, the power consumption in the electrode driver circuit in a matrix panel display device such as a liquid crystal television can be significantly reduced, and the above device can be made smaller. It also contributes to the development and portability of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a matrix panel display device to which the present invention is applied, and FIG. 2 is a block diagram showing an example of a specific circuit of the main part thereof.
FIG. 3 is an operational waveform diagram of the main part. FIG. 4 is a block diagram showing a schematic configuration of a conventional matrix panel display device, and FIG. 5 is an operational waveform diagram of its main parts. 1... Matrix panel, 2, 2'... Y electrode driver circuit, 5... X electrode driver circuit,
3, 3', 10...shift register section, 9, 9',
11...Control circuit.

Claims (1)

[Claims for Utility Model Registration] A Y electrode driver circuit consisting of a panel 1 in which display elements are arranged in a matrix by X and Y electrode groups, shift registers 3, 3', and sample and hold circuits 4, 4'. 2, 2', and an X electrode driver circuit 5 consisting of a shift register, in which at least one shift register of both the driver circuits 2, 5 corresponds to a plurality of electrodes, respectively. A plurality of blocks Sy ₁ to _{Sy 5} , Sy′ ₁ to Sy′ ₅ ,
It is divided into Sx ₁ to Sx ₄ , and consists of a plurality of gate circuits Gy ₁ to _{Gy 5} , Gy′ ₁ to Gy′ ₅ , Gx ₁ to Gx ₄ provided for each block,
Each of these gate circuits, except for the first stage, is opened by the final stage outputs Qm ₁ to _{Qm 5} of the previous stage block and closed by the final stage output of the block concerned, so that the drive pulse is generated for each block. A drive circuit for a matrix panel display device, which is provided with control circuits 9, 9', and 11 for supplying and cutting off the pulses, and supplies the drive pulses to each block in sequence by the control circuits.