JPS6255177U - - Google Patents
Info
- Publication number
- JPS6255177U JPS6255177U JP14657185U JP14657185U JPS6255177U JP S6255177 U JPS6255177 U JP S6255177U JP 14657185 U JP14657185 U JP 14657185U JP 14657185 U JP14657185 U JP 14657185U JP S6255177 U JPS6255177 U JP S6255177U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- brightness
- inverting input
- input terminal
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Description
第１図及び第２図は本考案の一実施例を示す回
路図である。第３図は従来の輝度制御回路の例を
示す図。
１：輝度電流制御用可変抵抗器、３：ＮＰＮ形
トランジスタ、４：輝度増幅器、５：ブラウン管
、６：電流増幅回路、７：差動増幅器、１０：入
力電流、１１：出力電流（輝度電流）。
1 and 2 are circuit diagrams showing one embodiment of the present invention. FIG. 3 is a diagram showing an example of a conventional brightness control circuit. 1: Variable resistor for brightness current control, 3: NPN transistor, 4: Brightness amplifier, 5: Braun tube, 6: Current amplifier circuit, 7: Differential amplifier, 10: Input current, 11: Output current (brightness current) .
Claims (1)
動端と直列に接続された抵抗と、該抵抗の他端に
反転入力端を接続し、非反転入力端を接地した差
動増幅器と、該差動増幅器の出力端とベースを接
続し、エミツタを抵抗を介して接地し、コレクタ
を次段の輝度増幅器に接続したトランジスタと、
該トランジスタのエミツタと前記差動増幅器の反
転入力端との間に接続した抵抗より成る輝度制御
回路。 a brightness current control variable resistor, a resistor connected in series with a sliding end of the variable resistor, a differential amplifier having an inverting input terminal connected to the other end of the resistor and a non-inverting input terminal grounded; a transistor whose output terminal and base of the differential amplifier are connected, whose emitter is grounded via a resistor, and whose collector is connected to a brightness amplifier at the next stage;
A brightness control circuit comprising a resistor connected between the emitter of the transistor and the inverting input terminal of the differential amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14657185U JPH0532872Y2 (en) | 1985-09-27 | 1985-09-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14657185U JPH0532872Y2 (en) | 1985-09-27 | 1985-09-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6255177U true JPS6255177U (en) | 1987-04-06 |
| JPH0532872Y2 JPH0532872Y2 (en) | 1993-08-23 |
Family
ID=31059158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14657185U Expired - Lifetime JPH0532872Y2 (en) | 1985-09-27 | 1985-09-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0532872Y2 (en) |
-
1985
- 1985-09-27 JP JP14657185U patent/JPH0532872Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0532872Y2 (en) | 1993-08-23 |
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