JPS6253517A - 信号駆動回路 - Google Patents

信号駆動回路

Info

Publication number
JPS6253517A
JPS6253517A JP60194110A JP19411085A JPS6253517A JP S6253517 A JPS6253517 A JP S6253517A JP 60194110 A JP60194110 A JP 60194110A JP 19411085 A JP19411085 A JP 19411085A JP S6253517 A JPS6253517 A JP S6253517A
Authority
JP
Japan
Prior art keywords
signal
switch
circuit
nodes
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60194110A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0443446B2 (enExample
Inventor
Tetsuya Iizuka
飯塚 哲哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60194110A priority Critical patent/JPS6253517A/ja
Publication of JPS6253517A publication Critical patent/JPS6253517A/ja
Publication of JPH0443446B2 publication Critical patent/JPH0443446B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)
JP60194110A 1985-09-03 1985-09-03 信号駆動回路 Granted JPS6253517A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60194110A JPS6253517A (ja) 1985-09-03 1985-09-03 信号駆動回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60194110A JPS6253517A (ja) 1985-09-03 1985-09-03 信号駆動回路

Publications (2)

Publication Number Publication Date
JPS6253517A true JPS6253517A (ja) 1987-03-09
JPH0443446B2 JPH0443446B2 (enExample) 1992-07-16

Family

ID=16319088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60194110A Granted JPS6253517A (ja) 1985-09-03 1985-09-03 信号駆動回路

Country Status (1)

Country Link
JP (1) JPS6253517A (enExample)

Also Published As

Publication number Publication date
JPH0443446B2 (enExample) 1992-07-16

Similar Documents

Publication Publication Date Title
KR100347144B1 (ko) 고전압 발생회로
US5677645A (en) Vccp pump for low voltage operation
US5786711A (en) Data output buffer for use in a semiconductor memory device
US5828095A (en) Charge pump
US6208197B1 (en) Internal charge pump voltage limit control
US4508978A (en) Reduction of gate oxide breakdown for booted nodes in MOS integrated circuits
JPS62500063A (ja) 電子信号の立上り時間改良用補助回路
US4638182A (en) High-level CMOS driver circuit
US6215329B1 (en) Output stage for a memory device and for low voltage applications
JP2915625B2 (ja) データ出力回路
JP2733578B2 (ja) Cmosラッチ回路
US4894559A (en) Buffer circuit operable with reduced power consumption
US5369320A (en) Bootstrapped high-speed output buffer
US4352996A (en) IGFET Clock generator circuit employing MOS boatstrap capacitive drive
KR0159324B1 (ko) 데이터 출력회로
EP0342592B1 (en) Chip enable input circuit in semiconductor memory device
US6430093B1 (en) CMOS boosting circuit utilizing ferroelectric capacitors
US6864738B2 (en) CMOS voltage booster circuits
US4636657A (en) High speed CMOS clock generator
KR100316982B1 (ko) 2개의 n-채널 mos 트랜지스터로 구성된 푸시풀형 출력회로를 갖는 반도체 메모리 장치
KR100362897B1 (ko) 전하 재사용을 이용한 저 소비전력 메모리 및 비메모리 장치
JPH06105875B2 (ja) 半導体集積論理回路
KR100596748B1 (ko) 다이내믹 시모스 로직
JPH0443446B2 (enExample)
JP3083654B2 (ja) 出力回路

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term