JPS6251501B2 - - Google Patents
Info
- Publication number
- JPS6251501B2 JPS6251501B2 JP4031981A JP4031981A JPS6251501B2 JP S6251501 B2 JPS6251501 B2 JP S6251501B2 JP 4031981 A JP4031981 A JP 4031981A JP 4031981 A JP4031981 A JP 4031981A JP S6251501 B2 JPS6251501 B2 JP S6251501B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- package
- semiconductor device
- present
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 230000001681 protective effect Effects 0.000 claims description 10
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 238000005452 bending Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にパツケージおよびリ
ードの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to package and lead structures.
近年、電子機器の小形化に伴ないIC等の半導
体装置に対し、パツケージ外形を小形化するいわ
ゆる高密度実装に適したものが要求されるように
なつている。 In recent years, with the miniaturization of electronic equipment, there has been a demand for semiconductor devices such as ICs that are suitable for so-called high-density packaging, which reduces the size of the package.
従来のICのパツケージは第１図ａ，ｂで示す
ように、トランスフアーモルドレジンで構成され
ている所から、電気的な接続を目的とする必要本
数のリード１がレジン本体２の外部に出ている。
ICパツケージの信頼性からリード１はその成形
時にレジン本体２から可能な限り遠く離れ（例え
ばａ）た所で、リード成形する方法を採用してい
る。これは、レジン本体２にリード成形時の機械
的なストレスを与えないような配慮からである。
しかしながら、このような外形はIC部品を搭載
する実装設計上は、ICパツケージの占める実装
面積を大きくしていることに他ならない。特に、
同図ｂで示すように、リード１の先端を水平方向
に外方に折り曲げて接続部３を設けたIC（半導
体装置）では実装面積が広くなる。 As shown in Figures 1a and 1b, the conventional IC package is made of transfer molded resin, and the necessary number of leads 1 for the purpose of electrical connection extend outside the resin body 2. ing.
For the reliability of the IC package, a method is adopted in which the lead 1 is molded as far away from the resin body 2 as possible (for example, point a). This is to avoid applying mechanical stress to the resin body 2 during lead molding.
However, such an external shape only increases the mounting area occupied by the IC package in terms of packaging design for mounting IC components. especially,
As shown in FIG. 1B, an IC (semiconductor device) in which a connecting portion 3 is provided by bending the tip of a lead 1 outward in a horizontal direction has a large mounting area.
そこで本発明は信頼性を損うことなく、外形の
大きさ（実装面積）を小さくし、高密度実装に適
した半導体装置を提供することにある。 Therefore, an object of the present invention is to provide a semiconductor device that has a reduced external size (mounting area) and is suitable for high-density packaging without impairing reliability.
また、最近では外形の小形化軽量化（薄形化）
からリードフレームの板厚が薄くなる傾向にあ
り、この場合、特にリードの機械的強度が弱くな
る。このため、工程内、出荷時の取り扱い時にリ
ードに外力が加わつたりすると、リードは簡単に
曲がりリード曲りなどの不良が生じやすくなる。 In addition, recently, the outer size has become smaller and lighter (thinner).
As a result, the thickness of the lead frame tends to become thinner, and in this case, the mechanical strength of the leads in particular becomes weaker. For this reason, if an external force is applied to the lead during handling during the process or during shipping, the lead easily bends and defects such as lead bending are likely to occur.
したがつて、本発明の他の目的は、リードの変
形を防止することにある。 Therefore, another object of the present invention is to prevent lead deformation.
このような目的を達成するために本発明は、パ
ツケージの周面から突出するリードが途中で一方
向に折れ曲がつてなるインライン形の半導体装置
において、前記リードはその先端を除く部分がパ
ツケージに設けた保護溝内に入つた構造となつて
いるものであつて、以下実施例により本発明を説
明する。 In order to achieve such an object, the present invention provides an in-line type semiconductor device in which a lead protruding from the peripheral surface of a package is bent in one direction in the middle, and the lead has a portion other than its tip that is attached to the package. The present invention will be described below with reference to Examples.
第２図および第３図は本発明の一実施例による
半導体装置を示す図であつて、第２図は外観を示
す斜視図、第３図は一部を切り欠いた正面図であ
る。これらの図で示すように、この半導体装置４
はトランスフアモールドによつて形作られるレジ
ンからなるパツケージ５と、このパツケージ５の
両側部に配設された複数の金属からなるリード６
とからなつている。リード６の付け根から下方に
向かつてパツケージ５の下半分には保護溝７が設
けられている。この保護溝７はリード６が入るに
充分な幅を有するとともに、インライン形のリー
ド６が没するに充分な深さを有している。また、
リード６は保護溝底からａだけ離れた位置で下方
に折り曲げられ、折曲時のストレスがパツケージ
５に加わらないように配慮されている。また、保
護溝７の下端に突出したリード６の先端は外方に
向かつて水平に延び、プリント基板等への取り付
け用の接続部８を形作つている。しかし、この接
続部８の先端もパツケージ５の側縁よりも外方に
は突出しないようになつている。 2 and 3 are diagrams showing a semiconductor device according to an embodiment of the present invention, in which FIG. 2 is a perspective view showing the external appearance, and FIG. 3 is a partially cutaway front view. As shown in these figures, this semiconductor device 4
A package 5 made of resin formed by transfer molding, and leads 6 made of a plurality of metals arranged on both sides of this package 5.
It is made up of. A protective groove 7 is provided in the lower half of the package 5 extending downward from the base of the lead 6. This protective groove 7 has a width sufficient to accommodate the lead 6, and a depth sufficient to allow the in-line type lead 6 to sink therein. Also,
The lead 6 is bent downward at a distance a from the bottom of the protective groove so that no stress is applied to the package 5 when the lead 6 is bent. Further, the tips of the leads 6 protruding from the lower end of the protective groove 7 extend outward and horizontally to form a connecting portion 8 for attachment to a printed circuit board or the like. However, the tip of this connecting portion 8 is also designed not to protrude outward beyond the side edge of the package cage 5.
このような半導体装置にあつては、リード先端
はパツケージ５の外周よりも外側に突出しないた
め、従来に比較して外形寸法が小さくなり、実装
面積が小さくなる。 In such a semiconductor device, the lead tips do not protrude beyond the outer periphery of the package 5, so the external dimensions and mounting area are smaller than in the prior art.
また、この半導体装置では、各リード６の大半
は保護溝７内に入つて保護されているため、外部
からの接触の機会が少なくなるとともに、リード
先端部に外力が加わつても、突出長さが短かく、
かつ保護溝７でガイドされるため、曲がり難い。
したがつて、リード６先端の寸法位置関係が保証
できるため、実装歩留も向上する。 In addition, in this semiconductor device, most of each lead 6 is protected by entering into the protective groove 7, so there is less chance of contact from the outside, and even if an external force is applied to the lead tip, the protrusion length will be reduced. is short,
Moreover, since it is guided by the protective groove 7, it is difficult to bend.
Therefore, since the dimensional positional relationship of the tips of the leads 6 can be guaranteed, the mounting yield is also improved.
なお、本発明は前記実施例に限定されない。す
なわち、リードの先端は下方に真直に延在する形
状でもよい。また、実施例ではデユアルインライ
ン形について示したが、リードがパツケージの４
面等から突出する構造でもよい。また、本発明は
他のレジンパツケージ、あるいはレジン以外のパ
ツケージにも適用できる。 Note that the present invention is not limited to the above embodiments. That is, the tip of the lead may be shaped to extend straight downward. In addition, although the dual inline type was shown in the example, the lead is
It may be a structure that protrudes from a surface or the like. Further, the present invention can be applied to other resin packages or packages other than resin.
以上のように、本発明によれば、リードはパツ
ケージの下半分に設けた保護溝内に入りかつ先端
もパツケージ外周よりも外方に突出しない。この
ため、外径寸法が小さくなつて小型となるととも
に、実装面積が小さくなり、高集積度が可能とな
つた。 As described above, according to the present invention, the leads fit into the protective groove provided in the lower half of the package, and the tips do not protrude outward beyond the outer periphery of the package. For this reason, the outer diameter dimension has become smaller, making it more compact, and the mounting area has become smaller, making it possible to achieve a high degree of integration.
また、本発明の半導体装置は、リードが保護溝
によつて保護されているため、リード曲り不良も
発生しにくくなり、リード各部の寸法精度の高い
半導体装置となり、実装効率が向上する。 Further, in the semiconductor device of the present invention, since the leads are protected by the protective grooves, lead bending defects are less likely to occur, resulting in a semiconductor device with high dimensional accuracy of each part of the leads, and mounting efficiency is improved.
第１図ａ，ｂは従来の半導体装置を示す斜視
図、第２図は本発明の一実施例による半導体装置
の斜視図、第３図は同じく一部を切り欠いた正面
図である。
４……半導体装置、５……パツケージ、６……
リード、７……保護溝。
1A and 1B are perspective views showing a conventional semiconductor device, FIG. 2 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a partially cutaway front view. 4...Semiconductor device, 5...Package, 6...
Lead, 7...protective groove.
Claims (1)
で一方向に折れ曲がつてなるインライン形の半導
体装置において、前記リードはその先端を除く部
分がパツケージに設けた保護溝内に入つた構造と
なつていることを特徴とする半導体装置。1. In an in-line type semiconductor device in which a lead protruding from the peripheral surface of a package is bent in one direction in the middle, the lead has a structure in which the portion of the lead except for its tip is placed in a protective groove provided in the package. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4031981A JPS57155758A (en) | 1981-03-23 | 1981-03-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4031981A JPS57155758A (en) | 1981-03-23 | 1981-03-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155758A JPS57155758A (en) | 1982-09-25 |
| JPS6251501B2 true JPS6251501B2 (en) | 1987-10-30 |
Family
ID=12577286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4031981A Granted JPS57155758A (en) | 1981-03-23 | 1981-03-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155758A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58169948A (en) * | 1982-03-30 | 1983-10-06 | Fujitsu Ltd | Resin-sealed type semiconductor device |
| JPS58184746A (en) * | 1982-04-22 | 1983-10-28 | Toshiba Corp | Package |
| JPS5980955A (en) * | 1982-10-29 | 1984-05-10 | Matsushita Electronics Corp | Electronic parts device |
| JPS59104544U (en) * | 1982-12-29 | 1984-07-13 | 松下電器産業株式会社 | integrated circuit device |
| JPS59189662A (en) * | 1983-04-13 | 1984-10-27 | Fujitsu Ltd | Resin-sealed type semiconductor device |
| JPS6088561U (en) * | 1983-11-22 | 1985-06-18 | 日本電気株式会社 | semiconductor equipment |
| JPS6116556A (en) * | 1984-07-03 | 1986-01-24 | Matsushita Electronics Corp | Resin sealed type semiconductor device |
| JPS6132490A (en) * | 1984-07-24 | 1986-02-15 | 富士通株式会社 | Mounting structure of flat lead package type electronic part |
| JPS6398640U (en) * | 1986-12-16 | 1988-06-25 |
-
1981
- 1981-03-23 JP JP4031981A patent/JPS57155758A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155758A (en) | 1982-09-25 |
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