JPH03190270A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03190270A JPH03190270A JP33045889A JP33045889A JPH03190270A JP H03190270 A JPH03190270 A JP H03190270A JP 33045889 A JP33045889 A JP 33045889A JP 33045889 A JP33045889 A JP 33045889A JP H03190270 A JPH03190270 A JP H03190270A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- semiconductor device
- package
- mechanical strength
- reinforcing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 19
- 238000005452 bending Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
を目的とし、
パンケージの側面から該側面に垂直に取り出された端子
を有する半導体装置において、端子を、長手方向の中間
部に部分的に幅が拡大された補強部と、補強部でパッケ
ージの表面と平行方向に屈曲して形成される先端部とを
設けて構成する。[Detailed Description of the Invention] [Summary] In a semiconductor device having a terminal taken out perpendicularly to the side surface of a pan cage, the width of the terminal is partially enlarged in the middle part in the longitudinal direction. The package is configured by providing a reinforcing portion and a tip portion formed by bending the reinforcing portion in a direction parallel to the surface of the package.
に機械的強度が大きく機械的な外力により変形し難い端
子を有する半導体装置に関する。The present invention relates to a semiconductor device having a terminal having high mechanical strength and not easily deformed by external mechanical force.
半導体装置の高集積・大規模化に伴って、半導体装置の
端子数も著しく多くなっている。2. Description of the Related Art As semiconductor devices become more highly integrated and larger in scale, the number of terminals in semiconductor devices has also increased significantly.
一方、斯かる半導体装置の端子の太さは、ますます細く
なって、機械的強度は必然的に弱いものとなっている。On the other hand, the thickness of the terminals of such semiconductor devices has become thinner and thinner, and the mechanical strength has inevitably become weaker.
従って、高集積・大規模化された半導体装置においては
、大きな機械的強度を有する端子が強く要請されている
。Therefore, in highly integrated and large-scale semiconductor devices, there is a strong demand for terminals with high mechanical strength.
するための工程順図で、同図（ａ）はタイバー切断前の
部分平面図、同図（ｂ）はタイバー切断後の平面図、同
図（ｃ）は端子成型完了後の正面図、同図（ｄ）は部分
拡大斜視図である。Figure (a) is a partial plan view before the tie bar is cut, figure (b) is a plan view after the tie bar is cut, figure (c) is a front view after terminal molding is completed, and figure (c) is a partial plan view before the tie bar is cut. Figure (d) is a partially enlarged perspective view.
すなわち、同図（ａ）は、リードフレーム２０に搭載さ
れ、該リードフレーム２０の端子２１等と電気的に接続
した半導体チップ（図示せず）が、封止用の樹脂、例え
ばエポキシ樹脂を用いたモールドによって形成したパン
ケージ２４によりパンケージングされた状態を示すもの
である。That is, in FIG. 2A, a semiconductor chip (not shown) mounted on a lead frame 20 and electrically connected to terminals 21, etc. of the lead frame 20 is sealed using a sealing resin such as epoxy resin. This figure shows the state of being pancaged by a pancage 24 formed by a mold.
この後、リードフレーム２０を、切断線Ａ及び切断線Ｂ
に沿って切断工具等により切断する。After that, the lead frame 20 is cut along cutting line A and cutting line B.
Cut along with a cutting tool etc.
斯くすることにより、端子２１とタイバー２２間、及び
端子２工とクレドール２３間は切断・分離されることと
なる（同図（ｂ）参照）。By doing so, the terminal 21 and the tie bar 22 and the terminal 2 and the cradle 23 are cut and separated (see FIG. 2(b)).
次いで、端子の曲げ工具等により折り曲げ線Ｃする（同
図（ｃ）参照）。Next, the terminal is bent along a line C using a terminal bending tool or the like (see FIG. 3(c)).
なお、端子２１とタイバー２２間を切断する際に、端子
２１の側面部が過って切断されることを防止するために
、端子２１の側端から僅か外側に切断線Ｂを設定してい
る。In addition, when cutting between the terminal 21 and the tie bar 22, in order to prevent the side surface of the terminal 21 from being accidentally cut, the cutting line B is set slightly outward from the side edge of the terminal 21. .
従って、端子２１は同図（ｂ）に示すように、通常その
中間部に幅広部２１ａを有することとなる。Therefore, the terminal 21 usually has a wide portion 21a in the middle thereof, as shown in FIG. 2(b).
また、幅広部２１ａは、端子２１を折り曲げ線Ｃ及び折
り曲げ線りに沿って折り曲げて成型した際にせ、パッケ
ージ２４の側面２４ａと平行となる部分に位置する（同
図（ｃ）及び同図（ｄ）参照）。Further, the wide portion 21a is located in a portion parallel to the side surface 24a of the package 24 when the terminal 21 is bent and molded along the bending line C and the bending line (FIG. 2(c) and FIG. d)).
高集積・大規模化された半導体装置は、一つの側面に４
０本を越えるような端子２１を有することも少なくない
。Highly integrated and large-scale semiconductor devices are equipped with four devices on one side.
It is not uncommon to have more than zero terminals 21.
このような端子２１は、通常、４２７０イ（鉄、ニッケ
ル合金）で形成され、その長さ方向に垂直な断面の形状
は、厚さ０．１５ｍｍ、横０．３０ｍｍ程度になってい
る。Such a terminal 21 is usually formed of 4270I (iron, nickel alloy), and its cross section perpendicular to its length direction is about 0.15 mm thick and 0.30 mm wide.
従って、斯かる端子は、機械的な外力により極めて簡単
に変形することにより端子２１の配列が乱れて、プリン
ト基板等への実装作業がスムーズに行えない問題があっ
た。Therefore, such terminals are extremely easily deformed by mechanical external force, causing the arrangement of the terminals 21 to be disordered, resulting in a problem that mounting work on a printed circuit board or the like cannot be carried out smoothly.
本発明は上記問題に鑑みてなされたものであって、その
目的は機械的強度が大きく機械的な外力により変形し難
い端子を有するフラットＪの半導体装置の提供にある。The present invention has been made in view of the above problems, and its object is to provide a flat J semiconductor device having terminals that have high mechanical strength and are difficult to deform due to external mechanical force.
前記目的は、第１図に示すようにパッケージ１４子１１
が、その長手方向の中間部に機械的強度の大きい補強部
１１ａと、補強部１１ａでパッケージ１４の表面１４ｂ
と平行方向に屈曲して、平坦面と接触できる先端部１１
ｂとを有することを特徴とする半導体装置によって達成
される。The purpose is to package the package 14 and the child 11 as shown in FIG.
However, there is a reinforcing part 11a with high mechanical strength in the middle part in the longitudinal direction, and the reinforcing part 11a strengthens the surface 14b of the package 14.
A tip portion 11 that can be bent in a direction parallel to the flat surface to make contact with a flat surface.
This is achieved by a semiconductor device characterized by having the following features.
本発明の半導体装置の端子１１は、その長手方向の中間
部に機械的な強度を向上させる補強部１１ａを有すると
°ともに、この補強部１１ａでパッケージ１４の表面１
４ｂと平行方向に屈曲して平坦面と接触できる先端部１
１ｂとを有している。The terminal 11 of the semiconductor device of the present invention has a reinforcing portion 11a in the longitudinally intermediate portion thereof to improve mechanical strength, and this reinforcing portion 11a extends over the surface of the package 14.
4b and a tip portion 1 that can be bent in a direction parallel to the flat surface and come into contact with a flat surface.
1b.
従って、この端子１１は、外力を受けても変形し難いた
めに、端子１１の配列状態が乱されることが減少する。Therefore, since the terminals 11 are not easily deformed even when subjected to external force, the arrangement state of the terminals 11 is less likely to be disturbed.
この結果、本発明の半導体装置は、プリント基板等への
実装作業が簡単となり、実装作業の能率が向上する。As a result, the semiconductor device of the present invention can be easily mounted on a printed circuit board, etc., and the efficiency of the mounting work is improved.
以下、本発明の半導体装置の一実施例を図面を参照しな
がら説明する。An embodiment of the semiconductor device of the present invention will be described below with reference to the drawings.
第１図は本発明の半導体装置の第１の実施例を説明する
ための工程順図で、同図（ａ）はタイバー切断前の部分
平面図、同図（ｂ）はタイバー切断後の平面図、同図（
ｃ）は端子成型完了後の正面図、同図（ｄ）は部分拡大
斜視図である。FIG. 1 is a process diagram for explaining the first embodiment of the semiconductor device of the present invention, in which (a) is a partial plan view before cutting the tie bars, and (b) is a plan view after cutting the tie bars. Figure, same figure (
(c) is a front view after the terminal molding is completed, and (d) is a partially enlarged perspective view.
尚、同じ部品・材料に対しては全図を通して同じ記号を
付与しである。Note that the same symbols are given to the same parts and materials throughout the drawings.
すなわち、本発明の半導体装置の一実施例は、第１図の
（ａ）〜（ｄ）図に示すように、リードフレーム１０の
タイバー１２の幅を広くするとともに、端子１１とタイ
バー１２とを切断する際にタイバー１２の一部を端子１
１に残して切断し、このタイバー１２の一部を端子１１
の補強部１１ａとするように構成したものである。In other words, in one embodiment of the semiconductor device of the present invention, as shown in FIGS. When cutting, attach a part of tie bar 12 to terminal 1.
1, and cut a part of this tie bar 12 to the terminal 11.
The reinforcing portion 11a is configured to have the following structure.
次に、本発明の半導体装置の一実施例を工程順に従って
説明する。Next, an embodiment of the semiconductor device of the present invention will be described in accordance with the order of steps.
同図（ａ）は、リードフレーム１０に搭載され、該リー
ドフレーム１０の端子１１等と電気的に接続した半導体
チップ（図示せず）が、封止用の樹脂、例えばエポキシ
樹脂のモールドによって形成したパッケージ１４により
パッケージングされた状態を示すものである。In the figure (a), a semiconductor chip (not shown) mounted on a lead frame 10 and electrically connected to terminals 11, etc. of the lead frame 10 is formed by molding with a sealing resin, for example, an epoxy resin. This figure shows the state in which the package 14 is packaged.
この後、リードフレーム１０を切断線Ａ及び切断線Ｂに
沿って切断工具等により切断することにより、端子１１
とタイバー１２間、及び端子１１とクレドール１３間は
分離される。Thereafter, the terminal 11 is cut by cutting the lead frame 10 along the cutting line A and the cutting line B with a cutting tool or the like.
and the tie bar 12, and between the terminal 11 and the cradle 13 are separated.
この切断線Ｂは、端子１１の側面から外側位置、すなわ
ちタイバー１２の一部が残る位置に設定しであるから、
端子１１とタイバー１２とを切断・分離した際、端子１
１の中間部に補強部１１ａが形成されることとなる。This cutting line B is set at a position outward from the side surface of the terminal 11, that is, at a position where a portion of the tie bar 12 remains.
When terminal 11 and tie bar 12 are cut and separated, terminal 1
A reinforcing portion 11a will be formed in the middle portion of 1.
具体的な寸法としては、例えば、端子１１の幅を０．４
５ｍｍとした場合、隣接する端子１１との間隔は１．２
７ｍｍであり、またタイバー１２が残される補強部１１
ａの全幅は、１．０５ｍｍであるものが想定される。As a specific dimension, for example, the width of the terminal 11 is 0.4
If the distance is 5 mm, the distance between adjacent terminals 11 is 1.2
7 mm, and the reinforcing part 11 where the tie bar 12 is left
The total width of a is assumed to be 1.05 mm.
次いで、端子の曲げ工具等により折り曲げ線Ｃ及び補強
部１１ａの略中央部に設定した折り曲げ線りに沿って、
それぞれの部分で略直角に折り曲げ置の一実施例が完成
する（同図（ｃ）参照）。Next, along the bending line C and the bending line set approximately at the center of the reinforcing portion 11a using a terminal bending tool or the like,
An embodiment in which each portion is bent approximately at right angles is completed (see FIG. 10(c)).
斯くして、本発明の半導体装置の端子は、機械的強度が
増し機械的外力を受けても変形し難く、且つ先端部１１
ｂの幅が広くなっているために、プリント基板等のはん
だ付は用のパターンから位置ずれする危険が少な（なっ
て、プリント基板等への実装が簡単となる利点をも有す
ることとなる。In this way, the terminal of the semiconductor device of the present invention has increased mechanical strength and is difficult to deform even when subjected to external mechanical force, and the tip portion 11
Since the width of b is wide, there is less risk of misalignment from the intended pattern when soldering a printed circuit board, etc. (this also has the advantage of simplifying mounting on a printed circuit board, etc.).
また、第２図の本発明の半導体装置の第２の実施例の平
面図で示す如く、補強部を互い違い（１１ａ。Further, as shown in the plan view of the second embodiment of the semiconductor device of the present invention in FIG. 2, the reinforcing portions are staggered (11a).
１１ａ’）に設ければ端子１１の実装密度も向上する。11a'), the packaging density of the terminals 11 can also be improved.
この場合、補強部１１ａを有する端子１１は、Ｂの部分
を山折り、Ａの部分を谷折りして整形し、補強部１１ａ
゛を有する端子１１は、Ｃの部分を山折り、Ｂの部分を
谷折りして整形される。In this case, the terminal 11 having the reinforcing part 11a is shaped by mountain-folding the part B and valley-folding the part A.
The terminal 11 having a shape is formed by mountain-folding the C portion and valley-folding the B portion.
以上の説明から明らかなように本発明によれば、機械的
強度が大きく、また先端部の幅が広くなった端子を有す
る半導体装置の提供が可能となる。As is clear from the above description, according to the present invention, it is possible to provide a semiconductor device having a terminal having high mechanical strength and a wide tip portion.
従って、本発明の半導体装置は、端子の変形が少なく、
しかも端子の先端部の幅が広いために、プリント基板等
への実装作業が簡単となり、実装作業の能率を向上させ
ることができる。Therefore, the semiconductor device of the present invention has less deformation of the terminals, and
Moreover, since the width of the tip of the terminal is wide, the mounting work on a printed circuit board or the like becomes easy, and the efficiency of the mounting work can be improved.
第１図は本発明の半導体装置の第１の実施例を説明する
ための工程順図、
第２図は本発明の半導体装置の第２の実施例のｌ”ｉｌ
［ｆｆｌ゛ 仏
画３図は従来のフラットｆの半導体装置を説明するため
の工程順図である。
図において、
１０はリードフレーム、
１１は端子。
１１ａは補強部、
１１ｂは先端部、
１２はタイバー
１３はクレドール、
１４はパッケージ、
１４ａはパッケージの側面、
１４ｂはパッケージの表面をそれぞれ示す。
（Ｑ） フィバ°−ｔア＃ｒｔ５ｒ 射Ｐｆｉｒｙ Ｉ
！１【ｄ＋射抹大ｔ＋！ｉｌ力
ｘｇｆ４． ＃４＃に影４ｔｅ＋ｆＱＩｒｆＰＪｅｔｔ
ＢＡｔｔｒ：ｈｎＩｉｔ’１ｌｒＸＪイトぞ４８月、牛
４Ｉばの竿２め定ＡシタＣ乎面図第２図FIG. 1 is a process sequence diagram for explaining the first embodiment of the semiconductor device of the present invention, and FIG. 2 is a diagram of the second embodiment of the semiconductor device of the present invention.
[ffl゛ Figure 3 is a process sequence diagram for explaining a conventional flat-f semiconductor device. In the figure, 10 is a lead frame, and 11 is a terminal. Reference numeral 11a indicates a reinforcing portion, 11b indicates a tip, 12 indicates a tie bar 13, a cradle, 14 indicates a package, 14a indicates a side surface of the package, and 14b indicates a surface of the package. (Q) Fiber°-tA #rt5r Fire Pfiry I
! 1 [d+shooting large t+! il force xgf4. Shadow 4te+fQIrfPJett on #4#
BAttr: hnIit'1lrXJ itozo 48 month, cow 4I bar 2nd set A sita C surface diagram 2nd figure
Claims (1)
に取り出された端子（１１）を有する半導体装置におい
て、 端子（１１）は、その長手方向の中間部に部分的に幅が
拡大された補強部（１１ａ）と、 補強部（１１ａ）でパッケージ（１４）の表面（１４ｂ
）と平行方向に屈曲して形成される先端部（１１ｂ）と
を有することを特徴とする半導体装置。[Claims] In a semiconductor device having a terminal (11) taken out from a side surface (14a) of a package (14) perpendicularly to the side surface, the terminal (11) is partially disposed at an intermediate portion in the longitudinal direction. The reinforcing portion (11a) has an expanded width, and the surface (14b) of the package (14) is formed by the reinforcing portion (11a).
) and a tip (11b) bent in a parallel direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33045889A JPH03190270A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33045889A JPH03190270A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03190270A true JPH03190270A (en) | 1991-08-20 |
Family
ID=18232846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33045889A Pending JPH03190270A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03190270A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06260582A (en) * | 1993-03-09 | 1994-09-16 | Hitachi Ltd | Semiconductor device |
| US5736784A (en) * | 1996-10-31 | 1998-04-07 | Hewlett-Packard Co. | Variable-width lead interconnection structure and method |
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
-
1989
- 1989-12-20 JP JP33045889A patent/JPH03190270A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06260582A (en) * | 1993-03-09 | 1994-09-16 | Hitachi Ltd | Semiconductor device |
| US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
| US5736784A (en) * | 1996-10-31 | 1998-04-07 | Hewlett-Packard Co. | Variable-width lead interconnection structure and method |
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