JPS6249459A - Memory bank switching system in microprocessor - Google Patents

Abstract

PURPOSE:To obtain a memory bank switching mechanism using simple circuit configuration by making specific addresses different from each other correspond to plural memory banks and accessing a memory bank corresponding to the specific address automatically when a CPU accessed. CONSTITUTION:Specific addresses different from each other are allocated to correspond to plural memory banks 1-3 just as their naming. When a CPU accessed a specific address, a memory bank corresponding to the specific address is accessed automatically by a memory bank switching mechanism X. For instance, when the CPU accessed 0000 address, only the memory bank 1 is selected, and when the CPU accessed 0001 address, only the memory bank 2 is selected, and when the CPU accessed 0002, only the bank 3 is selected and kept in usable state respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory bank switching method in a microprocessor, which is one means for expanding the memory capacity that can be used in the microprocessor.

(Prior Art) The memory capacity that can be used in a microprocessor is basically determined by the size of the address bus in the microprocessor. For example, if the address bus is 1
In the case of 6, the memory capacity is approximately 64 bytes (2”-
1=65.535), and the address bus is 20
In the case of a book, the memory capacity is approximately I Mha() (2” −
1=1,048,575) T: Yes.

Therefore, in order to expand the memory capacity despite the basic limitation due to the size of the address bus, the above-mentioned bank switching method has been considered.

This bank switching method involves arranging multiple memory banks that have a common address group within an accessible range on a common address bus from the CPU, and also This allows a desired memory bank to be selected and accessed from among the banks, and conventionally, the configuration was as shown in FIG. 2.

That is, on the common address bus A and the common memory bus B from the CPU, a group of mutually common addresses (for example, addresses φφφφ to 7 FF F F
A plurality of (three in this example) memory banks ■, ■, ■ are arranged, and the first decoder i connected to the input/output port of the CPU and its first
A memory bank consisting of a second decoder 11 connected to the decoder i and the memory bus B, and a latch circuit 111 interposed between the second decoder +1 and each of the plurality of memory banks ■, ■, ■. A switching mechanism is provided. The reason why such a memory bank switching mechanism is necessary is that when the CPU accesses address 1φφ, for example, the memory banks 1 and 2 are switched.

Since the same 1φφ address exists in each of ■, unless you specify which memory bank the 1φφ address is,
This is because troubles such as data being written to the wrong location or data being read may conflict with each other may occur.

The memory bank switching operation by the memory bank switching mechanism is performed as follows.

First, when the first decoder i receives a memory bank switching command signal from the input/output board of the CPU, the first
Decoder i selects a port for switching memory banks and issues a signal to the second decoder ii to activate it. In this state, when a memory bank designation signal (for example, ■) is input from the CPU via the data bus B, the second decoder ii transmits a memory bank selection signal corresponding to the memory bank designation signal to the latch circuit 111. emit to. Then, the launch circuit iil issues a signal to enable only the memory bank (2) corresponding to the memory bank selection signal, and thereafter maintains this state until a new memory bank selection signal is applied. Therefore, if an address is accessed from the CPU via the address bus A during that time, a read/write operation is performed only for the selected memory bank (2).

However, in the memory bank switching method in the conventionally configured microprocessor described above, when configuring the memory bank switching mechanism, the CPU's human output board must be used and two decoders must be used. Therefore, there is a drawback that the circuit configuration becomes complicated.

(Object of the Invention) The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a microprocessor capable of realizing memory bank switching for expanding memory capacity with a relatively simple circuit. An object of the present invention is to provide a method for switching memory banks in a computer.

(Structure of the Invention) In order to achieve the above-mentioned object, the present invention provides a method for selecting a desired memory bank from among a plurality of memory banks arranged on a common address bus from the CPU and set with a mutually common address group. In a memory bank switching method in a microprocessor configured to be able to select and access a memory bank, a specific address (address) different from each other is assigned to each of the plurality of memory banks, and the CPU selects and accesses the memory bank. When a specific address (house number) is accessed, that specific address (house number)
The feature is that the memory bank corresponding to the memory bank is configured to be accessed automatically.

(Embodiment) An embodiment of a memory bank switching method in a microprocessor according to the present invention will be described below with reference to FIG.

That is, on a common address bus A and a common memory bus B from the CPU, a group of mutually common addresses within an accessible range (for example, addresses φφφφ to 7FFFH)
A plurality of (three in this example) memory banks ■, ■, ■ are set, and these multiple memory banks ■, ■ are set.

(2) A memory bank switching mechanism X is provided for arbitrarily selecting and accessing a desired memory bank from among the memory banks.

The memory bank switching mechanism X includes one address decoder I connected to the address bus A, its address decoder ■, and the plurality of memory banks ■, ■
, ■ a latch circuit connected interveningly between each, and the latch circuit H has an output command signal line C from the CPU.
is entered. In other words, the CPU uses the address bus A
At the same time as the bus access signal is issued, an output command signal is issued to the latch circuit (2) via the output command signal line C.

In addition, each of the plurality of memory banks ■, ■, ■,
As the naming suggests, specific addresses (addresses) that are different from each other are assigned to correspond to each other.For example, memory bank ■ is assigned address φφφφ, memory bank ■ is address φφφ1, and memory bank ■ is address φφφ2. The addresses are allocated as follows, and normal reading and writing are not performed to each specific address.

When the CPU accesses the specific address, the memory bank switching mechanism X automatically accesses the memory bank corresponding to the specific address.

For example, when the CPU accesses the φφφφ address, only memory bank ■ is used; when CPtJ accesses the φφφ1 address, only memory bank ■ is used;
When address φ2 is accessed, only memory bank (2) is selected and kept in a usable state.

Therefore, for example, when reading or writing to address 1φφ of memory bank ■, the CPU first accesses address φφφ1, which is a specific address (address) corresponding to memory bank ■, and then accesses memory bank ■. The operation of selecting and holding it in a usable state and then accessing the address 1φφ is performed.

That is, if the CPLI accesses address φφφ1, which is one of the specific addresses, the memory access signal is input from the address bus A to the address decoder I in the memory bank switching mechanism X, and the output command Since the output command signal is input to the latch circuit ■ via the signal line C, the address decoder ■ issues a signal to the latch circuit ■ to select the memory bank ■ corresponding to the φφφ1 address, and the launch circuit ■ selects the memory bank ■ corresponding to the address φφφ1. The bank (■) selection signal is held and simultaneously output to the memory bank (■), making only that memory bank (■) available for use instantaneously. Then, the latch circuit (■) continues to hold the memory bank (■) selection signal until a new memory bank selection signal is applied, and in that state, the memory access signal from the CPU to address 1φφ, for example, When the output command signal from the CPU is output via the bus A and input to the launch circuit ■ via the output command signal line C, the latch circuit ■ outputs the memory bank (■) selection signal held by the latch circuit ■. Since only the memory bank (2) is outputted and instantaneously becomes usable again, the address 1φφ of the memory bank (2) is accessed and read/written to it via the memory bus B.

Note that if the latch circuit (2) is configured to always output the memory bank selection signal it holds, the output command signal line C can be omitted.

(Effects of the Invention) As is clear from the detailed description above, according to the method of switching memory banks in a microprocessor according to the present invention, memory banks arranged on a common address bus from the CPU and having a common address (address) ) groups are set with different specific addresses (addresses), and when the CPU accesses the specific addresses (addresses), the specific addresses (addresses) are ) is configured so that the memory bank corresponding to The excellent effect of being able to configure a memory bank switching mechanism with a simple circuit configuration has been achieved.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a memory bank switching method in a microprocessor according to the present invention. FIG. 2 is a block circuit diagram showing a memory bank switching method in a conventional microprocessor. A・・・・・・Address bus, B・・・・・・・・・
...Memory bus, C...Memory access signal line, X...Memory bank switching mechanism, ■...Address decoder, ■...・・・
・・・・・・Lunch circuit, ■, ■, ■・・・・・・・・・
・Memory bank.

Claims (1)

[Scope of Claims] A configuration in which a desired memory bank can be selected and accessed from among a plurality of memory banks that are arranged on a common address bus from the CPU and that have mutually set a common address group. This is a memory bank switching method in a microprocessor that has been developed, in which specific addresses (addresses) different from each other are assigned to each of the plurality of memory banks in correspondence with each other, and when the CPU accesses the specific addresses (addresses). 1. A memory bank switching method in a microprocessor, characterized in that the memory bank corresponding to a particular address is automatically accessed.