JPS6248863B2 - - Google Patents

Info

Publication number
JPS6248863B2
JPS6248863B2 JP57052878A JP5287882A JPS6248863B2 JP S6248863 B2 JPS6248863 B2 JP S6248863B2 JP 57052878 A JP57052878 A JP 57052878A JP 5287882 A JP5287882 A JP 5287882A JP S6248863 B2 JPS6248863 B2 JP S6248863B2
Authority
JP
Japan
Prior art keywords
data
register
latch
instruction
storage element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57052878A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58169643A (ja
Inventor
Yoshio Tokutake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57052878A priority Critical patent/JPS58169643A/ja
Publication of JPS58169643A publication Critical patent/JPS58169643A/ja
Publication of JPS6248863B2 publication Critical patent/JPS6248863B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP57052878A 1982-03-31 1982-03-31 情報処理装置診断回路 Granted JPS58169643A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052878A JPS58169643A (ja) 1982-03-31 1982-03-31 情報処理装置診断回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052878A JPS58169643A (ja) 1982-03-31 1982-03-31 情報処理装置診断回路

Publications (2)

Publication Number Publication Date
JPS58169643A JPS58169643A (ja) 1983-10-06
JPS6248863B2 true JPS6248863B2 (enrdf_load_stackoverflow) 1987-10-15

Family

ID=12927133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052878A Granted JPS58169643A (ja) 1982-03-31 1982-03-31 情報処理装置診断回路

Country Status (1)

Country Link
JP (1) JPS58169643A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4494899B2 (ja) 2004-07-29 2010-06-30 富士通株式会社 プロセッサデバッグ装置およびプロセッサデバッグ方法

Also Published As

Publication number Publication date
JPS58169643A (ja) 1983-10-06

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