JPS6248830A - Bit buffer circuit - Google Patents

Abstract

PURPOSE:To make the operation of a data transfer section coincident with the operation of a slip detection section by using a clock having a period T so as to fix the relation of the phase of asynchronous clocks Wck and Rck. CONSTITUTION:The write clock Wck and the read clock Rck and fed respectively to FFs 12, 13 and FFs 14, 15 to which a clock having a period T is applied and clocks Wck' and Rck' synchronously with the clock are obtained. They are fed to a data transfer section 10 and a slip detection section 11 to apply data transfer operation and slip detection operation. In such a case, the leading point of the clocks Wck' and Rck' is made coincident with the clock and since an output Tck (this is called a dead band) of the delay circuit enters the period T, the clocks Wck' and Rck' do not enter the dead band. Further, the FFs 13, 15 are inserted to remove it when the FFs 12, 14 convert data and a spike is caused.

Description

[Detailed Description of the Invention] (Summary) In a bit buffer circuit, data transfer and slip detection are performed using a write clock and a read clock synchronized with a clock having a predetermined period. The operation of the slip detector always matches the output of the slip detector.

[Industrial application field]

The present invention relates to improvements in bit buffer circuits used, for example, in subscriber terminals of data transmission equipment.

Data from a terminal device installed on the subscriber side is transmitted to, for example, a telephone office via an interface section and a subscriber line, but since the reference clock on the subscriber side is accompanied by jitter, it is difficult to match the reference clock on the telephone office side. is asynchronous.

Therefore, the data transfer section of the bit buffer circuit included in the interface section synchronizes the data from the subscriber side with the reference clock of the central office side and sends it to the central office side.

At this time, the slip detection section monitors whether or not data is missing or duplicated, but it is desired that the operation of the data transfer section and the output of the slip monitoring section always match.

[Conventional technology]

FIG. 3 shows a block diagram of a conventional example of a bit buffer circuit, and FIG. 4 shows a time chart of FIG. 3. Furthermore, the fourth
The symbols on the left side of the figure indicate the waveforms of the portions with the same symbols in FIG.

Therefore, the operation shown in FIG. 3 will be explained with reference to FIG.

In FIG. 3, a write clock (hereinafter referred to as clock Wc) extracted from data applied to the bit buffer circuit
k) and read clock (hereinafter referred to as clock Rc)
(abbreviated as k) is asynchronous (Fig. 3 Di+
(See Wck, Rck).

First, when data Di and clock Wck are applied to a flip-flop (hereinafter abbreviated as PF) (2), data D1 is output from terminal 1 of FF1 and applied to the terminal of FF4.

Also, since the terminal ports of FF2 and F'F3 are set to 1, the clock Wck is applied to FF2, and then the clock 1 is applied to FF3.
? When ck is added, "1" is output from the AND gate 6, and Tck is added to FF4 through the delay circuit 7, so the input data DI is output from terminal I of FF4 as data D2 and is sent to the terminal of FF5. added to. Since this data is read out using the clock Rck applied to the FF5, data Do synchronized with the clock Rck is sent out (DI, D2, D3, D in FIG. 3).

reference).

However, while the output Tck of the delay circuit 7 is FF2 and FF3, the operation of the slip detection section 11 is as follows.

When the bit buffer circuit is operating normally, when the clock Wck is applied to FF2, 1 is added to FF8, but before the next clock Wck is applied manually, FF2 is reset by Tck and l" of F8 is added. The terminal becomes O.

Therefore, even if the next clock Wck is input to this FF8, 0 is output, and no alarm indicating data loss or duplication is sent out.

However, as shown below the dot-dashed line in FIG.
Since the clock -ck is applied to the terminal CK before ck arrives, a 1 is output to send out a data loss alarm.

Conversely, if the clocks Rck overlap, the same data is
The data will be read out once, but at this time, the FF9 will send out a data duplication alarm.

[Problem that the invention seeks to solve]

In the above operation, clock Wck and clock Rck
As shown in FIG. 5, the clock W is asynchronous to
ck or clock Rck rises, FF2
, 3 are reset a destinations, so these clocks are ignored.

Therefore, there is a problem that an alarm may be sent out even though the data transfer section 10 is operating normally, or an alarm may not be sent out even though the data transfer section 10 is operating abnormally.

[Means for solving problems]

The above-mentioned problem can be solved by the present invention, in which the write clock and the read clock are synchronized with a clock having a predetermined period, and then the synchronized write and read clocks are applied to the data transfer section 10 and the slip detection section 11.・Solved by node buffer circuit.

[Effect]

The present invention provides a clock Wck and a clock R that are asynchronous to each other.
ck and clock with the following period T to fix the phase relationship between the two.

As a result, the rising edge of the clock -ck or the clock Rck does not enter the dead band width, so that the operation of the data transfer unit 1O and the output of the slip detection unit 11 can be completely interrupted.

(Pulse width of delay time element Tck of delay circuit 6)
Circumstances of Clock-ck or Clock Rc [Embodiments] The contents of the present invention will be explained in detail below with reference to illustrated embodiments.

It should be noted that the same reference numerals indicate the same objects throughout the figures, and the dotted line parts are the parts added in the present invention.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart of FIG. 1. Note that the symbols on the left side of FIG. 2 indicate the waveforms of the portions with the same symbols in FIG. 1, and only the rising portion of the clock is shown.

Therefore, the operation shown in FIG. 1 will be explained with reference to FIG.

As shown in FIG. 1, clock switch k and clock Rck are FFs 12, 13 and 14 to which a clock of period T is added.
．． 15, and clocks Wck' and Rck' synchronized with this clock are obtained (second diagram 0
7ri+ Wck +Rck+ Wck', Rck
'reference).

Now, in addition to the data transfer section 10 and the slip detection section 11, the data transfer operation and the slip detection operation are performed.

At this time, the clock Wck' and the clock Rck
The rising point of " coincides with the clock, but Tck is the period T
These clocks Wck' and Rc
k' never enters the insensitive region.

Furthermore, FF13. FF15 is FFI2. This was inserted to remove spikes that occur when the FF 14 converts data.

〔Effect of the invention〕

As explained in detail above, there is an advantage that the operation of the data transfer section and the operation of the slip detection section can always be made one-and-tone.

[Brief explanation of the drawing]

Figure 1 is a professional diagram of an embodiment of the present invention, Figure 2 is a diagram of the first embodiment of the present invention.
3 is a block diagram of a conventional example, FIG. 4 is a time chart of FIG. 3, and FIG. 5 is an explanatory diagram of a dead area. In the figure, 1-5, 8, 9.12-15 are FF. 6 is an AND gate, 71:j is a delay circuit, 10 is a data transfer section, and 11 is a slip detection section. 70,. 7 f f ↑ ↑ 11
InrA%2 Figure

Claims (1)

[Claims] A data transfer unit (10) that converts data synchronized with a write clock into data synchronized with a read clock and transfers the data.
When data is transferred by operating the slip detection unit (11) that detects missing or duplicated data, the write clock and read clock are synchronized with a clock having a predetermined period, and then the synchronization is performed. A bit buffer circuit characterized in that the write and read clocks applied to the data transfer section and the slip detection section are applied to the data transfer section and the slip detection section.