TW560141B - Integrated services digital network private branch exchange with automatically selecting synchronous clock source - Google Patents

Abstract

The present invention is an integrated services digital network private branch exchange with automatically selecting synchronous clock source. The integrated services digital network private branch exchange includes several trunk chips, several subscriber chips, and several priority selection circuits; wherein, the trunk chips are connected to the network terminal through the trunk interfaces, and connected to the central office through the network terminal for receiving the frame synchronization clock output signal and the data clock output signal; the subscriber chips are connected to the terminal equipments through the subscriber interface for receiving the frame synchronization clock output signal and the data clock output signal; and, the priority selection circuits are connected to the trunk chips, and connected with each other in a daisy-chain circuit for transmitting the frame synchronization clock output signal and the data clock output signal.

Description

560141 Λ7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 8 4 7 twf-doc / 0 0 9 V. Description of the invention (/) The present invention relates to an integrated service that selects a synchronous clock source and is dedicated to a small-scale digital network. Switch and method and control method of digital phase-locked loop, and more particularly, it relates to an integrated service digital network dedicated small switch and method for automatically selecting synchronous clock source, and control method of digital phase-locked loop. The conventional integrated services digital network private branch exchange (ISDN PBX) is shown in Figure 1. This ISDN PBX (12) includes N (N is a positive integer) trunks (LT- T) Wafer 16, L client-side (LT-S) wafers 18. Among them, the N LT_T chips 16 are connected to a network terminal 1 (referred to as NT1) through a trunk (tnmk, hereinafter referred to as T) interface, and then connected to a central office (referred to as C0) through NT1. The L LT-S chips 18 are connected to terminal equipment (TE) via a subscriber (S) interface. Because in ISDN PBX (12), it is necessary to synchronize the clock source with the central office. Therefore, how to quickly and automatically select the clock source synchronized with the central office is an important issue. When the ISDN PBX (12) is not used by any outside line, a stable free running clock must be provided by the ISDN PBX itself for use by the ISDN PBX. When an outside line is called for use, one of the n LT-T chips 16 ^ the first layer of the LT-T chip will be enabled and a ^ clock synchronization from the clock recovery circuit will be generated at the office. The clock source is called clock pulse (CP) and active signal (ACTL). Use CP as the reference clock of ISDN PBX. In the first figure, a non-terrninal 8-channel generic circuit interface (GCI) is used to converge 3 I paper standards (CNS) A4 specifications ⑵ G X 297 meals) " '( (Please read the notes on the back before filling out this page)

560141 Λ7 B7 7847twf.doc / 009 V. Description of the invention (>) (Please read the notes on the back before filling in this page) The bus is used as the system's bus. The data clock (data clock, DCL for short) The operating frequency is 4.096 million hertz (MHZ), and the frame synchronization clock (FSC) signal is 8 kilohertz (kHZ). A conventional method for selecting a synchronous clock source is to phase-lock the CP through a digital phase locked loop (DPLL) to generate DCL for use by the ISDN PBX. In the first! The part numbered 10 in the figure is a digital phase locked loop (DPLL) and fixed logic that need to be added. For the conventional method of selecting a synchronous clock source, if multiple external lines are called or used together, the ISDN PBX must first determine which LT of the N LT-T chips 16 through software and then through the microprocessor 14 The first layer of the -T chip is being enabled, and then the clock of the LT-T chip in the enabled state is arbitrarily selected as the reference clock of the local (ISDN) PBX. Because the clock source synchronized with the central office must be selected by software, real-time control cannot be performed, and system resources are wasted. Therefore, from the above, the known technology has the following disadvantages: 1. The software does control, so it cannot do real-time control, so it is difficult to ensure the system performance of ISDN PBX. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. As all outside lines may be connected or hung up at any time, in order to obtain a reference to the outside line being called or connected, the software needs to be busy polling (polling) and alignment, thus reducing system performance. 3. Increase the complexity of software programs. 4. Additional DPLL and fixed logic circuits are required to achieve the function of a synchronous clock source. 4 This paper size is applicable ® 0 standards (CNSM.1 grid (21〇χ 297 mm) 560141 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 8 4 7 twf .doc / 0 0 9 V. Description of the invention ($) 5. Cannot automatically select the appropriate clock source for synchronization with the central office. 6. Because this ISDN PBX cannot automatically select the clock source for synchronization, the external DPLL must be powered on to increase power In view of this, the present invention proposes a method for automatically selecting an ISDN PBX of a synchronous clock source and a control method of a digital phase-locked loop. Because this ISDN PBX integrates a DPLL circuit in a chip, it can reduce the occupation of a printed circuit board Space and the number of components on the printed circuit board. Moreover, the ISDN PBX not only automatically selects the synchronization clock source through the priority selection circuit, but also enables the software to determine the reference synchronization time without the need for constant polling and comparison. The pulse source can also automatically turn off the power of the DPLL that is not selected as the pulse source for reference synchronization to achieve the purpose of saving power consumption. In order to achieve the above purpose, the present invention This paper proposes an ISDN PBX that automatically selects the synchronous clock source. The ISDN PBX includes several LT-T chips, several LT-S chips, and several priority selection circuits. The main line chip is connected to the network terminal through the main line interface ( NT1), and then connected to the central office via the network terminal to receive the frame synchronous clock output signal and data clock output signal. The client chip is connected to the terminal device through the user interface to receive the frame synchronous clock output The signal and the data clock output signal. The priority selection circuit is connected to the mains chip and is connected to each other in a daisy-ring circuit to send the frame synchronous clock output signal and the data clock output signal. In a preferred embodiment, each priority selection circuit 5 I paper size is applicable to the Chinese National Standard (CNS) A4 specification (: 〇〇χ297 公 餐) a (Please read the precautions on the back before filling this page)

560141 Λ7 137 7847twf · doc / 009 V. The description of the invention (middle) includes a DPLL, which is placed in the chip of the ISDN PBX that automatically selects the synchronization clock source. DPLL is used to lock the first clock signal and synchronize the third clock signal with the central office to generate the fourth clock signal. It is used as the data clock output (DCLO) signal of the local ISDN PBX. Clock, and the fourth clock signal passes the second frequency divider in the priority selection circuit to generate a fifth clock signal, which is used as the frame synchronization clock output (FSCO) signal of the local ISDN PBX. The clock. The invention also proposes a method for automatically selecting a synchronous clock source, which is suitable for an ISDN PBX having several LT-T chips and several LT-S chips. In this method, a plurality of priority selection circuits are first provided. Later, when an outside line is called, these priority selection circuits will automatically select the priority selection circuit and the LT-T chip with the highest priority in the called outside line, and the enable signal (En) of this LT-T chip will be Enable, and provide the synchronization clock source synchronized with the central office. In a preferred embodiment of the present invention, the synchronous clock source is generated by a clock recovery circuit. The other priority selection circuits that are not selected as the synchronization clock source and the other layer 1 of the LT-T chip are disabled. In addition, if there is no outside call, these priority selection circuits will enable the enable signal (Eη) of the LT-T chip of the priority selection circuit with the lowest priority and provide a stable arbitrary execution clock. The invention also proposes a DPLL control method for automatically selecting a synchronous clock source, which is suitable for an ISDN PBX with a plurality of LT-T chips, a plurality of LT-S chips, and a plurality of priority selection circuits. In this method, the first 6 paper sizes are applicable to the Chinese National Standard (CNS) A '丨 size (21〇χ 297 cm) (Please read the precautions on the back before filling this page) Install i! S Order-- ---- Line 1 Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, India 560141 7847twf.doc / 009 Λ7 B7 Print of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs of the People ’s Republic of China. 5. Description of Invention (6) Provide a number of digital phase-locked circuits Placed in the priority selection circuit. Then, when an outside call is made, these priority selection circuits will automatically select the highest priority selection circuit and the LT_T chip, and enable the enable signal (En) of this LT-T chip to provide synchronization at the central office. Clock signal. After that, the digital phase-locked loop in the priority selection circuit is used to lock the synchronous clock signal synchronized with the local terminal. In another preferred embodiment of the present invention, only the DPLL placed in this highest priority selection circuit is enabled. All other DPLLs that are not selected as the synchronization clock source are disabled. In addition, if there is no outside call, only the DPLL in the priority selection circuit with the lowest priority will be enabled, and the other DPLLs will be disabled. In summary, the ISDN PBX and method for automatically selecting a synchronous clock source and the method for controlling the DPLL of the present invention can automatically select the synchronous clock source in real time when there is no outside call, so it can solve the problem of continuous software rotation. Query and comparison, resulting in reduced system performance. Furthermore, integrating the DPLL into an ISDN PBX chip that automatically selects the synchronization clock source can reduce the space occupied by the printed circuit board and the number of components on the printed circuit board. In addition, because only the power of the DPLL selected as the reference clock source is turned on, the power of the DPLL not selected as the reference clock source is turned off to achieve the purpose of saving power consumption. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments and the accompanying drawings to make a detailed description as follows: Schematic description of the paper Applicable to Chinese National Standard (CNS) / \ '4 specifications (210x297 meals) (Please read the precautions on the back before filling out this page)! · Packing -------- Order -------- -Line · 560141 7847twf.doc / 009 Λ7 B7 V. Description of the Invention (k) Figure 1 shows the circuit block diagram of the conventional ISDN PBX; Figure 2 shows the automatic selection of the synchronous clock according to the present invention A circuit block diagram of a preferred embodiment of the ISDN PBX source of the source; FIG. 3 shows a circuit block diagram of a priority selection circuit of a preferred embodiment of the ISDN PBX that automatically selects a synchronous clock source according to the present invention And FIG. 4 shows a detailed circuit diagram of a priority selection circuit of a preferred embodiment of an ISDN PBX that automatically selects a synchronous clock source according to the present invention. Significant component number = 10: Digital Phase Locked Loop (DPLL) and fixed logic

12: Conventional ISDN PBX 14: Microprocessor 16: N LT-T chips 18: L LT-S chips

20: ISDN PBX 200, 202, 204 of the present invention: LT-T chip and priority selection circuit 206, 208, 210: LT-S chip 30, 32, 34, 36: priority selection circuit 402, 404, 408: And gate 406: OR gate 410 · Switch 412: Digital phase-locked loop (DPLL) 414: Clock recovery circuit 8 (Please read the precautions on the back before filling this page)-丨 -------- Order --------- line. The paper printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is compliant with Chinese National Standard (CNS) A · 丨 (210 X 297 Gong) 560141 7847twf.doc / 009 Λ7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () 416: divide by 64 divider 418: divide by 512 divider 420, 422 · · gate 424, 426: preferred embodiment of the buffer: Please refer to FIG. 2, which shows a circuit block diagram of a preferred embodiment of an ISDN PBX that automatically selects a synchronous clock source according to the present invention. The ISDN PBX (20) includes the first LT_T chip and priority. Selection circuit 200, second LT-T chip and priority selection circuit 202 to N (N is a positive integer) LT-T chip and priority selection circuit 204; and An LT-S wafer 206, the second LT-S wafer 208 through L (L is a positive integer number) LT-S wafer 210. FIG. 3 shows a circuit block diagram of a priority selection circuit of a preferred embodiment of an ISDN PBX that automatically selects a synchronous clock source according to the present invention, including a chip 1 of a first priority selection circuit 30 (chip (l)), chip (2) of the second priority selection circuit 32, chip (M) of the priority selection circuit 34 to the Mth (M is a positive integer and 1 < M < N), and the Chip (N) of N priority selection circuits 36. Fig. 4 is a detailed circuit diagram of a priority selection circuit of a preferred embodiment of the ISDN PBX architecture for automatically selecting a synchronous clock source according to the present invention. The priority selection circuit includes a reverse gate 420 having an input terminal and an output terminal of an enable signal (active level 1 (ACTL1) for short) connected to a first layer of an LT-T chip. There is a reverse gate 422 connected to an input end and an output end of a priority level (PL) signal. With external clock indication signal (external clock indication 9) This paper size is applicable to China's 0 standards (CNS) A'l regulations 丨 each (21〇χ 297cm) (Please read the precautions on the back before filling this page )

560141 Λ7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7847twf.doc / 009 V. Description of the invention (8) The first input terminal of the signal (XCI), the input terminal connected to the ACTL1 signal and the back gate (420) The second input terminal and an output gate (402) connected to an output terminal connected to an internal clock output sign (ICO). There is a first input terminal connected to the output terminal of the ICO and the AND gate (402), a second input terminal 'connected to the output terminal of the reverse gate (422), and an AND gate (404) of the output terminal. A sum gate (408) having a first input terminal, a second input terminal, and an output terminal connected to the XCI. A first input terminal connected to the output terminal of the AND gate (408), a second input terminal connected to the output terminal of the AND gate (404), and an OR gate (406) of the output terminal. There is a clock recovery circuit (414) connected to the input terminal of the T interface and the output terminal. It has an input terminal connected to the output terminal of the clock recovery circuit (414), and a divide-by-64 divider (416) at the output terminal. A first input terminal connected to a 16.384MHz clock signal, a second input terminal connected to an output terminal of a divide-by-64 divider (416), a first output terminal, a second output terminal, and an OR gate (4 〇6) The control terminal switch (410). A DPLL (412) having a first input terminal connected to a first output terminal of the switch (410), a second input terminal connected to a second output terminal of the switch (4.0), a first output terminal, and a second output terminal. There is an input terminal 'connected to the first output terminal of the DPLL (412) and a divide-by-512 divider (418) at the output terminal. A buffer (424) having an input terminal connected to an output terminal of a divide-by-512 divider (418), an output terminal connected to FSC0, and an output terminal connected to an OR gate (406) and a control terminal of a switch (410) ). And an input terminal connected to the second output terminal of the DPLL (412), an output terminal connected to the DCL0, and a control terminal connected to the buffer (424), or an output terminal and switch (41) of the OR gate (406) Control of the control side (please read the precautions on the back before filling this page)

This paper size applies to Chinese National Standard (CNS) / Y 丨 specifications (21〇χ 297 meals) 560141 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7847twf. Doc / 009 V. Buffer of the invention (q) system end (426) ° In this embodiment, 'assuming chip0) has the highest priority and chiP (N) has the lowest priority. This priority selection circuit will be described in detail with reference to FIG. 4. If the XCI of chip (M) is 0, that is, when XCI (M) = 0, it means that chipO (-1), chiP (M_2), ..., chip (l) have higher priority than this chip. The first layer of a chip has been enabled, and the ACTL1 signal of this chip is 0, indicating that this chip has been selected as the source that provides the reference synchronization clock source. And those with lower priority than chip (M) (including chip (M), chip (M + 1), chip (M + 2), ..., chip (N) will not be selected as the synchronization clock source. So chip (M) 's ACTLl (M) signal is 1. As can be seen in Figure 4, the chip (M)' s ICO (M) is the output of XCI (M) and ACTLl (M) via gate 402, because XCI (M ) = 0, so ICO (M) = 0. Because XCI (M + 1) = ICO (M) = 0, so ICO (M + 1) = 0. Similarly, ICO (M + 2), ICO (M +3), ..., ICO (N) are all 0. Because ICO is an input of AND gate 404, the output of gate 404 is 0. Therefore, the output of OR gate 406 is En (M), En (M + 1) ···, En (N) can be simply the inverted output signal of XCI and ACT1 through the first inverse gate 420, and the output of the AND gate 408. Because chip (M), chip (M + l), chip (M + 2), ..., XCI of chip (N) is 0, ACT1 is 1, then the output signal Eri of gate 408 is all 0. Because chip (M), chip (M + 1), chip (M + 2), …, En of chip (N) are 0, so the switch 410 is in an open state, so that the clock of DPLL 412 is disabled, and the FSCO and DCLO signals are also disabled, so chip (M), chip (M + l), chip (M + 2), ... chip (N) is not selected Scale applicable Chinese National Standard (CNS) A4 size (210 x 297 mm) (Please read the back of the precautions to fill out this page)

560141 7847twf.doc / 009 A7 B7 V. Description of the invention) is the source of the synchronous clock. At this time, only the DPLL of the selected chip will be enabled, and the DPLL of other chips will be disabled. Therefore, the system can achieve the function of saving power consumption. If XCI (M) is 1, it means that the first layer among chip (Ml), chip (M-2), ". 'ChipO) which has higher priority than this chip is not enabled, but is in division. Can state. Therefore, those with lower priority than chip (M) (including chip (M), chip (M + 1), chip (M + 2), ..., chip (N) can be selected as the synchronous clock Source. If any of chip (M), chip (M + 1), chip (M + 2), ..., chip (N) is enabled, the ACTL1 signal of this chip is 0, in this example In the example, chip (M) is selected as the synchronization clock source, so ACTL1 (M) = 0, referring to Figure 4, we can know that ICO (M) = 0 〇 makes En (M) can be simply XCI (M) and The inversion of ACT1 (M) passes the output of the AND gate 408, so En (M) is 1. Since the switch 410 is turned on at this time, the DPLL 412 is enabled, and the three-level signal from the T interface (Pseudo Tenary Coding) Through the clock recovery circuit 414 and the divide-by-64 divider 416, an 8kHz clock signal synchronized with the office is generated. When the switch 410 is turned on, the DPLL 412 uses the clock 16.384MHz outside the chip to lock the clock 8kHz synchronized to the office. To generate a clock of 4.096 MHz and use the buffer 426 as the DCLO clock of the local ISDN PBX. The clock of 4.096 MHz generates a clock of 8 kHz through the divide-by-512 divider 418 and the buffer 424 as a local FSCO clock of ISDN PBX. Because DCLO It is an open drain signal with FSCO, so the DCLO and DCL, FSCO and FSC of chip (l), chip (2) ... chip (N) are all connected together, and the clock of this local ISDNPBX is transmitted to the The selected Chip (l), chiP (2), ... chip (Ml), this paper size applies to Chinese national standards (CNS> A4 specification (21〇χ297297)> (Please read the notes on the back first (Fill in this page again) Packing -------- Order --------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 560141 7847twf.doc / 009 A7 B7 Employee of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperatives V. Description of Invention (u)

DCL and FSC for chip (M + l), chip (M + 2), ..., chip (N). Because ICO (M) = 0 and XCI (M + 1) which is serially connected to the lower priority chip (M + 1), XCI (M + 1) = 0, so the priority over chip (M) is The low chip (M + l) has En of 0 and ICO (M + 1) = 0, the same is true for chip (M + 2), chip (M + 3), ..., chip (N) 's En and ICO are 0 . Even if the first layer of chip (M + 2), ^^% + 3), ..., (: 1 ^ (> 〇) enters the enabled state (person (: several 1 = 0), due to XCI (M + 2), XCI (M + 3) ... XCI (N) are all 0, so the En and ICO of chip (M + 2), chip (M + 3), ..., chip (N) are still 0. Therefore If chip (M) is selected, then chip (l), chip (2), ..., chip (Ml), chip (M + l), chip (M + 2), ..., chip (N) The DPLL will be in a disabled state. That is, only the dpll of the selected chip will be enabled, and the DPLL of other chips will be in a disabled state. Therefore, the system will achieve the function of saving power consumption. If all chips are in the disabled state State, that is, ACTLl (l) > ACTL1 (2), ..., ACTLl (N) and XCI (l), XCI (2), ..., XCI (N) are all 1, so ICO (l), ICO (2), ..., ICO (M) are all 1. Except that the PL signal of chip (N) with the lowest priority is set to 0, other chips (l), chip (2), ..., chip (Nl ) 'S PL signal is set to 1. Because the output of the PL signal of chip (N) after the back gate 422 is a high logic level, and the output of the gate 404 is a high logic level. The output En of the OR gate 406 is 1 while The switch 410 is turned on, and then provides an arbitrary execution clock to the DPLL, so that the system provides a stable and arbitrary execution clock to the system when there is no outside call. In this case, only the DPLL of chip (N) will Yes, the DPLLs of other chips are in the range of 13 (please read the precautions on the back before filling this page). Install --------- Order II -----. This paper size applies to Chinese national standard (CNSM4 Specifications (210 x 297 meals) 560141 7847twf. Doc / 009 Λ7 B7 V. Description of the invention (\ 1) The state of performance. So the system achieves the function of saving power consumption. In summary, the invention has the following advantages: 1. Regardless of the operation of the outside line, the ISDN PBX's priority selection circuit that automatically selects the synchronization clock source can automatically select the highest priority immediately, and the first layer of the LT-T chip is enabling the recovery clock as the synchronization clock. Source to ensure the system performance of the 1SDN PBX that automatically selects the synchronous clock source. If the ISDN PBX that automatically selects the synchronous clock source is not used by any outside call, it can provide a stable arbitrary execution clock to the system. 2. Solve the first layer enable of which outside line is continuously polled and compared by the software to decide to choose the reference synchronous clock source method. 3. Software no longer needs to waste resources to determine the source of synchronization clock. 4. Because this ISDN PBX contains DPLL circuit, it can reduce the space occupied by the printed circuit board and the number of components on the printed circuit board. The present invention provides a DPLL power-off function, that is, only the power of the DPLL selected as the reference clock source will be turned on, and the power of the DPLL not selected as the reference clock source will be turned off to achieve power saving. the goal of. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 14 (Please read the precautions on the back before filling out this page) > 1 pack I I--order ---! !! -Line Edge Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to Chinese national standards (CNS > / V1 specifications (21〇χ 297 meals)

Claims (1)

560141 7847twf.doc / 009 B8 C8 D8 _ VI. Patent Application Fan Garden 1. An integrated service digital network dedicated small switch that automatically selects a synchronous clock source, including: multiple priority selection circuits, daisy-ring circuits A sequential connection method is used to send a frame synchronous clock output signal and a data clock output signal; a plurality of trunk chips are connected to a network terminal through a trunk interface, and then connected to a local terminal through the network terminal, For receiving the frame synchronous clock output signal and the data clock output signal; and a plurality of client chips connected to a terminal device through a client interface for receiving the frame synchronous clock output signal and the data Pulse output signal. 2. The integrated service digital network dedicated small switch that automatically selects the synchronous clock source as described in item 1 of the scope of the patent application, wherein each of the priority selection circuits includes: a first reverse gate having a connection to the A first anti-brake input terminal and a first anti-brake output terminal of the first layer of the energy chip of the main line chip; Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the note on the back first) (Fill in this page again) A second reverse gate with a second reverse gate input connected to a priority level signal, and a second reverse gate output with a first sum gate connected to an external clock indicator A first and first input terminal of the signal, the enable signal connected to the first layer of the trunk chip and a first and second input terminal of the first anti-gate input terminal, and when connected to an internal A first sum gate output terminal of the pulse output signal; a sum gate having a connection to the internal clock output signal and the first 15 paper standards applicable to China National Standards (CNS) A4 specifications (2ΐ〇χ297 公 董) ) 560 141 7847 twf.doc / 009 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. The scope of patent application and the output of the gate and the first input of the gate, the first connected to the output of the second reverse gate and the gate of the second An input terminal and a gate output terminal; a third gate having a third and gate first input terminal, a third and gate second input terminal, and a third gate connected to the external clock indication signal; AND gate output terminal; an OR gate having an OR gate first input terminal connected to the third AND gate output terminal, an OR gate second input terminal connected to the AND gate output terminal, and an OR gate output terminal A clock recovery circuit having a clock recovery circuit input terminal connected to a mains interface and a clock recovery circuit output terminal; a first frequency divider having a first frequency division connected to the clock recovery circuit output terminal A switch input terminal and a first frequency divider output terminal; a switch having a switch first input terminal connected to a first clock signal and a switch second input terminal connected to the first frequency divider output terminal ,One Off the first output terminal, a switch second output terminal, and a switch control terminal connected to the OR gate output terminal; a digital phase locked loop having a first input terminal of a digital phase locked loop connected to the first output terminal of the switch A digital phase-locked loop second input, a digital phase-locked loop first output, and a digital phase-locked loop second output connected to the second output of the switch; a second frequency divider having a connection to A second frequency divider input terminal of the first phase output terminal of the digital phase locked loop, and a second frequency divider output terminal; a first buffer having a first buffer connected to the second frequency divider output terminal Input terminal, 16—ϋ fen ϋϋ ml ϋ— n —ϋ 11 连接 connected to a frame synchronous clock output signal (please read the note on the back before filling this page)-'This paper size applies to Chinese national standards ( CNS) M specifications (210 X 297 mm) 560141 A8 7847twf.doc / 009 B8 C8 D8 VI. Patent application scope-a first buffer output terminal, and a first connected to the OR output terminal and the switch control terminal A buffer control terminal; and a second buffer having a second buffer input terminal connected to the second output terminal of the digital phase-locked loop, a second buffer output terminal connected to a data clock output signal, and A second buffer control terminal connected to the buffer control terminal, the OR gate output terminal and the switch control terminal. 3. The automatic selection of the synchronous clock as described in item 2 of the scope of the patent application. The integrated service digital network dedicated small switch of the source, wherein the digital phase locked loop is placed in the integrated service digital network of the automatic selection of the synchronous clock source The chip of the special switchboard of the road. 4. As described in item 1 of the scope of the patent application, an integrated service digital network dedicated small switch that automatically selects a synchronous clock source, wherein each of these priority selection circuits includes a first reverse gate for One of the mainline chips is a logic inversion of the uniform energy signal of the first layer of the mainline chip, and an output signal of one of the first reverse gates is generated, and a second reverse gate is used to logically invert a priority level signal. Output signal of one of the second counter-gates; printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) A first gate to indicate an external clock The signal and the enable signal of the first layer of the mainline chip are subjected to a logical operation to generate an internal clock output signal; a AND gate is used to connect the internal clock output signal with the signal from the second reverse gate. The output signal is subjected to AND logic operation to generate an output signal of the AND gate. 17 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 560141 7847twf.doc / 009 A8 B8 C8 D8 VI. Application A third range gate is used to perform an AND operation on the external clock indication signal and the output signal from the first reverse gate to generate an output signal of the third level gate; a * or wide ' The OR signal is used to perform an OR operation on the output signal from the second device and the output signal from the AND gate to generate a uniform energy signal. A clock recovery circuit is used to convert a three-state signal from a trunk interface. . The number is converted into a second clock signal; a first frequency divider for dividing the second clock signal to generate a third clock signal; a switch, if the enable signal is high Logic level, the switch will be turned on. If the enable signal is low logic level, then the switch will be in an open state. A digital phase locked loop is used to receive a first clock when the switch is turned on. Signal and a third clock signal to generate a fourth clock signal; a second frequency divider for dividing the fourth clock signal to generate a fifth clock signal; a first Buffer: Shellfish Consumption of the Central Bureau of Standards of the Ministry of Economic Affairs Cooperative printed (please read the precautions on the back before filling this page) When the enable signal is high logic level, then the first buffer is enabled, and the fifth clock signal is used as a frame synchronization clock The clock of the output signal; and when the enable signal is at a low logic level, then the first buffer will be in a disabled state; and a second buffer: 18 This paper size applies Chinese National Standard (CNS) A4 Specifications (21 × X 297 mm) 560141 A8 7847twf.doc / 009 B8 C8 D8 VI. Patent application scope When the enable signal is a high logic level, the second buffer is enabled, and the fourth time The pulse signal is used as the clock of a data clock output signal; and (please read the precautions on the back before writing this page) When the enable signal is a low logic level, the second buffer will be in the disabled state status. 5. The integrated service digital network dedicated small switch that automatically selects the synchronization clock source as described in item 4 of the scope of the patent application, wherein the digital phase-locked loop is used to lock and synchronize the first clock signal to the central office. The third clock signal is used to generate the fourth clock signal as the clock of the data clock output signal of the local integrated service digital network dedicated small switch, and the fourth clock signal is passed through the second division. The frequency generator generates the fifth clock signal 'as the clock of the synchronous clock output signal of the frame of the local integrated service digital network dedicated small switch. 6. —A method for automatically selecting a synchronous clock source, which is applicable to an integrated service digital network dedicated small switch having a plurality of trunk chips and a plurality of client chips, including the following steps: providing a plurality of priority selection circuits; and Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs when an outside call is made, the priority selection circuits will automatically select one of the priority selection circuits with the highest priority and one of the trunk chips, and the trunk The first layer of the chip is enabled and provides a synchronous clock source synchronized to a local end. 7. The method for automatically selecting a synchronous clock source as described in item 6 of the scope of patent application, wherein the synchronous clock source is generated by a clock recovery circuit in the priority selection circuit. 19 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 560141 A8 7B4Vtwf.doc / 003? Δ8 D8 6. Application for patent scope 8. Automatic selection of synchronization clock as described in item 6 of patent scope The source method, in which the other priority selection circuits that are not selected as the synchronous clock source and the first layer of the other mainline chips are all disabled. 9. The method for automatically selecting a synchronous clock source as described in item 6 of the scope of the patent application, wherein if there is no outside call, the priority selection circuits will have the same performance of the priority selection circuits with the lowest priority. The signal (Εη) is enabled and provides a stable random execution clock. 10. —A control method for a digital phase-locked loop that automatically selects a synchronous clock source, which is suitable for an integrated service digital network dedicated small switch with a plurality of mainline chips, a plurality of client chips, and a plurality of priority selection circuits. Including the following steps = providing a plurality of digital phase-locked loops and placing them in the priority selection circuits; when an outside call is made, the priority selection circuits automatically select one of the priority selection circuits with the highest priority and the One of the mainline wafers, and enable the first layer of the mainline wafers to provide a synchronized clock signal synchronized to a central office; and printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back first) (Fill in this page again) Use one of the digital phase-locked loops in the priority selection circuit to lock the synchronous clock signal synchronized to the central office. 11. The control method of the digital phase locked loop for automatically selecting a synchronous clock source as described in item 10 of the scope of patent application, wherein the digital phase locked loop is in an enabled state. 12. When automatic synchronization is selected as described in item 10 of the scope of patent application, 20 paper sizes are applicable to Chinese National Standard (CNS) A4 specification (210 × 297 mm) 560141 A8 7S47twf.doc / 00.? Δ8 D8 6. Application scope The control method of the digital phase-locked loop of the pulse source, wherein the other digital phase-locked loops which are not selected as the pulse source at the time of synchronization are in a disabled state. 13. The control method of the digital phase-locked loop for automatically selecting a synchronous clock source as described in item 10 of the scope of patent application, wherein when there is no outside call, only one of the priority selection circuits with the lowest priority will cause Yes, and the other digital phase-locked loops are disabled. (Please read the precautions on the back before filling out this page) Copy and print 2 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Printed by the Bayer Consumer Cooperatives 2 The paper size applies to the Chinese National Standard (CNS) Α4 specification (210 × 297 mm)