JP2664880B2 - Clock signal generation method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for generating clock signals of various ratios in an electronic circuit, in particular a microprocessor.

[0002]

BACKGROUND OF THE INVENTION In the prior art, the internal clock of a microprocessor (ie, the processor clock) is:
It operates at basically the same speed as the frequency of the external system clock, or simply at an integer multiple thereof. For example, when a microprocessor in a system operates at 66 MHz, the external system clock may simply be one-half, one-third, or one-quarter of that frequency (ie, 33, 22 respectively). , 16.5 MHz).

[0003] Microprocessors have traditionally typically included a processor that responds to an external system clock signal.
A phase locked loop clock generator is provided for generating a clock signal. FIG. 1 shows a delay element 1
1 shows a conventional phase-locked loop clock generation device 100 including the same. Clock generator 100 receives an external system clock signal and outputs a delayed system clock signal that essentially matches the propagation delay of divider 150 (divider 150 is described below).

[0004] Phase comparator 120 receives the delayed system clock signal from delay element 110 and the “clock” signal from divider 150. The phase comparator 120 has a circuit that generates a DC voltage in response to a change in the phase or frequency of these two clock signals.

Specifically, if the phase of the "clock" signal lags behind the delayed system clock signal, the phase comparator 12
0 outputs a slightly larger DC voltage. Similarly,
If the frequency of the "clock" signal lags the delayed system clock signal, phase generator 120 outputs a large DC voltage.

Next, a voltage controlled oscillator (VCO) 130
Outputs a signal having a clock frequency corresponding to the voltage output of the phase comparator 120. That is, the phase comparator 12
The higher the voltage output of 0, the higher the frequency of the clock signal output of the voltage controlled oscillator 130. vice versa,
The smaller the voltage output of the phase comparator 120, the more
The frequency of the clock signal output of the voltage controlled oscillator 130 becomes lower.

In this manner, the voltage controlled oscillator 130 and the phase comparator 120 operate together so that the phase and frequency of the "clock" signal are substantially the same as the delayed system clock signal at the input of the phase comparator 120. And make sure they match. Several repetitions are required for these clock signals to essentially match.

[0008] H-tree distribution network (hereinafter abbreviated as distribution network)
140 distributes the output of the voltage controlled oscillator to the entire microprocessor. This output operates as an internal processor clock signal, which is driven into the processor by a plurality of clock regenerators 142 over distribution network 140.

The output of the clock regenerator 146 is
Feedbacked back to zero, divider 150 divides the frequency of this output by n. This factor n represents the desired ratio between the processor clock frequency and the external system clock frequency. Next, the divider 150 is connected to the phase comparator 120.
Output a "clock" signal. However, the phase comparator 1
20 and the voltage controlled oscillator 130 ensure that the "clock" signal has essentially the same frequency / phase as the delayed system clock signal, so that the voltage controlled oscillator 1
30 finally outputs an internal processor clock signal having a frequency that is a multiple of the frequency of the external system clock. Therefore, the internal processor clock signal has a frequency that is n times the frequency of the external system clock.

As dictated by system design, it is desirable that the external system clock signal operate at its maximum frequency whenever possible. For example, if the optimal frequency of the external system clock is 66 MHz and the optimal internal clock frequency of the microprocessor is 100 MHz, the latter is 1.5 times the former.

However, the clock generator 100 must be an integral multiple (ie, "n" times) of the external system clock frequency.
Since the clock generation device 100 generates
The optimal processor clock frequency cannot be generated. Therefore, the clock generation device 100
The disadvantage is that it can only support processor clock frequencies with a clock ratio of n: 1 times the external system clock frequency. Therefore, there is a great need for a clock generator capable of generating and distributing clock signals having a ratio of n: m (n and m are integers) in a microprocessor.

Typically, a microprocessor has logic such as a bus interface unit that operates at an external system clock frequency. However, unfortunately, the clock generator 100 only generates one high speed internal processor clock signal. Therefore, it is necessary to use another method of distributing the external system clock signal to the logic driven by the bus (eg, the distribution network described above).

[0013]

Accordingly, there is a great need for a clock regenerator that generates and distributes an internal processor clock signal and an internal system clock signal to the entire microprocessor using the same distribution network. That is, such a clock generation device must have a function of generating and distributing a plurality of in-phase clock signals inside the microprocessor (including a function of a ratio of n: m).

In addition, delay element 110 receives an external system clock signal and has a delay system having a phase that essentially matches the "clock" signal of divider 150.
By outputting the clock signal, the propagation delay of the divider 150 is compensated. However, the delay element 110 is connected to the divider 15
It is not possible to exactly match the propagation delay of zero, and the "clock" signal has a slight skew when compared to the delayed system clock, thus slowing the overall system. Therefore, a clock regenerator that does not require a delay element is required for realizing the design.

[0015]

SUMMARY OF THE INVENTION A method is provided for generating a processor clock signal having a ratio of n: m to an external system clock and generating an internal system clock signal. The method includes comparing an internal system clock signal with an external system clock signal to create a DC voltage output, and generating a processor clock signal in response to the DC voltage output, wherein the processor clock signal and n:
generating a plurality of gating signals in response to the m ratio, generating an internal system clock signal in response to the gating signal and the processor clock signal, and providing the processor clock signal and the internal system clock signal to the entire processor. Distributing.

Further, there is provided an apparatus for generating an internal system clock signal and a processor clock signal having an n: m ratio with respect to an external system clock signal. This device uses an internal system to create a DC output voltage.
A comparator for comparing the clock signal with an external system clock signal; an oscillator for generating a processor clock signal in response to the DC output voltage; and a plurality of gatings in response to the processor clock signal and the n: m ratio. Modification logic to generate signals, gating signals and processor
A clock regenerator for regenerating an internal system clock signal in response to the clock signal. The regenerator also
Distribute the processor clock signal and the internal system clock signal throughout the processor.

Accordingly, it is an object of the present invention to generate an internal processor clock frequency having a ratio of n: m to an external system clock frequency.

Further, an object of the present invention is to provide an external system
In response to a clock signal, generating an internal processor clock and an internal system clock and distributing these signals to the entire microprocessor.

[0019]

FIG. 2 illustrates the present invention embodied within a microprocessor 10. FIG. Microprocessor 10 is a single integrated circuit microprocessor of the superscalar type. Microprocessor 10 operates according to the "RISC" approach. However, it should be understood that the invention can be implemented within other processors and on other hardware platforms.

The system bus 11 includes a data line and a clock line. The clock line is connected to the clock generator 300 of the present invention, and the data line is connected to the bus interface unit 12. bus·
The interface unit 12 controls the transfer of information between the processor unit 20 and the system bus 11. Clock generator 300 generates an internal processor clock signal and distributes it to, for example, processor unit 20 and also generates an internal system clock signal, for example, to bus interface unit 12. These signals are generated in response to a clock line on the system bus 11.

FIG. 3 shows components of the clock generator 300. The clock generation device 300 includes the phase comparator 32
0, voltage controlled oscillator 330, distribution network 340, modification logic 3
50 and clock regenerators 342, 344, 346
Having.

The clock generator 300 generates an internal processor clock signal (Proc-clk) and an internal system clock signal (System-clk-internal) in response to the external system clock signal 310. To do this, the phase comparator 320 uses the internal system clock signal 365 from the clock regenerator 346 and the system
External system clock signal 31 from bus 11 (FIG. 2)
Receives 0. Phase comparator 320 includes a circuit that generates a DC voltage in response to a phase or frequency change between these clock signals.

Specifically, if the internal system clock signal 365 lags the external system clock signal 310, the phase comparator 320 will output a slightly larger DC voltage. Similarly, the internal system clock signal 3
If the frequency of 65 lags the frequency of external system clock signal 310, phase comparator 320 outputs a large DC voltage.

The voltage controlled oscillator 330 is connected to the phase comparator 32
A circuit for generating a 50% duty cycle square wave clock signal having a frequency responsive to a zero voltage output. That is, the greater the voltage output of the phase comparator 320, the higher the frequency of the clock signal output by the voltage controlled oscillator 330. Conversely, if the voltage output of the phase comparator 320 is smaller, the frequency of the clock signal output by the voltage controlled oscillator 330 is lower.

In this manner, the voltage controlled oscillator 330 and the phase comparator 320 operate in cooperation, and the phase and frequency of the internal system clock signal 365 are
At the input of the external system clock signal. Several repetitions may be required until these signals basically match.

The distribution network 340 outputs the output of the voltage controlled oscillator 330 (ie, the distribution clock 341) to the modification logic 35.
0, and distributed to multiple nodes within the entire microprocessor. Each node is equidistant from the voltage controlled oscillator 330 and a plurality of clock regenerators 342, 344, 346
Including one of the following. However, it should be understood that other distribution networks could be used to distribute the output of voltage controlled oscillator 330 to the entire microprocessor.

FIG. 4 shows that the modification logic 350 is
0, master / slave latches 420, 430, 44
0, an inverter 450, and a clock regenerator 460. The input circuit 410 includes an AND gate 411,
412 and 413, and OR gates 414 and 415. Clock regenerator 460 regenerates distributed clock 341 and provides master / slave latches 420, 430,
440. Thus, during the negative cycle of the distribution clock 341, the master latch opens and the slave latch latches. Conversely, during the positive cycle of distribution clock 341, the master latch latches and the slave latch opens. Latches 420, 430, and 44
0 is triggered on the positive edge (rising) of the distribution clock 341.

The input circuit 410 receives the ratio of the user-defined processor clock frequency to the external system clock signal frequency, ie, the n: m ratio. Selection ratio input 356 (FIG. 3) includes a set of input pins 401, 402 for defining a desired n: m ratio. For example, "0, 0" is assigned to pins 401 and 402, respectively.
To enter a 1: 1 ratio, enter "0,1" to correspond to 2: 1, and similarly, "1,0" becomes 3: 1,
“1, 1” corresponds to 3: 2. Alternatively, additional pins may be used to specify another ratio.

User defined ratio and distribution clock 34
In response to a phase / frequency of one, input circuit 410 produces three output signals 416, 417, 418. Output signal 416 is latched by master / slave latch 420 and then fed back to input circuit 410. Output signal 417 is output from master / slave latch 4
30 is latched by the master latch and then inverted by the inverter 450 to provide the gating signal 3
52 is generated. Master / slave latch 430
Slave latch latches the signal previously latched from its master latch, and feeds back the latched signal to input circuit 410. Finally,
Output signal 418 is output to master / slave latch 440.
To generate a gating signal 354.

Thus, the modifier logic 350 receives the n: m ratio and the distribution clock 341 and, in response, the gating signal (QUAL1) 352 and the gating signal (Q
UAL2) 354 is generated.

FIGS. 5, 6, and 7 show timing charts of the modification logic 350 corresponding to user-defined 3: 2, 2: 1, and 3: 1 ratios, respectively. Specifically, FIGS. 5-7 illustrate external system clock signal 310, processor clock 360 (ie, distributed clock 3).
41), gating signals 352 and 354, and internal system clock signal 365. In each of FIGS. 5-7, the external system clock signal 310 is:
Have the same frequency, phase and duty cycle.

In FIG. 5, processor clock 360
Is 1.times. Of the frequency of the external system clock signal 310.
It has five times the frequency. In FIG. 6, processor clock 360 has twice the frequency of external system clock signal 310. Further, in FIG. 7, processor clock 360 has a frequency that is three times the frequency of external system clock signal 310.

Further, as shown in FIGS. 5-7, the internal system clock signal 365 has a different duty cycle, but has basically the same phase and frequency as the corresponding external system clock signal 310. ing. That is, each internal system clock signal 365
At the beginning of each corresponding external system clock signal.

Referring to FIGS. 3 and 8, each of the clock regenerators 342, 344, 346 has an input circuit 500 for generating a processor clock 360 or an internal system clock signal 365. These clock signals are generated in response to the distribution clock 341 and the signals input to inputs 510 and 520.

To generate internal system clock signal 365, inputs 510 and 520 of clock regenerators 344 and 346 respectively receive gating signals 352 and 354, respectively. The gate 501 “ANDs” the distribution clock 341 and the gating signal 352.
Then, the gate 502 “ANDs” the gating signal 354 and the inverted distribution clock 341. Next, gate 503 "ORs" the outputs of gates 501 and 502 to generate internal system clock 365.

To generate processor clock 360, inputs 510 and 520 of clock regenerator 342 are
They are kept at constants “1” and “0”, respectively. as a result,
Clock regenerator 342 regenerates a clock signal (ie, processor clock 360) that is essentially equal in phase and frequency to distributed clock 341. Also,
For ratios greater than 3: 2 (e.g., 4: 3, 5: 4), the modifier logic 350 outputs
, And two additional gating signals can be generated.

In summary, modifier logic 350 operates with clock regenerators 344 and 346, respectively, to generate "n" (eg, 1, 2, or 1) on distributed clock 341 to generate internal system clock signal 365. 3), then divide the result by "m" (eg, 1 or 2). To do this, the qualification logic 350
Is the distribution clock 341 and the user defined n: m
In response to the ratio, the gating signals 352 and 354
Generate Next, the clock regenerators 344 and 346
Each of the input circuits 500 generates an internal system clock signal 365 in response to the distribution clock 341 and the gating signals 352 and 354.

The output of clock regenerator 346 (ie,
The internal system clock signal 365) is
It is fed back to 0. Since the phase comparator 320 and the voltage controlled oscillator 330 cooperate to ensure that the internal system clock signal 365 has essentially the same frequency and phase as the external system clock signal 310, the voltage controlled oscillator 330 System clock signal 31
A signal having a frequency n / m times the frequency of 0 (ie,
The distribution clock 341) is finally output.

FIG. 9 shows a second embodiment of the clock generator 600. The clock generator 600 includes a delay element 6
10, phase comparator 320, voltage controlled oscillator 330, distribution network 340, modification logic 350, clock regenerator 342,3
44 and 346, and a divider 660.

The output of clock regenerator 344 (ie,
Processor clock 360) is fed back to divider 660. Divider 660 includes circuitry that multiplies processor clock 360 by "n" and divides the result by "m". Delay element 610 receives external system clock signal 310 and generates a delayed system clock signal that essentially matches the propagation delay of divider 660. In all other respects, the clock generator 60
0 functions similarly to the clock generator 300 (FIG. 3).

[0041]

[0042]

The present invention provides a method and apparatus for generating a processor clock signal having a ratio of n: m to an external system clock and generating an internal system clock signal. In the prior art, the above n: m can only support the ratio of n: 1, and the optimal processor
While the clock frequency cannot be generated, the present invention adopts the configuration described in the embodiment to support the ratio of n: m to the external system clock and generate the optimum processor clock frequency. be able to.

[Brief description of the drawings]

FIG. 1 illustrates a prior art phase locked loop clock generation and distribution mechanism.

FIG. 2 is a block diagram of a microprocessor for processing information according to an embodiment of the present invention.

FIG. 3 illustrates a phase locked loop clock generator and distribution mechanism according to an embodiment of the present invention.

FIG. 4 is a schematic diagram showing the modification logic according to the present invention.

FIG. 5 is a timing diagram of a 3: 2 ratio according to the present invention.

FIG. 6 is a timing diagram of a 2: 1 ratio according to the present invention.

FIG. 7 is a timing diagram of a 3: 1 ratio according to the present invention.

FIG. 8 is a schematic diagram showing an input circuit of a clock regenerator according to the present invention.

FIG. 9 is a diagram showing a phase locked loop clock generator and a distribution mechanism according to a second embodiment of the present invention.

[Explanation of symbols]

10 Microprocessor 11 System bus 12 Bus interface
Unit 20 Processor unit 100 Prior art clock generator 110, 610 Delay element 120, 320 Phase comparator 130, 330 Voltage controlled oscillator 140, 340 Distribution network 150, 660 Divider 142, 146, 342, 344, 346, 460
Clock regenerator 300, 600 Clock generator according to the present invention 310 External system clock signal 341 Distribution clock 350 Modification logic 352, 354 Gating signal 356 Ratio select input 360 Processor clock (=
Distribution clock 341) 365 Internal system clock signal 401, 402 Input pin 410, 500 Input circuit 411, 412, 413 AND gate 414, 415 OR gate 416, 417, 418 Output signal 420, 430, 440 generated by input circuit 410 Master / slave latch 450 Inverter 501, 502, 503 Gate 510, 520 Clock regenerator (344,
346) Input

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Charles Gordon Wright 1204, Woodrock, Round Rock, Texas, 78681, United States of America 1204 (56) References JP-A-2-255908 (JP, A) JP-A-59-110227 JP, A) JP-A-4-37219 (JP, A) JP-A-4-235616 (JP, A) JP-A-58-47928 (JP, U)

Claims (8)

(57) [Claims] 1. A method for generating a clock signal of a predetermined frequency by feeding back an output clock signal, comprising: an internal processor having a frequency of n: m with respect to the frequency of an external system clock signal. Outputting a clock signal; outputting at least one gating signal representing the ratio; responsive to the internal processor clock signal and the at least one gating signal, the external system clock signal; A clock signal generating method, comprising: outputting an internal system clock signal having the same frequency as the frequency; and feeding back the internal system clock signal. 2. The method of claim 1, wherein outputting the internal processor clock signal comprises generating an output corresponding to a difference between the fed back internal system clock signal and the external system clock signal. Generating the internal processor clock signal in response to the method. 3. A method for generating a clock signal of a predetermined frequency by feeding back an output clock signal, comprising: an internal processor having a frequency of n: m with respect to the frequency of an external system clock signal. Outputting a clock signal; outputting at least one gating signal representing the ratio; responsive to the internal processor clock signal and the at least one gating signal, the external system clock signal; A method for generating a clock signal, comprising: outputting an internal system clock signal having the same frequency as the frequency; and feeding back the internal processor clock signal at a frequency of m / n. 4. The step of outputting the internal processor clock signal comprises: generating an output corresponding to a difference between the fed back internal processor clock signal and the external system clock signal. Generating the internal processor clock signal in response to the method. 5. An apparatus for generating a clock signal having a predetermined frequency by feeding back an output clock signal, the internal processor having a frequency of n: m with respect to the frequency of an external system clock signal. Means for outputting a clock signal; means for outputting at least one gating signal representing said ratio; and means for responsive to said internal processor clock signal and said at least one gating signal, A clock signal generator comprising: means for outputting an internal system clock signal having the same frequency as the frequency; and means for feeding back the internal system clock signal. 6. A comparator for generating an output corresponding to a difference between the fed back internal system clock signal and the external system clock signal; and an internal processor clock based on the output of the comparator. The apparatus of claim 5, comprising: an oscillator for generating a signal. 7. An apparatus for generating a clock signal of a predetermined frequency by feeding back an output clock signal, the internal processor having a frequency of n: m with respect to the frequency of an external system clock signal. Means for outputting a clock signal; means for outputting at least one gating signal representing said ratio; and means for responsive to said internal processor clock signal and said at least one gating signal, A clock signal generating apparatus comprising: means for outputting an internal system clock signal having the same frequency as the frequency; and means for feeding back the internal processor clock signal by setting the frequency to m / n. 8. A comparator for generating an output corresponding to a difference between the fed back internal processor clock signal and the external system clock signal; and the internal processor clock based on the output of the comparator. The apparatus of claim 7, comprising: an oscillator for generating a signal.