JP2000068819A - Counter circuit, frequency bisected logic circuit and clock signal supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize the rising edges of an input clock and counter output without providing an initial value reset mechanism by selecting one of the outputs of first and second latch circuits and outputting the output data. SOLUTION: When an input clock IN is at 'H' level and an inverted clock CKB is at 'L' level, a transfer gate 31 is turned to on-state and the transfer gate 32 is turned to off-state. When the input clock IN is at 'L' level and the inverted clock is at 'H' level, the transfer gate 31 is turned to off-state and the transfer gate 32 is turned to on-state. A selector 30 selects one of the holding data of a master latch 10 and a slave latch 20 and outputs it through an inverter 33 with the input clock IN as a selector signal. An edge is outputted once every time the total of the rising and falling edges of the input clock IN is two, and the respective rising edges of the input clock IN and the counter output are synchronized without providing the initial value reset mechanism.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a counter circuit, a frequency-divided logic circuit, and a clock signal supply circuit mounted on a logic circuit device that operates synchronously at a plurality of clock frequencies.

[0002]

2. Description of the Related Art In recent years, circuits and systems for transferring data between logic circuits operating at different clock frequencies or between chips have been increasingly designed, and accordingly, a reference supplied to a PLL circuit has been increased. In some cases, the frequency of the clock and the frequency of the clock that is fed back to the PLL circuit from the end of the clock tree connected after the PLL circuit are different.

In such a case, as shown in FIG.
Frequency dividers 101 and 102 having different frequency division ratios immediately before the circuit 100
, And the feedback input Xin (F) and the reference input Yin (F ′) are frequency-divided by the reciprocal frequency-dividing ratios of the respective frequency ratios so as to have the same frequency.
At 0, the phase is adjusted. That is, the clock signal supply circuit shown in FIG.
Clock signal Xin of F ′ (F: F ′ = p: q)
(F) and Yin (F ') are divided into 1 / p and 1 / q, respectively, and the signals X (f) and Y (f) are aligned at the same frequency f.
Is input to the PLL circuit 100 to adjust the phase, and then an output signal Z (F) having a frequency F is generated.

Consider a data transfer procedure between a logic circuit connected to the output terminal of the PLL circuit 100 shown in FIG. 5 and operating at the frequency F and a logic circuit operating at the same frequency F 'as the clock of the reference input Yin. In this case, in order to avoid complicating the operation procedure and the timing design, the feedback input Xin and the reference input Y
It is desirable that the clock phase relationship be uniquely determined between in.

Since the PLL circuit 100 adjusts the timing of the output Z such that the phases of the rising edges of the inputs X and Y are aligned as its own function, the rising and falling of the clock edge before and after the frequency division are performed. Can be provided correctly, and a frequency divider pair can be provided such that the operation delay of the frequency divider circuit becomes equal between the two frequency dividers 101 and 102.
And the reference input Yin can uniquely guarantee the synchronization of the clock edge.

Here, consider a system in which the frequency ratio of the input clock signal is (2n + 1): 2.

FIG. 6 shows a case in which clocks Xin and Yin having a frequency ratio of n = 1, that is, 3: 2 can be generated as a relationship between clock edges when the clocks Xin and Yin are divided by 3 and 2 respectively. That is, in the figure, the frequency ratio F:
A clock signal Xin having F ′ = 3f: 2f = 3: 2,
When Yin is frequency-divided by three and frequency-divided by two to generate clock signals X and Y having a frequency f, combinations that can be taken in correspondence between rising and falling edges between clocks before and after frequency division are shown. .

First, on the divide-by-three side, four combinations of 1A, 1B, 2A, and 2B can be considered as combinations of clock phases before and after frequency division. 1A and 2B, in which rising edges and falling edges are always the same before and after frequency division, and conversely, 1B and 2A in which edges are not always aligned. From the same consideration, also on the divide-by-2 side, the case of 1'A 'and 1'B' and the case of 2'A 'and 2'
The case of B 'can be summarized.

The divided clocks X and Y are shown in FIG.
As shown in (1), the phase is adjusted so that the rising edges and the falling edges of the clocks are input to the PLL circuit 100 so that the rising edges and the falling edges thereof are aligned with each other. Considering the pair of A and A ′, as an independent combination, 1
A, 2A, and the 2 divider side are 1'A 'and 2'A'.

[0010] From this, the clock signals Xin and Xi
1A-1 ′
A ', 1A-2'A', 2A-1'A ', 2A-2'
Although there are four sets of A ′, considering an equivalent set, 1A-1′A ′, where the rising edge of Yin is always synchronized with the rising edge and falling edge of Xin,
2A-1'A ', and conversely, 1A-2'A' and 2A-2'A 'in which the falling edge of Yin is always synchronized with the rising edge and falling edge of Xin. . 1A-1'A 'and 1 as independent cases
A-2 If you choose 'A' as the representative, Xi you want to finally realize
When the phase relationship between n and Yin is 1A-1'A ', 1
There is a need to provide a divider pair that guarantees that A-2'A 'cannot occur.

From the above considerations, regarding the frequency division by three, the set of 1A and 2A is equivalent in relation to the frequency division by two, and it is not necessary to guarantee which combination is the frequency divider by three. That is, the reset mechanism (initial value setting mechanism) of the frequency divider is unnecessary. On the other hand, for frequency division by 2, 1'A 'and 2'
Since it is not equivalent to A ', in order to guarantee that 1A-2'A' does not occur, an edge change of the output clock occurs only at the rising edge of the clock before frequency division as a 2 frequency divider. It is necessary to provide a guarantee mechanism for the dividing edge.

Note that the contents described here hold not only when the frequency ratio of the two input clock signals Xin and Yin is 3: 2 but also generally when the frequency ratio is (2n + 1): 2.

Next, before describing a conventional example of a divide-by-2 frequency divider having a dividing edge guaranteeing mechanism, a circuit configuration of a 2n + 1 odd-numbered frequency divider to be compared with the conventional example will be described.

FIGS. 7 (a) and 7 (b) are diagrams relating to a 3 frequency divider with n = 1, FIG. 7 (a) is a circuit diagram thereof, and FIG. 7 (b) is a clock waveform during the operation. Is shown.

[0015] The three-frequency divider is configured to receive the input clock IN (f).
Unit 210 that generates one rising edge in the output data every time the number of both rising and falling edges is counted three times, and the counter unit 210
The output clock OUT (f / f) is connected to the output clock OUT (f /
3) and an edge generating section 220 for outputting the result.

With such a configuration, the frequency divider of FIG.
As shown in (b), the input clock IN is delayed by the operation delay t3.
(F) is divided by 3 and the output clock OUT (f / 3)
Is output. In this circuit, since there is no reset mechanism in the counter section 210, the operation waveforms IN and OU
The phase relationship of T is not always determined in the illustrated case. This figure only shows possible combinations-examples.

To describe a more specific configuration, the storage logic circuit 221 used in the output edge generating section 220
This is a normal single-edge trigger flip-flop circuit (hereinafter simply referred to as an F / F circuit), and is a so-called master and slave latch that operates at different clock phases (CK, CKB) as shown in FIG. 221a, 2
21b are connected in series. This F /
The F circuit has a function of latching the data D only at the rising edge of the input clock CK.

The storage logic circuits 211 and 212 used in the counter section 210 have double edge triggers.
This is a flip-flop circuit (hereinafter simply referred to as DBL-F / F), and has a circuit configuration in which master and slave latches 211a and 211b are connected in parallel by shorting data input D as shown in FIG. The output is connected to a 2-1 selector 211c that uses the clock CK as a select signal. The DBL-F / F outputs the data DB at both the rising and falling edges of the input clock CK.
Has the function of latching.

As described above, since the initial value setting mechanism is not required for the 周 frequency divider, the circuit shown in FIG. 7 does not include a reset terminal or the like.

As for one of the two frequency dividers, a conventional circuit of a type provided with a mechanism for guaranteeing a frequency division edge is shown in FIG.
There is the one shown in FIG.

The frequency divider shown in FIG. 9A corresponds to the frequency divider shown in FIG.
Is a type of frequency divider composed of the same components as the odd-numbered frequency divider, and outputs one rising edge every time the number of both rising and falling edges of the input clock IN (f) is counted as two in total. And an output edge generator 240 that detects a rising edge from the counter 230 and inverts the output OUT (f / 2).
It is composed of

Also, the frequency division edge is guaranteed, that is, only at the rising edge of the input clock IN, the frequency divider output OUT
In order to guarantee that (f / 2) is inverted, a reset terminal 232 is provided so that the rising edge of the counter unit 230 is synchronized with the rising edge of the input clock IN, and an initial value is set when the operation of the counter unit 230 starts. It has a mechanism.

The frequency divider shown in FIG. 9B has an F /
This is the most basic frequency divider constituted by the F circuit 250, and the output OUT (f / 2) which is the clock value after frequency division is inverted only at the rising edge of the input clock IN.

[0024]

However, the frequencies F and F '(F: F' = 2: 2n + 1 (n = 1, 2, 3, 3)
..)) Are divided into 1/2, 1 / (2n +
The clock signal of the same frequency after the frequency division is
It is necessary to form a frequency divider pair of a 2,2n + 1 frequency divider that inputs the signal to the LL circuit 100 to perform phase matching, and guarantees that the rising edges of the clocks F and F ′ before the frequency division are uniform. In some cases, it is impossible to avoid both of the following two drawbacks at the same time with the conventional configuration method, particularly for the ２ frequency divider.

(1) It is said that a reset input is required for a 2n + 1 frequency divider and a frequency division edge guarantee mechanism for aligning rising edges (a mechanism for guaranteeing that an output change occurs only at the rising edge of the input clock). There was a problem. More specifically, in the 2 divider shown in FIG. 9A, a circuit can be realized with the same components as the odd divider, and thus the 3 divider shown in the operation waveform diagram of FIG. Although it is possible to divide the frequency by 2 with a circuit delay substantially equal to the circuit delay t3, an initial value reset mechanism of the counter unit 230 is required. Therefore, not only does the number of elements and the layout area of the circuit increase due to the reset mechanism of the frequency divider itself, but it is necessary to prepare reset signal supply means that is correctly synchronized with the edge of the clock signal input to the frequency divider. There is a problem that the design and control of the frequency divider and the reset signal supply system as a whole become complicated. In particular, when the clock frequency is on the order of several hundred MHz or more, the influence of delay and the like generated in the wiring for supplying the reset signal is large, and it becomes very difficult to synchronize with the clock signal input to the frequency divider.

(2) There is a problem that the delay of the frequency divider from the 2n + 1 frequency divider is not uniform, and consequently, the edges are not aligned between the F and F 'clocks before the frequency division. More specifically, in the 2 divider shown in FIG. 9B, although a circuit for guaranteeing a dividing edge is inevitably provided in the circuit configuration, the components of the entire divider are shown in FIG. , The circuit delay from the input to the output is smaller than the circuit delay t3 of the 3 divider, and a difference occurs in the circuit delay with the 3 divider. If a difference occurs in the frequency divider circuit delay from the input clock to the output clock between the two frequency dividers in this way, even if the output clocks of both frequency dividers are phase-matched by the PLL circuit, the phases are really matched. The phase between the clock signals before the frequency division is shifted by the difference of the frequency divider circuit delay, which complicates the timing design when performing data transfer between logic circuits driven at the respective clock frequencies.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to make the rising edge of the input clock and the rising edge of the counter output even without providing the initial value reset mechanism. It is to provide a counter circuit that can be synchronized. Also,
Another object of the present invention is to provide a divide-by-two logic circuit that can realize a divided edge guarantee without providing an initial value reset mechanism in the counter section. Still another object is to ensure the correspondence of clock edges so that only the rising edge of one clock is always synchronized with the rising and falling edges of the other clock even without a reset signal, and An object of the present invention is to provide a clock signal supply circuit in which skew does not occur between corresponding clock edges.

[0028]

In order to achieve the above object, a counter circuit according to a first aspect of the present invention has a function of counting that the total number of rising and falling edges of an input clock is two. In a counter circuit in which the correspondence between the rising edge and the falling edge of the output data with respect to the rising edge and the falling edge of the input clock is always kept constant, the first logic constant is latched in synchronization with the input clock. A first latch circuit, a second latch circuit for latching a second logical constant in synchronization with a different phase of the input clock, and the first and second latch circuits using the input clock as a select signal. And a selector circuit for selecting one of the outputs and outputting the output data.

According to the first aspect, the correspondence between the rising edge and the falling edge of the input clock with respect to the rising edge and the falling edge of the input clock is always assured without providing the initial value reset mechanism. .

A feature of the divide-by-two logic circuit according to the second invention is that a rising edge or a falling edge is output every time the number of both rising and falling edges of the input clock is counted two in total. A counter section,
2. A frequency-divided-by-2 logic circuit comprising: an edge generator for detecting a rising edge or a falling edge from the counter unit and inverting an output.
The above-described counter circuit is used.

According to the second aspect of the present invention, the division edge can be guaranteed without providing an initial value reset mechanism in the counter section.

The feature of the clock signal supply circuit according to the third invention is that the frequencies f and f ′ (frequency ratio f: f ′ = 2: 2n)
+1 and n are positive integers).
/ 2, 1 / (2n + 1) frequency-dividing logic circuit and 2n + 1 frequency-dividing logic circuit, and the divide-by-2 logic circuit and 2n
And a PLL circuit for inputting the same frequency clock signal after frequency division by the +1 frequency dividing logic circuit and performing phase adjustment, wherein the two-frequency dividing logic circuit comprises:
The present invention is configured by the divide-by-2 logic circuit.

According to the third aspect of the present invention, it is possible to guarantee the correspondence between clock edges so that only the rising edge of one clock is always synchronized with the rising and falling edges of the other clock without a reset signal. And no skew occurs between corresponding clock edges.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram of a counter circuit according to a first embodiment of the present invention.

This counter circuit separates the input terminal of the DBL-F / F circuit shown in FIG. 8B into a master latch and a slave latch, and holds the data during the "H" level period of the input clock. The power supply potential VDD is applied to the input of the latch.
Has a circuit configuration in which the ground potential GND is connected to the input of the latch that holds data during the “L” level period of the input clock.

Specifically, the counter circuit of the present embodiment
Master latch 10 having power supply potential VDD connected to its input terminal
, A slave latch 20 connected to the input terminal of the ground potential GND, and a selector 30 for selecting an output of the slave latch 20.

The master latch 10 has a power supply potential V
It comprises a transfer gate 11 to which DD is connected and a latch circuit 12 in which two inverters are connected in anti-parallel. The transfer gate 11 receives the input clock I
ON / OFF control is performed by N and an inverted clock CKB of the opposite phase. That is, it is turned on when the input clock IN is at the “L” level and the inverted clock CKB is at the “H” level, and is turned off when the input clock IN is at the “H” level and the inverted clock CKB is at the “L” level. Becomes When the transfer gate 11 is on, “1” data of the power supply potential VDD is input to the latch circuit 12, and while the transfer gate 11 is off, the “1” data is held in the latch circuit 12.

On the other hand, the slave latch 20 has a transfer gate 21 connected to the ground potential GND on the input side.
And a latch circuit 2 in which two inverters are connected in anti-parallel.
And 2. The transfer gate 21 is on / off controlled by an input clock IN and an inverted clock CKB having a phase opposite to that of the input clock IN. That is, the input clock IN
Is at an "H" level and the inverted clock CKB is at an "L" level, and conversely, it is turned off when the input clock IN is at an "L" level and the inverted clock CKB is at an "H" level. When the transfer gate 21 is on, “0” data of the ground potential GND is input to the latch circuit 22, and while the transfer gate 21 is off, the “0” data is held in the latch circuit 22.

The selector 30 comprises transfer gates 31 and 32 connected to the output side of the master latch 10 and the slave latch 20, respectively, and an inverter 33 connected to the output side. The transfer gates 31 and 32 are on / off controlled by an input clock IN and an inverted clock CKB having a phase opposite to that of the input clock IN. That is, when the input clock IN is at the “H” level and the inverted clock CKB is at the “L” level, the transfer gate 31 is on and the transfer gate 32 is off. Conversely, when the input clock IN is at the “L” level and the inverted clock CKB is at the “H” level, the transfer gate 31 is off and the transfer gate 32 is on. The selector 30 selects one of the data held in the master latch 10 and the slave latch 20 using the input clock IN as a selector signal,
The selected signal is output via the inverter 33.

The counter circuit according to the present embodiment is similar to the counter circuit shown in FIG.
In the DBL-F / F shown in (1), the data input terminal of the shorted parallel latch is separated into two, and the input data of the master latch 10 on the side that holds the input data during the “H” level period of the input clock IN VDD (logical value "1"), and GND (logical value "0") as input data of the slave latch 20 that holds input data during the "L" level period of the input clock IN. .

With such a structure, a counter circuit is constructed in which a rising edge is output once every time the total of the rising and falling edges of the input clock IN counts 2, as in the conventional circuit. The rising edge of the input clock IN and the rising edge of the counter output can be synchronized without providing an initial value reset mechanism (a mechanism for setting an initial value at the start of the operation of the counter circuit).

(Second Embodiment) In a second embodiment, a divide-by-2 circuit using the counter circuit of the first embodiment will be described.

FIG. 2 is a circuit diagram of a divide-by-2 circuit according to a second embodiment of the present invention, and FIG. 3 is an operation waveform diagram thereof.

The divide-by-2 circuit includes a counter section 50 composed of the counter circuit shown in FIG. 1 and an output edge generating section for detecting the rising edge of the output by the F / F circuit 61 and inverting the output of the frequency divider. 60.

Specifically, the data output from the output inverter 33 of the counter unit 50 is
0 is input to the clock terminal CK of the F / F circuit 61. The output terminal Q of the F / F circuit 61 is connected to the inverter 6
2 and a feedback connection with the data terminal D.

With such a structure, the output OUT of the frequency divider can be output only at the rising edge of the input clock IN.
The edge of (f / 2) changes. T2 in FIG. 3 is the operation delay of the divide-by-2 circuit. Further, since the output of the frequency divider OUT changes at the rising edge of the input clock IN in this two-frequency divider, the phase relationship between IN and OUT in the operation waveform diagram shown in FIG. I can't get it.

Next, the advantage of the ２ frequency divider of the present embodiment shown in the figure will be explained by the two conventional examples described above (FIG. 9A,
Details will be mentioned in comparison with (b)).

In the case where the divide-by-2 circuit shown in FIG. 9A is used, in order to realize a divided edge in which the divided output changes only at the rising edge of the input clock of the divider, It was necessary to provide an initial value reset mechanism for the counter section of the frequency divider. On the other hand, when the frequency divider shown in FIG. 2 is configured using the counter circuit shown in FIG. 1, the circuit configuration itself realizes a mechanism for guaranteeing a frequency-divided edge. Since there is no reset mechanism as in the conventional example shown in a), it is possible to reduce the number of elements and area of the frequency dividing circuit itself, and it is not necessary to design and control a complicated reset signal supply system. There is.

On the other hand, when the conventional divide-by-2 circuit shown in FIG. 9 (b) is used, the circuit has a configuration such as a 2n + 1 divider and a counter section and an output edge generating section. Absent. Therefore, when a 2n + 1 frequency divider and a frequency divider pair are configured, a difference occurs in the frequency divider delay from the input clock to the output clock between the two frequency dividers. The timing design when performing data transfer between driven logic circuits has been complicated. On the other hand, when the 2 frequency divider as in the present embodiment is used, the structure is the same as that of the 2n + 1 frequency divider, ie, the counter section + the output edge generating section. It is possible to eliminate the difference in the frequency divider delay from the input clock to the output clock. This is shown by the operation waveforms shown in FIG. 3, in which the delay time t2 in the figure becomes equal to t3 in FIG. 7B. This facilitates timing design between logic circuits driven by each clock signal before frequency division.

(Third Embodiment) In a third embodiment, a clock supply circuit using the divide-by-2 circuit of the second embodiment will be described.

FIG. 4 is a block diagram of a clock supply circuit according to a third embodiment of the present invention.

This clock supply circuit includes the frequency divider 70 of the present invention shown in FIG. 2, the conventional 2n + 1 frequency divider 80 shown in FIG. 7, and a PLL circuit 90 connected to the output side. It is configured.

The 2 frequency divider 70 and the 2n + 1 frequency divider 80
Clock signals Y of frequencies 2f and (2n + 1) f, respectively
in, Xin are both clocks Y (f), X of frequency f
(F). Then, the PLL circuit 90 performs phase matching between the clock Y (f) output from the frequency divider 2 and the clock X (f) output from the 2n + 1 frequency divider 80, and outputs an output clock Z.

With the above configuration, only the rising edge of the clock Xin is always synchronized with the rising and falling edges of the clock Yin without skew.

As described above, in the present embodiment, the 2n + 1 frequency divider shown in FIG. 7 and the 2 frequency divider shown in FIG. 2 are combined to generate the frequency-divided clock to the PLL circuit input.
Without the reset signal, the correspondence of the clock edges can be guaranteed so that only the rising edge of the clock signal Xin is always synchronized with the rising and falling edges of the clock signal Yin, and skew occurs between the corresponding clock edges. No clock supply circuit can be configured.

[0057]

As described in detail above, according to the counter circuit of the first invention, the input clock can be set without providing an initial value reset mechanism (a mechanism for setting an initial value at the start of operation of the counter circuit). , The correspondence between the rising edge and the falling edge of the output data with respect to the rising edge and the falling edge of the output data can be always kept constant.

According to the divide-by-two logic circuit according to the second aspect of the present invention, even if the counter unit is not provided with the initial value reset mechanism,
It is possible to guarantee a frequency-divided edge that causes an output change only at the rising edge of the input clock.
Since the initial value reset mechanism is unnecessary, the number of elements in the circuit itself is reduced,
Not only can the area be reduced, but there is no need to design and control a complicated reset signal supply system. Furthermore, 2n
In the case of forming a +1 frequency-dividing logic circuit and a frequency-dividing circuit pair, only one rising or falling edge of the input clock (frequency f) to the 2 frequency-dividing logic circuit is set to the other 2n + 1 Frequency division that is always synchronized with the rising and falling edges of the input clock (frequency f ′, f: f ′ = 2: 2n + 1) to the frequency divider logic circuit and that there is no difference in the frequency divider circuit delay between the two frequency dividers Circuit pairs can be configured.

According to the clock signal supply circuit of the third aspect of the present invention, even if there is no reset signal, the rising edge of one clock is always synchronized with the rising edge and the falling edge of the other clock. This has the effect that the correspondence can be guaranteed and no skew occurs between the corresponding clock edges.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a counter circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a divide-by-2 circuit according to a second embodiment of the present invention.

3 is an operation waveform diagram of the divide-by-2 circuit shown in FIG. 2;

FIG. 4 is a block diagram of a clock supply circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram of a conventional clock supply circuit.

FIG. 6 is a diagram showing a phase relationship between input / output clock waveforms of a 2 frequency divider and a 3 frequency divider.

FIG. 7 is a diagram relating to a conventional frequency divider of 3;

FIG. 8 is a circuit diagram of a conventional F / F and a DBL F / F.

FIG. 9 is a circuit diagram of a conventional frequency divider.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Master latch 20 Slave latch 30 Selector 50 Counter part 60 Output edge generation part 70 2 frequency divider 80 2n + 1 frequency divider 90 PLL circuit

Claims (3)

[Claims] 1. A function of counting that the total number of rising and falling edges of an input clock is two, and a correspondence between a rising edge and a falling edge of output data with respect to a rising edge and a falling edge of the input clock. In a counter circuit whose relationship is always guaranteed to be constant, a first latch circuit that latches a first logical constant in synchronization with the input clock, and a second logical constant in synchronization with a different phase of the input clock. A second latch circuit for latching, and a selector circuit for selecting one of the outputs of the first and second latch circuits and outputting output data by using the input clock as a select signal. Counter circuit. 2. A counter section for outputting a rising edge or a falling edge once every two rising and falling edges of the input clock are counted, and a rising or falling edge from the counter section. A divide-by-two logic circuit comprising: an edge generation unit that detects an edge and inverts an output, wherein the counter unit is configured by the counter circuit according to claim 1. 3. The frequency f, f ′ (frequency ratio f: f ′ =
2: 2n + 1, n is a positive integer). The two-divided logic circuit and the 2n + 1-divided logic circuit for dividing the two types of clocks into 1/2 and 1 / (2n + 1), respectively. 3. A clock signal supply circuit comprising: a PLL circuit that inputs the same frequency clock signal after frequency division by the 2n + 1 frequency-dividing logic circuit and performs phase adjustment, wherein the two-frequency-dividing logic circuit is configured to divide by two according to claim 2. A clock signal supply circuit comprising a logic circuit.